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* [RESEND PATCHv2 1/3] drm/i915/dp: use fsleep instead of usleep_range for LT
@ 2024-11-04  3:58 Arun R Murthy
  2024-11-04  3:58 ` [RESEND PATCHv4 2/3] drm/i915/dp: read Aux RD interval just before setting the FFE preset Arun R Murthy
                   ` (4 more replies)
  0 siblings, 5 replies; 6+ messages in thread
From: Arun R Murthy @ 2024-11-04  3:58 UTC (permalink / raw)
  To: intel-xe, intel-gfx; +Cc: Arun R Murthy, Srikanth V NagaVenkata, Jani Nikula

Sleeping for < 10us use udelay, for 10us to 20ms use usleep_range() and
for > 10ms use msleep. flseep() will call the particular API based on
the above condition. (Documentation/timers/timers-howto.rst)
Aux RD Interval value depends on the value read from the dpcd register
which is updated from the sink device, hence use flseep.

Co-developed-by: Srikanth V NagaVenkata <nagavenkata.srikanth.v@intel.com>
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp_link_training.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index 397cc4ebae52..f41b69840ad9 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -898,7 +898,7 @@ intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
 
 	voltage_tries = 1;
 	for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
-		usleep_range(delay_us, 2 * delay_us);
+		fsleep(delay_us);
 
 		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
 						     link_status) < 0) {
@@ -1040,7 +1040,7 @@ intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
 	}
 
 	for (tries = 0; tries < 5; tries++) {
-		usleep_range(delay_us, 2 * delay_us);
+		fsleep(delay_us);
 
 		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
 						     link_status) < 0) {
@@ -1417,7 +1417,7 @@ intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp,
 	deadline = jiffies + msecs_to_jiffies_timeout(400);
 
 	for (try = 0; try < max_tries; try++) {
-		usleep_range(delay_us, 2 * delay_us);
+		fsleep(delay_us);
 
 		/*
 		 * The delay may get updated. The transmitter shall read the
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2024-11-05  4:27 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-11-04  3:58 [RESEND PATCHv2 1/3] drm/i915/dp: use fsleep instead of usleep_range for LT Arun R Murthy
2024-11-04  3:58 ` [RESEND PATCHv4 2/3] drm/i915/dp: read Aux RD interval just before setting the FFE preset Arun R Murthy
2024-11-04  3:58 ` [RESEND PATCHv2 3/3] drm/i915/dp: Include the time taken by AUX Tx for timeout Arun R Murthy
2024-11-04 14:31 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [RESEND,PATCHv2,1/3] drm/i915/dp: use fsleep instead of usleep_range for LT Patchwork
2024-11-04 15:53 ` ✓ Fi.CI.BAT: success " Patchwork
2024-11-05  4:27 ` ✗ Fi.CI.IGT: failure " Patchwork

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