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From: Gustavo Sousa <gustavo.sousa@intel.com>
To: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Cc: Luca Coelho <luciano.coelho@intel.com>,
	Jani Nikula <jani.nikula@intel.com>
Subject: [PATCH v2 12/17] drm/i915/dmc_wl: Couple enable/disable with dynamic DC states
Date: Wed,  6 Nov 2024 18:50:38 -0300	[thread overview]
Message-ID: <20241106215231.103474-13-gustavo.sousa@intel.com> (raw)
In-Reply-To: <20241106215231.103474-1-gustavo.sousa@intel.com>

Enabling and disabling the DMC wakelock should be done as part of
enabling and disabling of dynamic DC states, respectively. We should not
enable or disable DMC wakelock independently of DC states, otherwise we
would risk ending up with an inconsistent state where dynamic DC states
are enabled and the DMC wakelock is disabled, going against current
recommendations and making MMIO transactions potentially slower. In
future display IPs that could have a worse outcome if DMC trap
implementation is completely removed.

So, let's make things safer by tying stuff together, removing the
independent calls, and also put warnings in place to detect inconsistent
calls.

Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power_well.c | 5 ++++-
 drivers/gpu/drm/i915/display/intel_dmc.c                | 4 ----
 drivers/gpu/drm/i915/display/intel_dmc_wl.c             | 6 ++++--
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 578959ff2d75..bdf6c690a03b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -988,6 +988,7 @@ void gen9_disable_dc_states(struct intel_display *display)
 	struct drm_i915_private *dev_priv = to_i915(display->drm);
 	struct i915_power_domains *power_domains = &display->power.domains;
 	struct intel_cdclk_config cdclk_config = {};
+	u32 old_state = power_domains->dc_state;
 
 	if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) {
 		tgl_disable_dc3co(display);
@@ -1003,7 +1004,9 @@ void gen9_disable_dc_states(struct intel_display *display)
 		return;
 	}
 
-	intel_dmc_wl_disable(display);
+	if (old_state == DC_STATE_EN_UPTO_DC5 ||
+	    old_state == DC_STATE_EN_UPTO_DC6)
+		intel_dmc_wl_disable(display);
 
 	intel_cdclk_get_cdclk(display, &cdclk_config);
 	/* Can't read out voltage_level so can't use intel_cdclk_changed() */
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 87bdacfd9edf..221d3abda791 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -638,8 +638,6 @@ void intel_dmc_disable_program(struct intel_display *display)
 	pipedmc_clock_gating_wa(display, true);
 	disable_all_event_handlers(display);
 	pipedmc_clock_gating_wa(display, false);
-
-	intel_dmc_wl_disable(display);
 }
 
 void assert_dmc_loaded(struct intel_display *display)
@@ -1146,8 +1144,6 @@ void intel_dmc_suspend(struct intel_display *display)
 	if (dmc)
 		flush_work(&dmc->work);
 
-	intel_dmc_wl_disable(display);
-
 	/* Drop the reference held in case DMC isn't loaded. */
 	if (!intel_dmc_has_payload(display))
 		intel_dmc_runtime_pm_put(display);
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
index b8887216a684..f2d64954916a 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
@@ -283,6 +283,7 @@ void intel_dmc_wl_init(struct intel_display *display)
 	refcount_set(&wl->refcount, 0);
 }
 
+/* Must only be called as part of enabling dynamic DC states. */
 void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state)
 {
 	struct intel_dmc_wl *wl = &display->wl;
@@ -295,7 +296,7 @@ void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state)
 
 	wl->dc_state = dc_state;
 
-	if (wl->enabled)
+	if (drm_WARN_ON(display->drm, wl->enabled))
 		goto out_unlock;
 
 	/*
@@ -328,6 +329,7 @@ void intel_dmc_wl_enable(struct intel_display *display, u32 dc_state)
 	spin_unlock_irqrestore(&wl->lock, flags);
 }
 
+/* Must only be called as part of disabling dynamic DC states. */
 void intel_dmc_wl_disable(struct intel_display *display)
 {
 	struct intel_dmc_wl *wl = &display->wl;
@@ -340,7 +342,7 @@ void intel_dmc_wl_disable(struct intel_display *display)
 
 	spin_lock_irqsave(&wl->lock, flags);
 
-	if (!wl->enabled)
+	if (drm_WARN_ON(display->drm, !wl->enabled))
 		goto out_unlock;
 
 	/* Disable wakelock in DMC */
-- 
2.47.0


  parent reply	other threads:[~2024-11-06 21:53 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-11-06 21:50 [PATCH v2 00/17] drm/i915/dmc_wl: Fixes and enablement for Xe3_LPD Gustavo Sousa
2024-11-06 21:50 ` [PATCH v2 01/17] drm/i915/dmc_wl: Use i915_mmio_reg_offset() instead of reg.reg Gustavo Sousa
2024-11-07  9:23   ` Jani Nikula
2024-11-07 10:39   ` Luca Coelho
2024-11-06 21:50 ` [PATCH v2 02/17] drm/xe: Mimic i915 behavior for non-sleeping MMIO wait Gustavo Sousa
2024-11-07 10:40   ` Luca Coelho
2024-11-06 21:50 ` [PATCH v2 03/17] drm/i915/dmc_wl: Use non-sleeping variant of " Gustavo Sousa
2024-11-07 10:42   ` Luca Coelho
2024-11-06 21:50 ` [PATCH v2 04/17] drm/i915/dmc_wl: Check for non-zero refcount in release work Gustavo Sousa
2024-11-06 21:50 ` [PATCH v2 05/17] drm/i915/dmc_wl: Get wakelock when disabling dynamic DC states Gustavo Sousa
2024-11-07 10:43   ` Luca Coelho
2024-11-06 21:50 ` [PATCH v2 06/17] drm/i915/dmc_wl: Use sentinel item for range tables Gustavo Sousa
2024-11-06 21:50 ` [PATCH v2 07/17] drm/i915/dmc_wl: Extract intel_dmc_wl_reg_in_range() Gustavo Sousa
2024-11-07 10:44   ` Luca Coelho
2024-11-06 21:50 ` [PATCH v2 08/17] drm/i915/dmc_wl: Rename lnl_wl_range to powered_off_ranges Gustavo Sousa
2024-11-07 10:46   ` Luca Coelho
2024-11-06 21:50 ` [PATCH v2 09/17] drm/i915/dmc_wl: Track registers touched by the DMC Gustavo Sousa
2024-11-07 10:47   ` Luca Coelho
2024-11-06 21:50 ` [PATCH v2 10/17] drm/i915/dmc_wl: Allow simpler syntax for single reg in range tables Gustavo Sousa
2024-11-07 10:48   ` Luca Coelho
2024-11-06 21:50 ` [PATCH v2 11/17] drm/i915/dmc_wl: Deal with existing references when disabling Gustavo Sousa
2024-11-06 21:50 ` Gustavo Sousa [this message]
2024-11-06 21:50 ` [PATCH v2 13/17] drm/i915/dmc_wl: Add and use HAS_DMC_WAKELOCK() Gustavo Sousa
2024-11-07 10:49   ` Luca Coelho
2024-11-06 21:50 ` [PATCH v2 14/17] drm/i915/dmc_wl: Init only after we have runtime device info Gustavo Sousa
2024-11-07 10:50   ` Luca Coelho
2024-11-06 21:50 ` [PATCH v2 15/17] drm/i915/dmc_wl: Use HAS_DMC() in HAS_DMC_WAKELOCK() Gustavo Sousa
2024-11-07 10:51   ` Luca Coelho
2024-11-06 21:50 ` [PATCH v2 16/17] drm/i915/dmc_wl: Sanitize enable_dmc_wl according to hardware support Gustavo Sousa
2024-11-06 21:50 ` [PATCH v2 17/17] drm/i915/xe3lpd: Use DMC wakelock by default Gustavo Sousa
2024-11-07 10:51   ` Luca Coelho
2024-11-06 22:24 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dmc_wl: Fixes and enablement for Xe3_LPD (rev2) Patchwork
2024-11-06 22:24 ` ✗ Fi.CI.SPARSE: " Patchwork
2024-11-06 22:46 ` ✗ Fi.CI.BAT: failure " Patchwork
2024-11-07 18:36   ` Gustavo Sousa

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