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From: Uma Shankar <uma.shankar@intel.com>
To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
	intel-xe@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, harry.wentland@amd.com,
	pekka.paalanen@haloniitty.fi, sebastian.wick@redhat.com,
	jadahl@redhat.com, mwen@igalia.com, contact@emersion.fr,
	naveen1.kumar@intel.com,
	Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>,
	Uma Shankar <uma.shankar@intel.com>
Subject: [v4 18/23] drm/i915/color: Add framework to program PRE/POST CSC LUT
Date: Wed, 12 Mar 2025 12:54:20 +0530	[thread overview]
Message-ID: <20250312072425.3099205-19-uma.shankar@intel.com> (raw)
In-Reply-To: <20250312072425.3099205-1-uma.shankar@intel.com>

From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>

Add framework that will help in loading LUT to Pre/Post CSC color
blocks.

Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 27 ++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_color.h |  2 ++
 2 files changed, 29 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 9fe5f29c9e68..b650a4d76be4 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -91,6 +91,10 @@ struct intel_color_funcs {
 	/* Plane CSC*/
 	void (*load_plane_csc_matrix)(const struct drm_plane_state *plane_state,
 				      const struct drm_property_blob *blob);
+
+	/* Plane Pre/Post CSC */
+	void (*load_plane_luts)(const struct drm_plane_state *plane_state,
+				const struct drm_property_blob *blob, bool is_pre_csc);
 };
 
 #define CTM_COEFF_SIGN	(1ULL << 63)
@@ -3903,6 +3907,20 @@ void intel_color_load_plane_csc_matrix(const struct drm_plane_state *plane_state
 		i915->display.funcs.color->load_plane_csc_matrix(plane_state, blob);
 }
 
+static void xelpd_plane_load_luts(const struct drm_plane_state *plane_state,
+				  const struct drm_property_blob *blob, bool is_pre_csc)
+{
+}
+
+void intel_color_load_plane_luts(const struct drm_plane_state *plane_state,
+				 const struct drm_property_blob *blob, bool is_pre_csc)
+{
+	struct drm_i915_private *i915 = to_i915(plane_state->plane->dev);
+
+	if (i915->display.funcs.color->load_plane_luts)
+		i915->display.funcs.color->load_plane_luts(plane_state, blob, is_pre_csc);
+}
+
 static const struct intel_color_funcs chv_color_funcs = {
 	.color_check = chv_color_check,
 	.color_commit_arm = i9xx_color_commit_arm,
@@ -3962,6 +3980,7 @@ static const struct intel_color_funcs xelpd_color_funcs = {
 	.read_csc = icl_read_csc,
 	.get_config = skl_get_config,
 	.load_plane_csc_matrix = xelpd_load_plane_csc_matrix,
+	.load_plane_luts = xelpd_plane_load_luts,
 };
 
 static const struct intel_color_funcs icl_color_funcs = {
@@ -4226,6 +4245,14 @@ static void apply_colorop(const struct drm_plane_state *plane_state,
 		(*plane_color_ctl) |= PLANE_COLOR_PLANE_CSC_ENABLE;
 		if (state->data && intel_colorop->id == CB_PLANE_CSC)
 			intel_color_load_plane_csc_matrix(plane_state, state->data);
+	} else if (colorop->type == DRM_COLOROP_1D_LUT_MULTSEG) {
+		if (state->data && intel_colorop->id == CB_PLANE_PRE_CSC_LUT) {
+			(*plane_color_ctl) |= PLANE_COLOR_PRE_CSC_GAMMA_ENABLE;
+			intel_color_load_plane_luts(plane_state, state->data, true);
+		} else if (state->data && intel_colorop->id == CB_PLANE_POST_CSC_LUT) {
+			(*plane_color_ctl) &= ~PLANE_COLOR_PLANE_GAMMA_DISABLE;
+			intel_color_load_plane_luts(plane_state, state->data, false);
+		}
 	}
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_color.h b/drivers/gpu/drm/i915/display/intel_color.h
index c8d4f23cfb99..5e9a6f2f2ad1 100644
--- a/drivers/gpu/drm/i915/display/intel_color.h
+++ b/drivers/gpu/drm/i915/display/intel_color.h
@@ -52,4 +52,6 @@ void intel_program_pipeline(const struct drm_plane_state *plane_state,
 			    u32 *plane_color_ctl);
 void intel_color_load_plane_csc_matrix(const struct drm_plane_state *plane_state,
 				       const struct drm_property_blob *blob);
+void intel_color_load_plane_luts(const struct drm_plane_state *plane_state,
+				 const struct drm_property_blob *blob, bool is_pre_csc);
 #endif /* __INTEL_COLOR_H__ */
-- 
2.42.0


  parent reply	other threads:[~2025-03-12  7:13 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-12  7:24 [v4 00/23] Plane Color Pipeline support for Intel platforms Uma Shankar
2025-03-12  7:24 ` [NOT FOR REVIEW] [v4 01/23] drm: color pipeline base work Uma Shankar
2025-03-12  7:24 ` [v4 02/23] drm: Add support for 3x3 CTM Uma Shankar
2025-03-12  7:24 ` [v4 03/23] drm: Add Enhanced LUT precision structure Uma Shankar
2025-03-12  7:24 ` [v4 04/23] drm: Add Color lut range attributes Uma Shankar
2025-03-12  7:24 ` [v4 05/23] drm: Add Color ops capability property Uma Shankar
2025-03-12  7:24 ` [v4 06/23] drm: Add 1D LUT multi-segmented color op Uma Shankar
2025-03-12  7:24 ` [v4 07/23] drm: Define helper to initialize segmented 1D LUT Uma Shankar
2025-03-12  7:24 ` [v4 08/23] drm/i915: Add identifiers for intel color blocks Uma Shankar
2025-03-12  7:24 ` [v4 09/23] drm/i915: Add intel_color_op Uma Shankar
2025-03-12  7:24 ` [v4 10/23] drm/i915/color: Add helper to create intel colorop Uma Shankar
2025-03-12  7:24 ` [v4 11/23] drm/i915/color: Create a transfer function color pipeline Uma Shankar
2025-03-12  7:24 ` [v4 12/23] drm/i915/color: Add and attach COLORPIPELINE plane property Uma Shankar
2025-03-12  7:24 ` [v4 13/23] drm/i915/color: Add framework to set colorop Uma Shankar
2025-03-12  7:24 ` [v4 14/23] drm/i915/color: Add callbacks to set plane CTM Uma Shankar
2025-03-12  7:24 ` [v4 15/23] drm/i915/color: Add new color callbacks for Xelpd Uma Shankar
2025-03-12  7:24 ` [v4 16/23] drm/i915/color: Add plane CTM callback for D13 and beyond Uma Shankar
2025-03-12  7:24 ` [v4 17/23] drm/i915: Add register definitions for Plane Degamma Uma Shankar
2025-03-12  7:24 ` Uma Shankar [this message]
2025-03-12  7:24 ` [v4 19/23] drm/i915: Add register definitions for Plane Post CSC Uma Shankar
2025-03-12  7:24 ` [v4 20/23] drm/i915/color: Program Pre-CSC registers Uma Shankar
2025-03-12  7:24 ` [v4 21/23] drm/i915/xelpd: Program Plane Post CSC Registers Uma Shankar
2025-03-12  7:24 ` [v4 22/23] drm/i915/color: Enable Plane Color Pipelines Uma Shankar
2025-03-12  7:24 ` [v4 23/23] drm/doc/rfc: Add documentation for multi-segmented 1D LUT Uma Shankar
2025-03-12  7:56 ` ✗ Fi.CI.CHECKPATCH: warning for Plane Color Pipeline support for Intel platforms (rev4) Patchwork
2025-03-12  7:56 ` ✗ Fi.CI.SPARSE: " Patchwork
2025-03-12  8:53 ` ✓ i915.CI.BAT: success " Patchwork

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