From: Uma Shankar <uma.shankar@intel.com>
To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
intel-xe@lists.freedesktop.org
Cc: ville.syrjala@linux.intel.com, harry.wentland@amd.com,
pekka.paalanen@haloniitty.fi, sebastian.wick@redhat.com,
jadahl@redhat.com, mwen@igalia.com, contact@emersion.fr,
naveen1.kumar@intel.com,
Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>,
Uma Shankar <uma.shankar@intel.com>
Subject: [v4 06/23] drm: Add 1D LUT multi-segmented color op
Date: Wed, 12 Mar 2025 12:54:08 +0530 [thread overview]
Message-ID: <20250312072425.3099205-7-uma.shankar@intel.com> (raw)
In-Reply-To: <20250312072425.3099205-1-uma.shankar@intel.com>
From: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Add support for color ops that can be programmed
by 1 dimensional multi segmented Look Up Tables.
v2: Fixed the documentation for Multi segmented lut (Dmitry)
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
---
drivers/gpu/drm/drm_atomic.c | 4 ++++
drivers/gpu/drm/drm_atomic_uapi.c | 3 +++
include/uapi/drm/drm_mode.h | 10 ++++++++++
3 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/drm_atomic.c b/drivers/gpu/drm/drm_atomic.c
index ab7d2ed9ee8c..c79ed3551abc 100644
--- a/drivers/gpu/drm/drm_atomic.c
+++ b/drivers/gpu/drm/drm_atomic.c
@@ -800,6 +800,10 @@ static void drm_atomic_colorop_print_state(struct drm_printer *p,
drm_get_colorop_lut1d_interpolation_name(colorop->lut1d_interpolation));
drm_printf(p, "\tdata blob id=%d\n", state->data ? state->data->base.id : 0);
break;
+ case DRM_COLOROP_1D_LUT_MULTSEG:
+ drm_printf(p, "\thw cap blob id=%d\n", state->hw_caps ? state->hw_caps->base.id : 0);
+ drm_printf(p, "\tdata blob id=%d\n", state->data ? state->data->base.id : 0);
+ break;
case DRM_COLOROP_CTM_3X3:
drm_printf(p, "\tdata blob id=%d\n", state->data ? state->data->base.id : 0);
break;
diff --git a/drivers/gpu/drm/drm_atomic_uapi.c b/drivers/gpu/drm/drm_atomic_uapi.c
index 14d7939780db..d9eee683b1f2 100644
--- a/drivers/gpu/drm/drm_atomic_uapi.c
+++ b/drivers/gpu/drm/drm_atomic_uapi.c
@@ -715,6 +715,9 @@ static int drm_atomic_color_set_data_property(struct drm_colorop *colorop,
size = colorop->lut_size * colorop->lut_size * colorop->lut_size *
sizeof(struct drm_color_lut);
break;
+ case DRM_COLOROP_1D_LUT_MULTSEG:
+ elem_size = sizeof(struct drm_color_lut_32);
+ break;
default:
/* should never get here */
return -EINVAL;
diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h
index 9ba64d5b20c8..bd58c9f5f98d 100644
--- a/include/uapi/drm/drm_mode.h
+++ b/include/uapi/drm/drm_mode.h
@@ -923,6 +923,16 @@ enum drm_colorop_type {
*/
DRM_COLOROP_CTM_3X4,
+ /**
+ * @DRM_COLOROP_1D_LUT_MULTSEG:
+ *
+ * A 1D LUT with multiple segments to cover the full color range with non-uniformly
+ * distributed &drm_color_lut entries, packed into a blob via the DATA property.
+ * The driver's expected LUT size and segmented capabilities are advertised via the
+ * HW_CAPS property.
+ */
+ DRM_COLOROP_1D_LUT_MULTSEG,
+
/**
* @DRM_COLOROP_CTM_3X3:
*
--
2.42.0
next prev parent reply other threads:[~2025-03-12 7:12 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-12 7:24 [v4 00/23] Plane Color Pipeline support for Intel platforms Uma Shankar
2025-03-12 7:24 ` [NOT FOR REVIEW] [v4 01/23] drm: color pipeline base work Uma Shankar
2025-03-12 7:24 ` [v4 02/23] drm: Add support for 3x3 CTM Uma Shankar
2025-03-12 7:24 ` [v4 03/23] drm: Add Enhanced LUT precision structure Uma Shankar
2025-03-12 7:24 ` [v4 04/23] drm: Add Color lut range attributes Uma Shankar
2025-03-12 7:24 ` [v4 05/23] drm: Add Color ops capability property Uma Shankar
2025-03-12 7:24 ` Uma Shankar [this message]
2025-03-12 7:24 ` [v4 07/23] drm: Define helper to initialize segmented 1D LUT Uma Shankar
2025-03-12 7:24 ` [v4 08/23] drm/i915: Add identifiers for intel color blocks Uma Shankar
2025-03-12 7:24 ` [v4 09/23] drm/i915: Add intel_color_op Uma Shankar
2025-03-12 7:24 ` [v4 10/23] drm/i915/color: Add helper to create intel colorop Uma Shankar
2025-03-12 7:24 ` [v4 11/23] drm/i915/color: Create a transfer function color pipeline Uma Shankar
2025-03-12 7:24 ` [v4 12/23] drm/i915/color: Add and attach COLORPIPELINE plane property Uma Shankar
2025-03-12 7:24 ` [v4 13/23] drm/i915/color: Add framework to set colorop Uma Shankar
2025-03-12 7:24 ` [v4 14/23] drm/i915/color: Add callbacks to set plane CTM Uma Shankar
2025-03-12 7:24 ` [v4 15/23] drm/i915/color: Add new color callbacks for Xelpd Uma Shankar
2025-03-12 7:24 ` [v4 16/23] drm/i915/color: Add plane CTM callback for D13 and beyond Uma Shankar
2025-03-12 7:24 ` [v4 17/23] drm/i915: Add register definitions for Plane Degamma Uma Shankar
2025-03-12 7:24 ` [v4 18/23] drm/i915/color: Add framework to program PRE/POST CSC LUT Uma Shankar
2025-03-12 7:24 ` [v4 19/23] drm/i915: Add register definitions for Plane Post CSC Uma Shankar
2025-03-12 7:24 ` [v4 20/23] drm/i915/color: Program Pre-CSC registers Uma Shankar
2025-03-12 7:24 ` [v4 21/23] drm/i915/xelpd: Program Plane Post CSC Registers Uma Shankar
2025-03-12 7:24 ` [v4 22/23] drm/i915/color: Enable Plane Color Pipelines Uma Shankar
2025-03-12 7:24 ` [v4 23/23] drm/doc/rfc: Add documentation for multi-segmented 1D LUT Uma Shankar
2025-03-12 7:56 ` ✗ Fi.CI.CHECKPATCH: warning for Plane Color Pipeline support for Intel platforms (rev4) Patchwork
2025-03-12 7:56 ` ✗ Fi.CI.SPARSE: " Patchwork
2025-03-12 8:53 ` ✓ i915.CI.BAT: success " Patchwork
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