[PATCH] drm/i915/cx0: Convert C10 PHY PLL SSC state mismatch WARN to a debug message

[PATCH] drm/i915/cx0: Convert C10 PHY PLL SSC state mismatch WARN to a debug message

[Imre Deak]

On C10 PHY PLLs the SSC is enabled by programming the
XELPDP_PORT_CLOCK_CTL / XELPDP_SSC_ENABLE_PLLB flag and the
PHY_C10_VDR_PLL 4..8 registers:

- If SSC is enabled XELPDP_SSC_ENABLE_PLLB is set and the
  PHY_C10_VDR_PLL registers are programmed to non-zero values.
- If SSC is disabled XELPDP_SSC_ENABLE_PLLB is cleared and the
  PHY_C10_VDR_PLL registers are programmed to zeroed-out values.

The driver's state checker verifies if the above settings are consistent,
i.e. if XELPDP_SSC_ENABLE_PLLB being set corresponds to the
PHY_C10_VDR_PLL registers being zeroed-out or not.

On WCL the BIOS programs non-zero values to the PHY_C10_VDR_PLL 4..8
registers, but does not set the XELPDP_SSC_ENABLE_PLLB flag. This will
trigger the following PLL state check warning during driver loading:

<4>[   44.457809] xe 0000:00:02.0: [drm] PHY B: SSC enabled state (no), doesn't match PLL configuration (SSC-enabled)
<4>[   44.457833] WARNING: CPU: 4 PID: 298 at drivers/gpu/drm/i915/display/intel_cx0_phy.c:2281 intel_cx0pll_readout_hw_state+0x221/0x620 [xe]

It's not clear whether the HW uses the PHY_C10_VDR_PLL 4..8 register
values if the XELPDP_SSC_ENABLE_PLLB flag is cleared, or just ignores
them in this case. Since the driver always programs the register values
according to the above, it still makes sense to verify that the
programming happened correctly.

To avoid the state check WARN during driver loading due to the way BIOS
programs the registers, convert the WARN to a debug message.

Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 7bd17723e7abb..b973a9201edda 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2278,11 +2278,12 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
 	pll_state->clock = intel_c10pll_calc_port_clock(encoder, pll_state);
 
 	cx0pll_state->ssc_enabled = readout_ssc_state(encoder, true);
-	drm_WARN(display->drm,
-		 cx0pll_state->ssc_enabled != intel_c10pll_ssc_enabled(pll_state),
-		 "PHY %c: SSC enabled state (%s), doesn't match PLL configuration (%s)\n",
-		 phy_name(phy), str_yes_no(cx0pll_state->ssc_enabled),
-		 intel_c10pll_ssc_enabled(pll_state) ? "SSC-enabled" : "SSC-disabled");
+
+	if (cx0pll_state->ssc_enabled != intel_c10pll_ssc_enabled(pll_state))
+		drm_dbg_kms(display->drm,
+			    "PHY %c: SSC enabled state (%s), doesn't match PLL configuration (%s)\n",
+			    phy_name(phy), str_yes_no(cx0pll_state->ssc_enabled),
+			    intel_c10pll_ssc_enabled(pll_state) ? "SSC-enabled" : "SSC-disabled");
 }
 
 static void intel_c10_pll_program(struct intel_display *display,
-- 
2.49.1

✗ i915.CI.BAT: failure for drm/i915/cx0: Convert C10 PHY PLL SSC state mismatch WARN to a debug message

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4732 bytes --]

== Series Details ==

Series: drm/i915/cx0: Convert C10 PHY PLL SSC state mismatch WARN to a debug message
URL   : https://patchwork.freedesktop.org/series/158575/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_17640 -> Patchwork_158575v1
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_158575v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_158575v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v1/index.html

Participating hosts (45 -> 44)
------------------------------

  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_158575v1:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_softpin@safe-alignment:
    - fi-hsw-4770:        [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17640/fi-hsw-4770/igt@gem_softpin@safe-alignment.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v1/fi-hsw-4770/igt@gem_softpin@safe-alignment.html

  
Known issues
------------

  Here are the changes found in Patchwork_158575v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@info:
    - fi-hsw-4770:        [PASS][3] -> [SKIP][4] ([i915#1849] / [i915#2582])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17640/fi-hsw-4770/igt@fbdev@info.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v1/fi-hsw-4770/igt@fbdev@info.html

  * igt@fbdev@nullptr:
    - fi-hsw-4770:        [PASS][5] -> [SKIP][6] ([i915#2582]) +3 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17640/fi-hsw-4770/igt@fbdev@nullptr.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v1/fi-hsw-4770/igt@fbdev@nullptr.html

  * igt@i915_selftest@live@mman:
    - bat-atsm-1:         NOTRUN -> [DMESG-FAIL][7] ([i915#14204])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v1/bat-atsm-1/igt@i915_selftest@live@mman.html

  * igt@i915_selftest@live@workarounds:
    - bat-arls-5:         [PASS][8] -> [DMESG-FAIL][9] ([i915#12061]) +1 other test dmesg-fail
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17640/bat-arls-5/igt@i915_selftest@live@workarounds.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v1/bat-arls-5/igt@i915_selftest@live@workarounds.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@requests:
    - bat-atsm-1:         [INCOMPLETE][10] -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17640/bat-atsm-1/igt@i915_selftest@live@requests.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v1/bat-atsm-1/igt@i915_selftest@live@requests.html

  * igt@kms_flip@basic-flip-vs-modeset:
    - fi-bsw-n3050:       [DMESG-WARN][12] ([i915#15371]) -> [PASS][13] +5 other tests pass
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17640/fi-bsw-n3050/igt@kms_flip@basic-flip-vs-modeset.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v1/fi-bsw-n3050/igt@kms_flip@basic-flip-vs-modeset.html

  
#### Warnings ####

  * igt@i915_selftest@live:
    - bat-atsm-1:         [INCOMPLETE][14] ([i915#12061] / [i915#15157]) -> [DMESG-FAIL][15] ([i915#12061] / [i915#14204])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17640/bat-atsm-1/igt@i915_selftest@live.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v1/bat-atsm-1/igt@i915_selftest@live.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#14204]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14204
  [i915#15157]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15157
  [i915#15371]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15371
  [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
  [i915#2582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2582


Build changes
-------------

  * Linux: CI_DRM_17640 -> Patchwork_158575v1

  CI-20190529: 20190529
  CI_DRM_17640: a36e2c7fed2132052900236e8c7aa563d339baaf @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8655: 8655
  Patchwork_158575v1: a36e2c7fed2132052900236e8c7aa563d339baaf @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v1/index.html

[-- Attachment #2: Type: text/html, Size: 5826 bytes --]

Re: [PATCH] drm/i915/cx0: Convert C10 PHY PLL SSC state mismatch WARN to a debug message

[Jani Nikula]

On Fri, 05 Dec 2025, Imre Deak <imre.deak@intel.com> wrote:
> On C10 PHY PLLs the SSC is enabled by programming the
> XELPDP_PORT_CLOCK_CTL / XELPDP_SSC_ENABLE_PLLB flag and the
> PHY_C10_VDR_PLL 4..8 registers:
>
> - If SSC is enabled XELPDP_SSC_ENABLE_PLLB is set and the
>   PHY_C10_VDR_PLL registers are programmed to non-zero values.
> - If SSC is disabled XELPDP_SSC_ENABLE_PLLB is cleared and the
>   PHY_C10_VDR_PLL registers are programmed to zeroed-out values.
>
> The driver's state checker verifies if the above settings are consistent,
> i.e. if XELPDP_SSC_ENABLE_PLLB being set corresponds to the
> PHY_C10_VDR_PLL registers being zeroed-out or not.
>
> On WCL the BIOS programs non-zero values to the PHY_C10_VDR_PLL 4..8
> registers, but does not set the XELPDP_SSC_ENABLE_PLLB flag. This will
> trigger the following PLL state check warning during driver loading:
>
> <4>[   44.457809] xe 0000:00:02.0: [drm] PHY B: SSC enabled state (no), doesn't match PLL configuration (SSC-enabled)

BTW I also think the message is really confusing.

"SSC enabled state (no)" vs. "PLL configuration (SSC-enabled)".

*BOTH* need to say SSC with str_enabled_disabled() and ditch the clumsy
"SSC enabled state yes/no" and "SSC-enabled/SSC-disabled".

BR,
Jani.


> <4>[   44.457833] WARNING: CPU: 4 PID: 298 at drivers/gpu/drm/i915/display/intel_cx0_phy.c:2281 intel_cx0pll_readout_hw_state+0x221/0x620 [xe]
>
> It's not clear whether the HW uses the PHY_C10_VDR_PLL 4..8 register
> values if the XELPDP_SSC_ENABLE_PLLB flag is cleared, or just ignores
> them in this case. Since the driver always programs the register values
> according to the above, it still makes sense to verify that the
> programming happened correctly.
>
> To avoid the state check WARN during driver loading due to the way BIOS
> programs the registers, convert the WARN to a debug message.
>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index 7bd17723e7abb..b973a9201edda 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -2278,11 +2278,12 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
>  	pll_state->clock = intel_c10pll_calc_port_clock(encoder, pll_state);
>  
>  	cx0pll_state->ssc_enabled = readout_ssc_state(encoder, true);
> -	drm_WARN(display->drm,
> -		 cx0pll_state->ssc_enabled != intel_c10pll_ssc_enabled(pll_state),
> -		 "PHY %c: SSC enabled state (%s), doesn't match PLL configuration (%s)\n",
> -		 phy_name(phy), str_yes_no(cx0pll_state->ssc_enabled),
> -		 intel_c10pll_ssc_enabled(pll_state) ? "SSC-enabled" : "SSC-disabled");
> +
> +	if (cx0pll_state->ssc_enabled != intel_c10pll_ssc_enabled(pll_state))
> +		drm_dbg_kms(display->drm,
> +			    "PHY %c: SSC enabled state (%s), doesn't match PLL configuration (%s)\n",
> +			    phy_name(phy), str_yes_no(cx0pll_state->ssc_enabled),
> +			    intel_c10pll_ssc_enabled(pll_state) ? "SSC-enabled" : "SSC-disabled");
>  }
>  
>  static void intel_c10_pll_program(struct intel_display *display,

-- 
Jani Nikula, Intel

Re: [PATCH] drm/i915/cx0: Convert C10 PHY PLL SSC state mismatch WARN to a debug message

[Imre Deak]

On Mon, Dec 08, 2025 at 02:03:15PM +0200, Jani Nikula wrote:
> On Fri, 05 Dec 2025, Imre Deak <imre.deak@intel.com> wrote:
> > On C10 PHY PLLs the SSC is enabled by programming the
> > XELPDP_PORT_CLOCK_CTL / XELPDP_SSC_ENABLE_PLLB flag and the
> > PHY_C10_VDR_PLL 4..8 registers:
> >
> > - If SSC is enabled XELPDP_SSC_ENABLE_PLLB is set and the
> >   PHY_C10_VDR_PLL registers are programmed to non-zero values.
> > - If SSC is disabled XELPDP_SSC_ENABLE_PLLB is cleared and the
> >   PHY_C10_VDR_PLL registers are programmed to zeroed-out values.
> >
> > The driver's state checker verifies if the above settings are consistent,
> > i.e. if XELPDP_SSC_ENABLE_PLLB being set corresponds to the
> > PHY_C10_VDR_PLL registers being zeroed-out or not.
> >
> > On WCL the BIOS programs non-zero values to the PHY_C10_VDR_PLL 4..8
> > registers, but does not set the XELPDP_SSC_ENABLE_PLLB flag. This will
> > trigger the following PLL state check warning during driver loading:
> >
> > <4>[   44.457809] xe 0000:00:02.0: [drm] PHY B: SSC enabled state (no), doesn't match PLL configuration (SSC-enabled)
> 
> BTW I also think the message is really confusing.
> 
> "SSC enabled state (no)" vs. "PLL configuration (SSC-enabled)".
> 
> *BOTH* need to say SSC with str_enabled_disabled() and ditch the clumsy
> "SSC enabled state yes/no" and "SSC-enabled/SSC-disabled".

Makes sense, can change it to:
if (cx0pll_state->ssc_enabled != intel_c10pll_ssc_enabled(pll_state))
	drm_dbg_kms(display->drm,
		    "PHY %c: SSC state mismatch: port SSC is %s, PLL SSC is %s\n",
		    phy_name(phy),
		    str_enabled_disabled(cx0pll_state->ssc_enabled),
		    str_enabled_disabled(intel_c10pll_ssc_enabled(pll_state)));

> 
> BR,
> Jani.
> 
> 
> > <4>[   44.457833] WARNING: CPU: 4 PID: 298 at drivers/gpu/drm/i915/display/intel_cx0_phy.c:2281 intel_cx0pll_readout_hw_state+0x221/0x620 [xe]
> >
> > It's not clear whether the HW uses the PHY_C10_VDR_PLL 4..8 register
> > values if the XELPDP_SSC_ENABLE_PLLB flag is cleared, or just ignores
> > them in this case. Since the driver always programs the register values
> > according to the above, it still makes sense to verify that the
> > programming happened correctly.
> >
> > To avoid the state check WARN during driver loading due to the way BIOS
> > programs the registers, convert the WARN to a debug message.
> >
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 ++++++-----
> >  1 file changed, 6 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > index 7bd17723e7abb..b973a9201edda 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > @@ -2278,11 +2278,12 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
> >  	pll_state->clock = intel_c10pll_calc_port_clock(encoder, pll_state);
> >  
> >  	cx0pll_state->ssc_enabled = readout_ssc_state(encoder, true);
> > -	drm_WARN(display->drm,
> > -		 cx0pll_state->ssc_enabled != intel_c10pll_ssc_enabled(pll_state),
> > -		 "PHY %c: SSC enabled state (%s), doesn't match PLL configuration (%s)\n",
> > -		 phy_name(phy), str_yes_no(cx0pll_state->ssc_enabled),
> > -		 intel_c10pll_ssc_enabled(pll_state) ? "SSC-enabled" : "SSC-disabled");
> > +
> > +	if (cx0pll_state->ssc_enabled != intel_c10pll_ssc_enabled(pll_state))
> > +		drm_dbg_kms(display->drm,
> > +			    "PHY %c: SSC enabled state (%s), doesn't match PLL configuration (%s)\n",
> > +			    phy_name(phy), str_yes_no(cx0pll_state->ssc_enabled),
> > +			    intel_c10pll_ssc_enabled(pll_state) ? "SSC-enabled" : "SSC-disabled");
> >  }
> >  
> >  static void intel_c10_pll_program(struct intel_display *display,
> 
> -- 
> Jani Nikula, Intel

RE: [PATCH] drm/i915/cx0: Convert C10 PHY PLL SSC state mismatch WARN to a debug message

[Kahola, Mika]

> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Monday, 8 December 2025 14.59
> To: Jani Nikula <jani.nikula@linux.intel.com>
> Cc: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org; Kahola, Mika <mika.kahola@intel.com>
> Subject: Re: [PATCH] drm/i915/cx0: Convert C10 PHY PLL SSC state mismatch WARN to a debug message
> 
> On Mon, Dec 08, 2025 at 02:03:15PM +0200, Jani Nikula wrote:
> > On Fri, 05 Dec 2025, Imre Deak <imre.deak@intel.com> wrote:
> > > On C10 PHY PLLs the SSC is enabled by programming the
> > > XELPDP_PORT_CLOCK_CTL / XELPDP_SSC_ENABLE_PLLB flag and the
> > > PHY_C10_VDR_PLL 4..8 registers:
> > >
> > > - If SSC is enabled XELPDP_SSC_ENABLE_PLLB is set and the
> > >   PHY_C10_VDR_PLL registers are programmed to non-zero values.
> > > - If SSC is disabled XELPDP_SSC_ENABLE_PLLB is cleared and the
> > >   PHY_C10_VDR_PLL registers are programmed to zeroed-out values.
> > >
> > > The driver's state checker verifies if the above settings are
> > > consistent, i.e. if XELPDP_SSC_ENABLE_PLLB being set corresponds to
> > > the PHY_C10_VDR_PLL registers being zeroed-out or not.
> > >
> > > On WCL the BIOS programs non-zero values to the PHY_C10_VDR_PLL 4..8
> > > registers, but does not set the XELPDP_SSC_ENABLE_PLLB flag. This
> > > will trigger the following PLL state check warning during driver loading:
> > >
> > > <4>[   44.457809] xe 0000:00:02.0: [drm] PHY B: SSC enabled state (no), doesn't match PLL configuration (SSC-enabled)
> >
> > BTW I also think the message is really confusing.
> >
> > "SSC enabled state (no)" vs. "PLL configuration (SSC-enabled)".
> >
> > *BOTH* need to say SSC with str_enabled_disabled() and ditch the
> > clumsy "SSC enabled state yes/no" and "SSC-enabled/SSC-disabled".
> 
> Makes sense, can change it to:

> if (cx0pll_state->ssc_enabled != intel_c10pll_ssc_enabled(pll_state))
> 	drm_dbg_kms(display->drm,
> 		    "PHY %c: SSC state mismatch: port SSC is %s, PLL SSC is %s\n",
> 		    phy_name(phy),
> 		    str_enabled_disabled(cx0pll_state->ssc_enabled),
> 		    str_enabled_disabled(intel_c10pll_ssc_enabled(pll_state)));

With this change applied

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> 
> >
> > BR,
> > Jani.
> >
> >
> > > <4>[   44.457833] WARNING: CPU: 4 PID: 298 at drivers/gpu/drm/i915/display/intel_cx0_phy.c:2281
> intel_cx0pll_readout_hw_state+0x221/0x620 [xe]
> > >
> > > It's not clear whether the HW uses the PHY_C10_VDR_PLL 4..8 register
> > > values if the XELPDP_SSC_ENABLE_PLLB flag is cleared, or just
> > > ignores them in this case. Since the driver always programs the
> > > register values according to the above, it still makes sense to
> > > verify that the programming happened correctly.
> > >
> > > To avoid the state check WARN during driver loading due to the way
> > > BIOS programs the registers, convert the WARN to a debug message.
> > >
> > > Cc: Mika Kahola <mika.kahola@intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_cx0_phy.c | 11 ++++++-----
> > >  1 file changed, 6 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > index 7bd17723e7abb..b973a9201edda 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> > > @@ -2278,11 +2278,12 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
> > >  	pll_state->clock = intel_c10pll_calc_port_clock(encoder,
> > > pll_state);
> > >
> > >  	cx0pll_state->ssc_enabled = readout_ssc_state(encoder, true);
> > > -	drm_WARN(display->drm,
> > > -		 cx0pll_state->ssc_enabled != intel_c10pll_ssc_enabled(pll_state),
> > > -		 "PHY %c: SSC enabled state (%s), doesn't match PLL configuration (%s)\n",
> > > -		 phy_name(phy), str_yes_no(cx0pll_state->ssc_enabled),
> > > -		 intel_c10pll_ssc_enabled(pll_state) ? "SSC-enabled" : "SSC-disabled");
> > > +
> > > +	if (cx0pll_state->ssc_enabled != intel_c10pll_ssc_enabled(pll_state))
> > > +		drm_dbg_kms(display->drm,
> > > +			    "PHY %c: SSC enabled state (%s), doesn't match PLL configuration (%s)\n",
> > > +			    phy_name(phy), str_yes_no(cx0pll_state->ssc_enabled),
> > > +			    intel_c10pll_ssc_enabled(pll_state) ? "SSC-enabled" :
> > > +"SSC-disabled");
> > >  }
> > >
> > >  static void intel_c10_pll_program(struct intel_display *display,
> >
> > --
> > Jani Nikula, Intel

[PATCH v2] drm/i915/cx0: Convert C10 PHY PLL SSC state mismatch WARN to a debug message

[Imre Deak]

On C10 PHY PLLs the SSC is enabled by programming the
XELPDP_PORT_CLOCK_CTL / XELPDP_SSC_ENABLE_PLLB flag and the
PHY_C10_VDR_PLL 4..8 registers:

- If SSC is enabled XELPDP_SSC_ENABLE_PLLB is set and the
  PHY_C10_VDR_PLL registers are programmed to non-zero values.
- If SSC is disabled XELPDP_SSC_ENABLE_PLLB is cleared and the
  PHY_C10_VDR_PLL registers are programmed to zeroed-out values.

The driver's state checker verifies if the above settings are consistent,
i.e. if XELPDP_SSC_ENABLE_PLLB being set corresponds to the
PHY_C10_VDR_PLL registers being zeroed-out or not.

On WCL the BIOS programs non-zero values to the PHY_C10_VDR_PLL 4..8
registers, but does not set the XELPDP_SSC_ENABLE_PLLB flag. This will
trigger the following PLL state check warning during driver loading:

<4>[   44.457809] xe 0000:00:02.0: [drm] PHY B: SSC enabled state (no), doesn't match PLL configuration (SSC-enabled)
<4>[   44.457833] WARNING: CPU: 4 PID: 298 at drivers/gpu/drm/i915/display/intel_cx0_phy.c:2281 intel_cx0pll_readout_hw_state+0x221/0x620 [xe]

It's not clear whether the HW uses the PHY_C10_VDR_PLL 4..8 register
values if the XELPDP_SSC_ENABLE_PLLB flag is cleared, or just ignores
them in this case. Since the driver always programs the register values
according to the above, it still makes sense to verify that the
programming happened correctly.

To avoid the state check WARN during driver loading due to the way BIOS
programs the registers, convert the WARN to a debug message.

While at it clarify the debug message.

v2: Clarify the debug message. (Jani)

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cx0_phy.c | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 7bd17723e7abb..f6d69627154e5 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2278,11 +2278,13 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
 	pll_state->clock = intel_c10pll_calc_port_clock(encoder, pll_state);
 
 	cx0pll_state->ssc_enabled = readout_ssc_state(encoder, true);
-	drm_WARN(display->drm,
-		 cx0pll_state->ssc_enabled != intel_c10pll_ssc_enabled(pll_state),
-		 "PHY %c: SSC enabled state (%s), doesn't match PLL configuration (%s)\n",
-		 phy_name(phy), str_yes_no(cx0pll_state->ssc_enabled),
-		 intel_c10pll_ssc_enabled(pll_state) ? "SSC-enabled" : "SSC-disabled");
+
+	if (cx0pll_state->ssc_enabled != intel_c10pll_ssc_enabled(pll_state))
+		drm_dbg_kms(display->drm,
+			    "PHY %c: SSC state mismatch: port SSC is %s, PLL SSC is %s\n",
+			    phy_name(phy),
+			    str_enabled_disabled(cx0pll_state->ssc_enabled),
+			    str_enabled_disabled(intel_c10pll_ssc_enabled(pll_state)));
 }
 
 static void intel_c10_pll_program(struct intel_display *display,
-- 
2.49.1

✗ i915.CI.BAT: failure for drm/i915/cx0: Convert C10 PHY PLL SSC state mismatch WARN to a debug message (rev2)

[Patchwork]

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== Series Details ==

Series: drm/i915/cx0: Convert C10 PHY PLL SSC state mismatch WARN to a debug message (rev2)
URL   : https://patchwork.freedesktop.org/series/158575/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_17649 -> Patchwork_158575v2
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_158575v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_158575v2, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/index.html

Participating hosts (38 -> 5)
------------------------------

  ERROR: It appears as if the changes made in Patchwork_158575v2 prevented too many machines from booting.

  Additional (1): bat-adls-6 
  Missing    (34): fi-rkl-11600 bat-adlp-6 bat-mtlp-9 fi-bsw-n3050 bat-dg2-8 bat-dg2-9 fi-hsw-4770 fi-ivb-3770 bat-rplp-1 bat-rpls-4 bat-apl-1 bat-dg2-11 bat-arls-5 bat-arlh-2 bat-twl-2 fi-kbl-7567u bat-dg1-7 bat-kbl-2 bat-arlh-3 bat-adlp-9 fi-cfl-8700k fi-glk-j4005 bat-dg1-6 bat-arls-6 bat-jsl-1 bat-mtlp-8 bat-adlp-11 fi-tgl-1115g4 fi-cfl-guc bat-jsl-5 fi-kbl-x1275 fi-kbl-8809g bat-dg2-14 bat-dg2-13 

Known issues
------------

  Here are the changes found in Patchwork_158575v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_lmem_swapping@verify-random:
    - bat-adls-6:         NOTRUN -> [SKIP][1] ([i915#4613]) +3 other tests skip
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@gem_lmem_swapping@verify-random.html

  * igt@gem_tiled_pread_basic:
    - bat-adls-6:         NOTRUN -> [SKIP][2] ([i915#3282])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@gem_tiled_pread_basic.html

  * igt@i915_selftest@live:
    - bat-adls-6:         NOTRUN -> [ABORT][3] ([i915#15399]) +1 other test abort
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@i915_selftest@live.html

  * igt@intel_hwmon@hwmon-read:
    - bat-adls-6:         NOTRUN -> [SKIP][4] ([i915#7707]) +1 other test skip
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@intel_hwmon@hwmon-read.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - bat-adls-6:         NOTRUN -> [SKIP][5] ([i915#4103]) +1 other test skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dsc@dsc-basic:
    - bat-adls-6:         NOTRUN -> [SKIP][6] ([i915#3555] / [i915#3840])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@kms_dsc@dsc-basic.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-adls-6:         NOTRUN -> [SKIP][7]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_pm_backlight@basic-brightness:
    - bat-adls-6:         NOTRUN -> [SKIP][8] ([i915#5354])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_psr@psr-primary-mmap-gtt:
    - bat-adls-6:         NOTRUN -> [SKIP][9] ([i915#1072] / [i915#9732]) +3 other tests skip
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@kms_psr@psr-primary-mmap-gtt.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-adls-6:         NOTRUN -> [SKIP][10] ([i915#3555])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-read:
    - bat-adls-6:         NOTRUN -> [SKIP][11] ([i915#3291]) +2 other tests skip
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@prime_vgem@basic-fence-read.html

  
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#15399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15399
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732


Build changes
-------------

  * Linux: CI_DRM_17649 -> Patchwork_158575v2

  CI-20190529: 20190529
  CI_DRM_17649: 55b19373186bc09befbc0068ee82a67ed9cfbc66 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8659: 8659
  Patchwork_158575v2: 55b19373186bc09befbc0068ee82a67ed9cfbc66 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/index.html

[-- Attachment #2: Type: text/html, Size: 6369 bytes --]

Re: ✗ i915.CI.BAT: failure for drm/i915/cx0: Convert C10 PHY PLL SSC state mismatch WARN to a debug message (rev2)

[Imre Deak]

On Tue, Dec 09, 2025 at 06:40:46PM +0000, Patchwork wrote:
> == Series Details ==
> 
> Series: drm/i915/cx0: Convert C10 PHY PLL SSC state mismatch WARN to a debug message (rev2)
> URL   : https://patchwork.freedesktop.org/series/158575/
> State : failure

The patch is pushed to drm-intel-next, thanks for the reviews.

The failures are on hosts unrelated to the change.

> == Summary ==
> 
> CI Bug Log - changes from CI_DRM_17649 -> Patchwork_158575v2
> ====================================================
> 
> Summary
> -------
> 
>   **FAILURE**
> 
>   Serious unknown changes coming with Patchwork_158575v2 absolutely need to be
>   verified manually.
>   
>   If you think the reported changes have nothing to do with the changes
>   introduced in Patchwork_158575v2, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
>   to document this new failure mode, which will reduce false positives in CI.
> 
>   External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/index.html
> 
> Participating hosts (38 -> 5)
> ------------------------------
> 
>   ERROR: It appears as if the changes made in Patchwork_158575v2 prevented too many machines from booting.
> 
>   Additional (1): bat-adls-6 
>   Missing    (34): fi-rkl-11600 bat-adlp-6 bat-mtlp-9 fi-bsw-n3050 bat-dg2-8 bat-dg2-9 fi-hsw-4770 fi-ivb-3770 bat-rplp-1 bat-rpls-4 bat-apl-1 bat-dg2-11 bat-arls-5 bat-arlh-2 bat-twl-2 fi-kbl-7567u bat-dg1-7 bat-kbl-2 bat-arlh-3 bat-adlp-9 fi-cfl-8700k fi-glk-j4005 bat-dg1-6 bat-arls-6 bat-jsl-1 bat-mtlp-8 bat-adlp-11 fi-tgl-1115g4 fi-cfl-guc bat-jsl-5 fi-kbl-x1275 fi-kbl-8809g bat-dg2-14 bat-dg2-13 
> 
> Known issues
> ------------
> 
>   Here are the changes found in Patchwork_158575v2 that come from known issues:
> 
> ### IGT changes ###
> 
> #### Issues hit ####
> 
>   * igt@gem_lmem_swapping@verify-random:
>     - bat-adls-6:         NOTRUN -> [SKIP][1] ([i915#4613]) +3 other tests skip
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@gem_lmem_swapping@verify-random.html
> 
>   * igt@gem_tiled_pread_basic:
>     - bat-adls-6:         NOTRUN -> [SKIP][2] ([i915#3282])
>    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@gem_tiled_pread_basic.html
> 
>   * igt@i915_selftest@live:
>     - bat-adls-6:         NOTRUN -> [ABORT][3] ([i915#15399]) +1 other test abort
>    [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@i915_selftest@live.html
> 
>   * igt@intel_hwmon@hwmon-read:
>     - bat-adls-6:         NOTRUN -> [SKIP][4] ([i915#7707]) +1 other test skip
>    [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@intel_hwmon@hwmon-read.html
> 
>   * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
>     - bat-adls-6:         NOTRUN -> [SKIP][5] ([i915#4103]) +1 other test skip
>    [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
> 
>   * igt@kms_dsc@dsc-basic:
>     - bat-adls-6:         NOTRUN -> [SKIP][6] ([i915#3555] / [i915#3840])
>    [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@kms_dsc@dsc-basic.html
> 
>   * igt@kms_force_connector_basic@force-load-detect:
>     - bat-adls-6:         NOTRUN -> [SKIP][7]
>    [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@kms_force_connector_basic@force-load-detect.html
> 
>   * igt@kms_pm_backlight@basic-brightness:
>     - bat-adls-6:         NOTRUN -> [SKIP][8] ([i915#5354])
>    [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@kms_pm_backlight@basic-brightness.html
> 
>   * igt@kms_psr@psr-primary-mmap-gtt:
>     - bat-adls-6:         NOTRUN -> [SKIP][9] ([i915#1072] / [i915#9732]) +3 other tests skip
>    [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@kms_psr@psr-primary-mmap-gtt.html
> 
>   * igt@kms_setmode@basic-clone-single-crtc:
>     - bat-adls-6:         NOTRUN -> [SKIP][10] ([i915#3555])
>    [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@kms_setmode@basic-clone-single-crtc.html
> 
>   * igt@prime_vgem@basic-fence-read:
>     - bat-adls-6:         NOTRUN -> [SKIP][11] ([i915#3291]) +2 other tests skip
>    [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/bat-adls-6/igt@prime_vgem@basic-fence-read.html
> 
>   
>   [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
>   [i915#15399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15399
>   [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
>   [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
>   [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
>   [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
>   [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
>   [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
>   [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
>   [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
>   [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
> 
> 
> Build changes
> -------------
> 
>   * Linux: CI_DRM_17649 -> Patchwork_158575v2
> 
>   CI-20190529: 20190529
>   CI_DRM_17649: 55b19373186bc09befbc0068ee82a67ed9cfbc66 @ git://anongit.freedesktop.org/gfx-ci/linux
>   IGT_8659: 8659
>   Patchwork_158575v2: 55b19373186bc09befbc0068ee82a67ed9cfbc66 @ git://anongit.freedesktop.org/gfx-ci/linux
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_158575v2/index.html