[i915-rt v5 00/21] drm/i915/display: All patches to make PREEMPT_RT work on i915 + xe.

[i915-rt v5 00/21] drm/i915/display: All patches to make PREEMPT_RT work on i915 + xe.

[Maarten Lankhorst]

We should probably take the uncore lock only once, and hold it during
entire evasion. For now just remove the code using it to see if CI
passes.

Since last time, adjust some patches to compile again, and also
add a lockdep_reset() to make CI pass from repeatedly loading
the i915 module.

Maarten Lankhorst (16):
  drm/i915/display: Fix intel_lpe_audio_irq_handler for PREEMPT-RT
  drm/i915/display: Make get_vblank_counter use intel_de_read_fw()
  drm/i915/display: Use intel_de_write_fw in intel_pipe_fastset
  drm/i915/display: Make set_pipeconf use the fw variants
  drm/i915/display: Move vblank put until after critical section
  drm/i915/display: Remove locking from intel_vblank_evade critical
    section
  drm/i915/display: Handle vlv dsi workaround in scanline_in_safe_range
    too
  drm/i915/display: Make icl_dsi_frame_update use _fw too
  drm/i915/display: Enable interrupts earlier on PREEMPT_RT
  drm/i915/display: Use intel_de_read/write_fw in colorops
  drm/i915/gt: Fix selftests on PREEMPT_RT
  drm/i915/gt: Set stop_timeout() correctly on PREEMPT-RT
  drm/i915/display: Do not take uncore lock in i915_get_vblank_counter
  drm/i915/display: Remove uncore lock from vlv_atomic_update_fifo
  PREEMPT_RT injection
  FOR-CI: drm/i915: Reset lockdep after selftest unload

Mike Galbraith (1):
  drm/i915: Use preempt_disable/enable_rt() where recommended

Sebastian Andrzej Siewior (4):
  drm/i915/gt: Use spin_lock_irq() instead of local_irq_disable() +
    spin_lock()
  drm/i915: Drop the irqs_disabled() check
  drm/i915/guc: Consider also RCU depth in busy loop.
  Revert "drm/i915: Depend on !PREEMPT_RT."

 drivers/gpu/drm/i915/Kconfig                  |   1 -
 drivers/gpu/drm/i915/Kconfig.debug            |  15 ---
 drivers/gpu/drm/i915/display/i9xx_wm.c        |   4 -
 drivers/gpu/drm/i915/display/icl_dsi.c        |   4 +-
 drivers/gpu/drm/i915/display/intel_color.c    |   6 +-
 drivers/gpu/drm/i915/display/intel_crtc.c     |  12 +-
 drivers/gpu/drm/i915/display/intel_cursor.c   |   8 +-
 drivers/gpu/drm/i915/display/intel_de.h       |   8 ++
 drivers/gpu/drm/i915/display/intel_display.c  |  46 +++----
 .../gpu/drm/i915/display/intel_lpe_audio.c    |   2 +-
 drivers/gpu/drm/i915/display/intel_vblank.c   | 115 ++++++++++--------
 drivers/gpu/drm/i915/display/intel_vblank.h   |   1 +
 drivers/gpu/drm/i915/display/intel_vrr.c      |  16 +--
 drivers/gpu/drm/i915/gt/intel_engine_cs.c     |   2 +-
 .../drm/i915/gt/intel_execlists_submission.c  |  17 +--
 drivers/gpu/drm/i915/gt/selftest_engine_pm.c  |   8 +-
 drivers/gpu/drm/i915/gt/uc/intel_guc.h        |   2 +-
 drivers/gpu/drm/i915/i915_module.c            |   6 +
 drivers/gpu/drm/i915/i915_request.c           |   2 -
 drivers/gpu/drm/i915/intel_uncore.h           |  26 ++--
 drivers/gpu/drm/xe/Kconfig.debug              |   5 +
 .../drm/xe/compat-i915-headers/intel_uncore.h |   7 ++
 kernel/Kconfig.preempt                        |   4 +-
 23 files changed, 180 insertions(+), 137 deletions(-)

-- 
2.51.0

[i915-rt v5 01/21] drm/i915/display: Fix intel_lpe_audio_irq_handler for PREEMPT-RT

[Maarten Lankhorst]

The LPE audio interrupt comes from the i915 interrupt handler. It
should be in irq disabled context.

With PREEMPT_RT enabled, the IRQ handler is threaded.
Because intel_lpe_audio_irq_handler() may be called in threaded IRQ context,
generic_handle_irq_safe API disables the interrupts before calling LPE's
interrupt top half handler.

This fixes braswell audio issues with RT enabled.

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
Reviewed-by: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/i915/display/intel_lpe_audio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
index 5b41abe1c64d5..172c0062237eb 100644
--- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
@@ -262,7 +262,7 @@ void intel_lpe_audio_irq_handler(struct intel_display *display)
 	if (!HAS_LPE_AUDIO(display))
 		return;
 
-	ret = generic_handle_irq(display->audio.lpe.irq);
+	ret = generic_handle_irq_safe(display->audio.lpe.irq);
 	if (ret)
 		drm_err_ratelimited(display->drm,
 				    "error handling LPE audio irq: %d\n", ret);
-- 
2.51.0

RE: [i915-rt v5 01/21] drm/i915/display: Fix intel_lpe_audio_irq_handler for PREEMPT-RT

[Shankar, Uma]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Maarten
> Lankhorst
> Sent: Wednesday, January 21, 2026 7:23 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Maarten Lankhorst <dev@lankhorst.se>; Brost, Matthew
> <matthew.brost@intel.com>
> Subject: [i915-rt v5 01/21] drm/i915/display: Fix intel_lpe_audio_irq_handler for
> PREEMPT-RT
> 
> The LPE audio interrupt comes from the i915 interrupt handler. It should be in irq
> disabled context.
> 
> With PREEMPT_RT enabled, the IRQ handler is threaded.
> Because intel_lpe_audio_irq_handler() may be called in threaded IRQ context,
> generic_handle_irq_safe API disables the interrupts before calling LPE's interrupt
> top half handler.
> 
> This fixes braswell audio issues with RT enabled.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
> Reviewed-by: Matthew Brost <matthew.brost@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_lpe_audio.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c
> b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
> index 5b41abe1c64d5..172c0062237eb 100644
> --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c
> +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c
> @@ -262,7 +262,7 @@ void intel_lpe_audio_irq_handler(struct intel_display
> *display)
>  	if (!HAS_LPE_AUDIO(display))
>  		return;
> 
> -	ret = generic_handle_irq(display->audio.lpe.irq);
> +	ret = generic_handle_irq_safe(display->audio.lpe.irq);
>  	if (ret)
>  		drm_err_ratelimited(display->drm,
>  				    "error handling LPE audio irq: %d\n", ret);
> --
> 2.51.0

[i915-rt v5 02/21] drm/i915/display: Make get_vblank_counter use intel_de_read_fw()

[Maarten Lankhorst]

Fixes the following lockdep splat on PREEMPT_RT:
<3> BUG: sleeping function called from invalid context at kernel/locking/spinlock_rt.c:48
<3> in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 1373, name: xe_module_load
<3> preempt_count: 1, expected: 0
<3> RCU nest depth: 0, expected: 0
<4> 11 locks held by xe_module_load/1373:
<4>  #0: ffff888107b691a0 (&dev->mutex){....}-{3:3}, at: __driver_attach+0x104/0x220
<4>  #1: ffff88813cd30280 (&dev->clientlist_mutex){+.+.}-{3:3}, at: drm_client_register+0x32/0xe0
<4>  #2: ffffffff837f88f8 (registration_lock){+.+.}-{3:3}, at: register_framebuffer+0x1b/0x50
<4>  #3: ffffffff835985e0 (console_lock){+.+.}-{0:0}, at: fbcon_fb_registered+0x6f/0x90
<4>  #4: ffff88812589e6a0 (&helper->lock){+.+.}-{3:3}, at: __drm_fb_helper_restore_fbdev_mode_unlocked+0x7b/0x110
<4>  #5: ffff88813cd30158 (&dev->master_mutex){+.+.}-{3:3}, at: drm_master_internal_acquire+0x20/0x50
<4>  #6: ffff88812589e488 (&client->modeset_mutex){+.+.}-{3:3}, at: drm_client_modeset_commit_locked+0x2a/0x1b0
<4>  #7: ffffc9000031eef0 (crtc_ww_class_acquire){+.+.}-{0:0}, at: drm_client_modeset_commit_atomic+0x4c/0x2b0
<4>  #8: ffffc9000031ef18 (crtc_ww_class_mutex){+.+.}-{3:3}, at: drm_client_modeset_commit_atomic+0x4c/0x2b0
<4>  #9: ffff888114f7b8b8 (&intel_dp->psr.lock){+.+.}-{3:3}, at: intel_psr_lock+0xc5/0xf0 [xe]
<4>  #10: ffff88812a0cbbc0 (&wl->lock){+.+.}-{2:2}, at: intel_dmc_wl_get+0x3c/0x140 [xe]

This splat will happen otherwise on all tracepoints too, for similar reasons.

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/display/intel_vblank.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 1b7cfe226ff8f..a85796f9d29ba 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -132,7 +132,7 @@ u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
 	if (!vblank->max_vblank_count)
 		return 0;
 
-	return intel_de_read(display, PIPE_FRMCOUNT_G4X(display, pipe));
+	return intel_de_read_fw(display, PIPE_FRMCOUNT_G4X(display, pipe));
 }
 
 static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
-- 
2.51.0

RE: [i915-rt v5 02/21] drm/i915/display: Make get_vblank_counter use intel_de_read_fw()

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Maarten
> Lankhorst
> Sent: Wednesday, January 21, 2026 7:23 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Maarten Lankhorst <dev@lankhorst.se>
> Subject: [i915-rt v5 02/21] drm/i915/display: Make get_vblank_counter use
> intel_de_read_fw()
> 
> Fixes the following lockdep splat on PREEMPT_RT:
> <3> BUG: sleeping function called from invalid context at
> kernel/locking/spinlock_rt.c:48 <3> in_atomic(): 1, irqs_disabled(): 0, non_block:
> 0, pid: 1373, name: xe_module_load <3> preempt_count: 1, expected: 0 <3> RCU
> nest depth: 0, expected: 0 <4> 11 locks held by xe_module_load/1373:
> <4>  #0: ffff888107b691a0 (&dev->mutex){....}-{3:3}, at:
> __driver_attach+0x104/0x220 <4>  #1: ffff88813cd30280 (&dev-
> >clientlist_mutex){+.+.}-{3:3}, at: drm_client_register+0x32/0xe0 <4>  #2:
> ffffffff837f88f8 (registration_lock){+.+.}-{3:3}, at: register_framebuffer+0x1b/0x50
> <4>  #3: ffffffff835985e0 (console_lock){+.+.}-{0:0}, at:
> fbcon_fb_registered+0x6f/0x90 <4>  #4: ffff88812589e6a0 (&helper->lock){+.+.}-
> {3:3}, at: __drm_fb_helper_restore_fbdev_mode_unlocked+0x7b/0x110
> <4>  #5: ffff88813cd30158 (&dev->master_mutex){+.+.}-{3:3}, at:
> drm_master_internal_acquire+0x20/0x50
> <4>  #6: ffff88812589e488 (&client->modeset_mutex){+.+.}-{3:3}, at:
> drm_client_modeset_commit_locked+0x2a/0x1b0
> <4>  #7: ffffc9000031eef0 (crtc_ww_class_acquire){+.+.}-{0:0}, at:
> drm_client_modeset_commit_atomic+0x4c/0x2b0
> <4>  #8: ffffc9000031ef18 (crtc_ww_class_mutex){+.+.}-{3:3}, at:
> drm_client_modeset_commit_atomic+0x4c/0x2b0
> <4>  #9: ffff888114f7b8b8 (&intel_dp->psr.lock){+.+.}-{3:3}, at:
> intel_psr_lock+0xc5/0xf0 [xe] <4>  #10: ffff88812a0cbbc0 (&wl->lock){+.+.}-{2:2},
> at: intel_dmc_wl_get+0x3c/0x140 [xe]
> 
> This splat will happen otherwise on all tracepoints too, for similar reasons.
> 
> Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
> ---
>  drivers/gpu/drm/i915/display/intel_vblank.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c
> b/drivers/gpu/drm/i915/display/intel_vblank.c
> index 1b7cfe226ff8f..a85796f9d29ba 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -132,7 +132,7 @@ u32 g4x_get_vblank_counter(struct drm_crtc *crtc)
>  	if (!vblank->max_vblank_count)
>  		return 0;
> 
> -	return intel_de_read(display, PIPE_FRMCOUNT_G4X(display, pipe));
> +	return intel_de_read_fw(display, PIPE_FRMCOUNT_G4X(display, pipe));

Looks good to me. However, I think it will be good to limit this to RT.
Just to contain the impact and plan a soft landing.

Regards,
Uma Shankar

>  }
> 
>  static u32 intel_crtc_scanlines_since_frame_timestamp(struct intel_crtc *crtc)
> --
> 2.51.0

[i915-rt v5 03/21] drm/i915/display: Use intel_de_write_fw in intel_pipe_fastset

[Maarten Lankhorst]

intel_set_pipe_src_size(), hsw_set_linetime_wm(),
intel_cpu_transcoder_set_m1_n1() and intel_set_transcoder_timings_lrr()
are called from an atomic context on PREEMPT_RT, and should be using the
_fw functions.

This likely prevents a deadlock on i915.

Again noticed when trying to disable preemption in vblank evasion:
<3> BUG: sleeping function called from invalid context at kernel/locking/spinlock_rt.c:48
<3> in_atomic(): 1, irqs_disabled(): 0, non_block: 0, pid: 1505, name: kms_cursor_lega
<3> preempt_count: 1, expected: 0
<3> RCU nest depth: 0, expected: 0
<4> 4 locks held by kms_cursor_lega/1505:
<4>  #0: ffffc90003c6f988 (crtc_ww_class_acquire){+.+.}-{0:0}, at: drm_mode_atomic_ioctl+0x13b/0xe90
<4>  #1: ffffc90003c6f9b0 (crtc_ww_class_mutex){+.+.}-{3:3}, at: drm_mode_atomic_ioctl+0x13b/0xe90
<4>  #2: ffff888135b838b8 (&intel_dp->psr.lock){+.+.}-{3:3}, at: intel_psr_lock+0xc5/0xf0 [xe]
<4>  #3: ffff88812607bbc0 (&wl->lock){+.+.}-{2:2}, at: intel_dmc_wl_get+0x3c/0x140 [xe]
<4> CPU: 6 UID: 0 PID: 1505 Comm: kms_cursor_lega Tainted: G     U              6.18.0-rc3-lgci-xe-xe-pw-156729v1+ #1 PREEMPT_{RT,(lazy)}
<4> Tainted: [U]=USER
<4> Hardware name: Intel Corporation Panther Lake Client Platform/PTL-UH LP5 T3 RVP1, BIOS PTLPFWI1.R00.3383.D02.2509240621 09/24/2025
<4> Call Trace:
<4>  <TASK>
<4>  dump_stack_lvl+0xc1/0xf0
<4>  dump_stack+0x10/0x20
<4>  __might_resched+0x174/0x260
<4>  rt_spin_lock+0x63/0x200
<4>  ? intel_dmc_wl_get+0x3c/0x140 [xe]
<4>  intel_dmc_wl_get+0x3c/0x140 [xe]
<4>  intel_set_pipe_src_size+0x89/0xe0 [xe]
<4>  intel_update_crtc+0x3c1/0x950 [xe]
<4>  ? intel_pre_update_crtc+0x258/0x400 [xe]
<4>  skl_commit_modeset_enables+0x217/0x720 [xe]
<4>  intel_atomic_commit_tail+0xd4e/0x1af0 [xe]
<4>  ? lock_release+0xce/0x2a0
<4>  intel_atomic_commit+0x2e5/0x330 [xe]
<4>  ? intel_atomic_commit+0x2e5/0x330 [xe]
<4>  drm_atomic_commit+0xaf/0xf0
<4>  ? __pfx___drm_printfn_info+0x10/0x10
<4>  drm_mode_atomic_ioctl+0xbd5/0xe90
<4>  ? lock_acquire+0xc4/0x2e0
<4>  ? __pfx_drm_mode_atomic_ioctl+0x10/0x10
<4>  drm_ioctl_kernel+0xb6/0x120
<4>  drm_ioctl+0x2d7/0x5a0
<4>  ? __pfx_drm_mode_atomic_ioctl+0x10/0x10
<4>  ? rt_spin_unlock+0xa0/0x140
<4>  ? __pm_runtime_resume+0x53/0x90
<4>  xe_drm_ioctl+0x56/0x90 [xe]
<4>  __x64_sys_ioctl+0xa8/0x110
<4>  ? lock_acquire+0xc4/0x2e0
<4>  x64_sys_call+0x1144/0x26a0
<4>  do_syscall_64+0x93/0xae0
<4>  ? lock_release+0xce/0x2a0
<4>  ? __task_pid_nr_ns+0xd9/0x270
<4>  ? do_syscall_64+0x1b7/0xae0
<4>  ? find_held_lock+0x31/0x90
<4>  ? __task_pid_nr_ns+0xcf/0x270
<4>  ? __lock_acquire+0x43e/0x2860
<4>  ? __task_pid_nr_ns+0xd9/0x270
<4>  ? lock_acquire+0xc4/0x2e0
<4>  ? find_held_lock+0x31/0x90
<4>  ? __task_pid_nr_ns+0xcf/0x270
<4>  ? lock_release+0xce/0x2a0
<4>  ? __task_pid_nr_ns+0xd9/0x270
<4>  ? do_syscall_64+0x1b7/0xae0
<4>  ? do_syscall_64+0x1b7/0xae0
<4>  entry_SYSCALL_64_after_hwframe+0x76/0x7e

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/display/intel_display.c | 36 ++++++++++----------
 drivers/gpu/drm/i915/display/intel_vrr.c     | 16 ++++-----
 2 files changed, 26 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7491e00e38585..d721a72072300 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1583,9 +1583,9 @@ static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
 	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 
-	intel_de_write(display, WM_LINETIME(crtc->pipe),
-		       HSW_LINETIME(crtc_state->linetime) |
-		       HSW_IPS_LINETIME(crtc_state->ips_linetime));
+	intel_de_write_fw(display, WM_LINETIME(crtc->pipe),
+			  HSW_LINETIME(crtc_state->linetime) |
+			  HSW_IPS_LINETIME(crtc_state->ips_linetime));
 }
 
 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
@@ -2582,14 +2582,14 @@ void intel_set_m_n(struct intel_display *display,
 		   i915_reg_t data_m_reg, i915_reg_t data_n_reg,
 		   i915_reg_t link_m_reg, i915_reg_t link_n_reg)
 {
-	intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
-	intel_de_write(display, data_n_reg, m_n->data_n);
-	intel_de_write(display, link_m_reg, m_n->link_m);
+	intel_de_write_fw(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
+	intel_de_write_fw(display, data_n_reg, m_n->data_n);
+	intel_de_write_fw(display, link_m_reg, m_n->link_m);
 	/*
 	 * On BDW+ writing LINK_N arms the double buffered update
 	 * of all the M/N registers, so it must be written last.
 	 */
-	intel_de_write(display, link_n_reg, m_n->link_n);
+	intel_de_write_fw(display, link_n_reg, m_n->link_n);
 }
 
 bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display,
@@ -2776,9 +2776,9 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
 	}
 
 	if (DISPLAY_VER(display) >= 13) {
-		intel_de_write(display,
-			       TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
-			       crtc_state->set_context_latency);
+		intel_de_write_fw(display,
+				  TRANS_SET_CONTEXT_LATENCY(display, cpu_transcoder),
+				  crtc_state->set_context_latency);
 
 		/*
 		 * VBLANK_START not used by hw, just clear it
@@ -2794,9 +2794,9 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
 	 * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP mode.
 	 * But let's write it anyway to keep the state checker happy.
 	 */
-	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
-		       VBLANK_START(crtc_vblank_start - 1) |
-		       VBLANK_END(crtc_vblank_end - 1));
+	intel_de_write_fw(display, TRANS_VBLANK(display, cpu_transcoder),
+			  VBLANK_START(crtc_vblank_start - 1) |
+			  VBLANK_END(crtc_vblank_end - 1));
 	/*
 	 * For platforms that always use VRR Timing Generator, the VTOTAL.Vtotal
 	 * bits are not required. Since the support for these bits is going to
@@ -2810,9 +2810,9 @@ static void intel_set_transcoder_timings_lrr(const struct intel_crtc_state *crtc
 	 * The double buffer latch point for TRANS_VTOTAL
 	 * is the transcoder's undelayed vblank.
 	 */
-	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
-		       VACTIVE(crtc_vdisplay - 1) |
-		       VTOTAL(crtc_vtotal - 1));
+	intel_de_write_fw(display, TRANS_VTOTAL(display, cpu_transcoder),
+			  VACTIVE(crtc_vdisplay - 1) |
+			  VTOTAL(crtc_vtotal - 1));
 
 	intel_vrr_set_fixed_rr_timings(crtc_state);
 	intel_vrr_transcoder_enable(crtc_state);
@@ -2829,8 +2829,8 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
 	/* pipesrc controls the size that is scaled from, which should
 	 * always be the user's requested size.
 	 */
-	intel_de_write(display, PIPESRC(display, pipe),
-		       PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
+	intel_de_write_fw(display, PIPESRC(display, pipe),
+			  PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
 }
 
 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index db74744ddb31a..66e9b18c92d2b 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -317,12 +317,12 @@ void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state)
 	if (!intel_vrr_possible(crtc_state))
 		return;
 
-	intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
-		       intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);
-	intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
-		       intel_vrr_fixed_rr_hw_vmax(crtc_state) - 1);
-	intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
-		       intel_vrr_fixed_rr_hw_flipline(crtc_state) - 1);
+	intel_de_write_fw(display, TRANS_VRR_VMIN(display, cpu_transcoder),
+			  intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);
+	intel_de_write_fw(display, TRANS_VRR_VMAX(display, cpu_transcoder),
+			  intel_vrr_fixed_rr_hw_vmax(crtc_state) - 1);
+	intel_de_write_fw(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
+			  intel_vrr_fixed_rr_hw_flipline(crtc_state) - 1);
 }
 
 static
@@ -876,7 +876,7 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
 	u32 vrr_ctl;
 
-	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN);
+	intel_de_write_fw(display, TRANS_PUSH(display, cpu_transcoder), TRANS_PUSH_EN);
 
 	vrr_ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
 
@@ -888,7 +888,7 @@ static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
 	if (cmrr_enable)
 		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
 
-	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
+	intel_de_write_fw(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
 }
 
 static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
-- 
2.51.0

RE: [i915-rt v5 03/21] drm/i915/display: Use intel_de_write_fw in intel_pipe_fastset

[Shankar, Uma]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Maarten
> Lankhorst
> Sent: Wednesday, January 21, 2026 7:23 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Maarten Lankhorst <dev@lankhorst.se>
> Subject: [i915-rt v5 03/21] drm/i915/display: Use intel_de_write_fw in
> intel_pipe_fastset
> 
> intel_set_pipe_src_size(), hsw_set_linetime_wm(),
> intel_cpu_transcoder_set_m1_n1() and intel_set_transcoder_timings_lrr()
> are called from an atomic context on PREEMPT_RT, and should be using the _fw
> functions.

Change looks good to me but still good to contain it under RT check.
There can be corner cases of cacheline with parallel accesses or any other force wake
dependency. Better to limit this to RT.

I think Ville plans to change uncore to display specific lock so that should be nice.

Regards,
Uma Shankar

> This likely prevents a deadlock on i915.
> 
> Again noticed when trying to disable preemption in vblank evasion:
> <3> BUG: sleeping function called from invalid context at
> kernel/locking/spinlock_rt.c:48 <3> in_atomic(): 1, irqs_disabled(): 0, non_block:
> 0, pid: 1505, name: kms_cursor_lega <3> preempt_count: 1, expected: 0 <3>
> RCU nest depth: 0, expected: 0 <4> 4 locks held by kms_cursor_lega/1505:
> <4>  #0: ffffc90003c6f988 (crtc_ww_class_acquire){+.+.}-{0:0}, at:
> drm_mode_atomic_ioctl+0x13b/0xe90 <4>  #1: ffffc90003c6f9b0
> (crtc_ww_class_mutex){+.+.}-{3:3}, at: drm_mode_atomic_ioctl+0x13b/0xe90 <4>
> #2: ffff888135b838b8 (&intel_dp->psr.lock){+.+.}-{3:3}, at:
> intel_psr_lock+0xc5/0xf0 [xe] <4>  #3: ffff88812607bbc0 (&wl->lock){+.+.}-{2:2},
> at: intel_dmc_wl_get+0x3c/0x140 [xe]
> <4> CPU: 6 UID: 0 PID: 1505 Comm: kms_cursor_lega Tainted: G     U
> 6.18.0-rc3-lgci-xe-xe-pw-156729v1+ #1 PREEMPT_{RT,(lazy)}
> <4> Tainted: [U]=USER
> <4> Hardware name: Intel Corporation Panther Lake Client Platform/PTL-UH LP5
> T3 RVP1, BIOS PTLPFWI1.R00.3383.D02.2509240621 09/24/2025 <4> Call Trace:
> <4>  <TASK>
> <4>  dump_stack_lvl+0xc1/0xf0
> <4>  dump_stack+0x10/0x20
> <4>  __might_resched+0x174/0x260
> <4>  rt_spin_lock+0x63/0x200
> <4>  ? intel_dmc_wl_get+0x3c/0x140 [xe]
> <4>  intel_dmc_wl_get+0x3c/0x140 [xe]
> <4>  intel_set_pipe_src_size+0x89/0xe0 [xe] <4>  intel_update_crtc+0x3c1/0x950
> [xe] <4>  ? intel_pre_update_crtc+0x258/0x400 [xe] <4>
> skl_commit_modeset_enables+0x217/0x720 [xe] <4>
> intel_atomic_commit_tail+0xd4e/0x1af0 [xe] <4>  ? lock_release+0xce/0x2a0 <4>
> intel_atomic_commit+0x2e5/0x330 [xe] <4>  ? intel_atomic_commit+0x2e5/0x330
> [xe] <4>  drm_atomic_commit+0xaf/0xf0 <4>  ?
> __pfx___drm_printfn_info+0x10/0x10
> <4>  drm_mode_atomic_ioctl+0xbd5/0xe90
> <4>  ? lock_acquire+0xc4/0x2e0
> <4>  ? __pfx_drm_mode_atomic_ioctl+0x10/0x10
> <4>  drm_ioctl_kernel+0xb6/0x120
> <4>  drm_ioctl+0x2d7/0x5a0
> <4>  ? __pfx_drm_mode_atomic_ioctl+0x10/0x10
> <4>  ? rt_spin_unlock+0xa0/0x140
> <4>  ? __pm_runtime_resume+0x53/0x90
> <4>  xe_drm_ioctl+0x56/0x90 [xe]
> <4>  __x64_sys_ioctl+0xa8/0x110
> <4>  ? lock_acquire+0xc4/0x2e0
> <4>  x64_sys_call+0x1144/0x26a0
> <4>  do_syscall_64+0x93/0xae0
> <4>  ? lock_release+0xce/0x2a0
> <4>  ? __task_pid_nr_ns+0xd9/0x270
> <4>  ? do_syscall_64+0x1b7/0xae0
> <4>  ? find_held_lock+0x31/0x90
> <4>  ? __task_pid_nr_ns+0xcf/0x270
> <4>  ? __lock_acquire+0x43e/0x2860
> <4>  ? __task_pid_nr_ns+0xd9/0x270
> <4>  ? lock_acquire+0xc4/0x2e0
> <4>  ? find_held_lock+0x31/0x90
> <4>  ? __task_pid_nr_ns+0xcf/0x270
> <4>  ? lock_release+0xce/0x2a0
> <4>  ? __task_pid_nr_ns+0xd9/0x270
> <4>  ? do_syscall_64+0x1b7/0xae0
> <4>  ? do_syscall_64+0x1b7/0xae0
> <4>  entry_SYSCALL_64_after_hwframe+0x76/0x7e
> 
> Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 36 ++++++++++----------
>  drivers/gpu/drm/i915/display/intel_vrr.c     | 16 ++++-----
>  2 files changed, 26 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index 7491e00e38585..d721a72072300 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1583,9 +1583,9 @@ static void hsw_set_linetime_wm(const struct
> intel_crtc_state *crtc_state)
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> 
> -	intel_de_write(display, WM_LINETIME(crtc->pipe),
> -		       HSW_LINETIME(crtc_state->linetime) |
> -		       HSW_IPS_LINETIME(crtc_state->ips_linetime));
> +	intel_de_write_fw(display, WM_LINETIME(crtc->pipe),
> +			  HSW_LINETIME(crtc_state->linetime) |
> +			  HSW_IPS_LINETIME(crtc_state->ips_linetime));
>  }
> 
>  static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
> @@ -2582,14 +2582,14 @@ void intel_set_m_n(struct intel_display *display,
>  		   i915_reg_t data_m_reg, i915_reg_t data_n_reg,
>  		   i915_reg_t link_m_reg, i915_reg_t link_n_reg)  {
> -	intel_de_write(display, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
> -	intel_de_write(display, data_n_reg, m_n->data_n);
> -	intel_de_write(display, link_m_reg, m_n->link_m);
> +	intel_de_write_fw(display, data_m_reg, TU_SIZE(m_n->tu) | m_n-
> >data_m);
> +	intel_de_write_fw(display, data_n_reg, m_n->data_n);
> +	intel_de_write_fw(display, link_m_reg, m_n->link_m);
>  	/*
>  	 * On BDW+ writing LINK_N arms the double buffered update
>  	 * of all the M/N registers, so it must be written last.
>  	 */
> -	intel_de_write(display, link_n_reg, m_n->link_n);
> +	intel_de_write_fw(display, link_n_reg, m_n->link_n);
>  }
> 
>  bool intel_cpu_transcoder_has_m2_n2(struct intel_display *display, @@ -2776,9
> +2776,9 @@ static void intel_set_transcoder_timings_lrr(const struct
> intel_crtc_state *crtc
>  	}
> 
>  	if (DISPLAY_VER(display) >= 13) {
> -		intel_de_write(display,
> -			       TRANS_SET_CONTEXT_LATENCY(display,
> cpu_transcoder),
> -			       crtc_state->set_context_latency);
> +		intel_de_write_fw(display,
> +				  TRANS_SET_CONTEXT_LATENCY(display,
> cpu_transcoder),
> +				  crtc_state->set_context_latency);
> 
>  		/*
>  		 * VBLANK_START not used by hw, just clear it @@ -2794,9
> +2794,9 @@ static void intel_set_transcoder_timings_lrr(const struct
> intel_crtc_state *crtc
>  	 * The hardware actually ignores TRANS_VBLANK.VBLANK_END in DP
> mode.
>  	 * But let's write it anyway to keep the state checker happy.
>  	 */
> -	intel_de_write(display, TRANS_VBLANK(display, cpu_transcoder),
> -		       VBLANK_START(crtc_vblank_start - 1) |
> -		       VBLANK_END(crtc_vblank_end - 1));
> +	intel_de_write_fw(display, TRANS_VBLANK(display, cpu_transcoder),
> +			  VBLANK_START(crtc_vblank_start - 1) |
> +			  VBLANK_END(crtc_vblank_end - 1));
>  	/*
>  	 * For platforms that always use VRR Timing Generator, the
> VTOTAL.Vtotal
>  	 * bits are not required. Since the support for these bits is going to @@ -
> 2810,9 +2810,9 @@ static void intel_set_transcoder_timings_lrr(const struct
> intel_crtc_state *crtc
>  	 * The double buffer latch point for TRANS_VTOTAL
>  	 * is the transcoder's undelayed vblank.
>  	 */
> -	intel_de_write(display, TRANS_VTOTAL(display, cpu_transcoder),
> -		       VACTIVE(crtc_vdisplay - 1) |
> -		       VTOTAL(crtc_vtotal - 1));
> +	intel_de_write_fw(display, TRANS_VTOTAL(display, cpu_transcoder),
> +			  VACTIVE(crtc_vdisplay - 1) |
> +			  VTOTAL(crtc_vtotal - 1));
> 
>  	intel_vrr_set_fixed_rr_timings(crtc_state);
>  	intel_vrr_transcoder_enable(crtc_state);
> @@ -2829,8 +2829,8 @@ static void intel_set_pipe_src_size(const struct
> intel_crtc_state *crtc_state)
>  	/* pipesrc controls the size that is scaled from, which should
>  	 * always be the user's requested size.
>  	 */
> -	intel_de_write(display, PIPESRC(display, pipe),
> -		       PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height -
> 1));
> +	intel_de_write_fw(display, PIPESRC(display, pipe),
> +			  PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height
> - 1));
>  }
> 
>  static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state) diff --
> git a/drivers/gpu/drm/i915/display/intel_vrr.c
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index db74744ddb31a..66e9b18c92d2b 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -317,12 +317,12 @@ void intel_vrr_set_fixed_rr_timings(const struct
> intel_crtc_state *crtc_state)
>  	if (!intel_vrr_possible(crtc_state))
>  		return;
> 
> -	intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder),
> -		       intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);
> -	intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder),
> -		       intel_vrr_fixed_rr_hw_vmax(crtc_state) - 1);
> -	intel_de_write(display, TRANS_VRR_FLIPLINE(display, cpu_transcoder),
> -		       intel_vrr_fixed_rr_hw_flipline(crtc_state) - 1);
> +	intel_de_write_fw(display, TRANS_VRR_VMIN(display, cpu_transcoder),
> +			  intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);
> +	intel_de_write_fw(display, TRANS_VRR_VMAX(display, cpu_transcoder),
> +			  intel_vrr_fixed_rr_hw_vmax(crtc_state) - 1);
> +	intel_de_write_fw(display, TRANS_VRR_FLIPLINE(display,
> cpu_transcoder),
> +			  intel_vrr_fixed_rr_hw_flipline(crtc_state) - 1);
>  }
> 
>  static
> @@ -876,7 +876,7 @@ static void intel_vrr_tg_enable(const struct
> intel_crtc_state *crtc_state,
>  	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
>  	u32 vrr_ctl;
> 
> -	intel_de_write(display, TRANS_PUSH(display, cpu_transcoder),
> TRANS_PUSH_EN);
> +	intel_de_write_fw(display, TRANS_PUSH(display, cpu_transcoder),
> +TRANS_PUSH_EN);
> 
>  	vrr_ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
> 
> @@ -888,7 +888,7 @@ static void intel_vrr_tg_enable(const struct
> intel_crtc_state *crtc_state,
>  	if (cmrr_enable)
>  		vrr_ctl |= VRR_CTL_CMRR_ENABLE;
> 
> -	intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
> vrr_ctl);
> +	intel_de_write_fw(display, TRANS_VRR_CTL(display, cpu_transcoder),
> +vrr_ctl);
>  }
> 
>  static void intel_vrr_tg_disable(const struct intel_crtc_state *old_crtc_state)
> --
> 2.51.0

[i915-rt v5 04/21] drm/i915/display: Make set_pipeconf use the fw variants

[Maarten Lankhorst]

The calls are used inside the critical section when updating
the gamma mode, and thus should use the _fw variants to prevent
locks.

Fixes following splat:
| BUG: sleeping function called from invalid context at kernel/locking/spinlock_rt.c:48
| in_atomic(): 0, irqs_disabled(): 1, non_block: 0, pid: 2115, name: modprobe
| preempt_count: 0, expected: 0
| RCU nest depth: 0, expected: 0
| 4 locks held by modprobe/2115:
|  #0: ffff99b9425161a0 (&dev->mutex){....}-{4:4}, at: __driver_attach+0xaf/0x1c0
|  #1: ffffaa224810f6c0 (crtc_ww_class_acquire){+.+.}-{0:0}, at: intel_initial_commit+0x4c/0x200 [i915]
|  #2: ffffaa224810f6e8 (crtc_ww_class_mutex){+.+.}-{4:4}, at: intel_initial_commit+0x4c/0x200 [i915]
|  #3: ffff99b94a6c9030 (&uncore->lock){+.+.}-{3:3}, at: gen6_write32+0x50/0x290 [i915]
| irq event stamp: 513344
| hardirqs last  enabled at (513343): [<ffffffff8ba8d84c>] _raw_spin_unlock_irqrestore+0x4c/0x60
| hardirqs last disabled at (513344): [<ffffffffc1543646>] intel_pipe_update_start+0x216/0x2c0 [i915]
| softirqs last  enabled at (512766): [<ffffffff8af045cf>] __local_bh_enable_ip+0x10f/0x170
| softirqs last disabled at (512712): [<ffffffffc14dfb6a>] __i915_request_queue+0x3a/0x70 [i915]
| CPU: 3 UID: 0 PID: 2115 Comm: modprobe Tainted: G        W           6.18.0-rc1+ #17 PREEMPT_{RT,(lazy)}
| Tainted: [W]=WARN
| Hardware name: To Be Filled By O.E.M. To Be Filled By O.E.M./Z68 Pro3-M, BIOS P2.30 06/29/2012
| Call Trace:
|  <TASK>
|  dump_stack_lvl+0x68/0x90
|  __might_resched.cold+0xf0/0x12b
|  rt_spin_lock+0x5f/0x200
|  gen6_write32+0x50/0x290 [i915]
|  ilk_set_pipeconf+0x12d/0x230 [i915]
|  ilk_color_commit_arm+0x2d/0x70 [i915]
|  intel_update_crtc+0x15b/0x690 [i915]
|  intel_commit_modeset_enables+0xa6/0xd0 [i915]
|  intel_atomic_commit_tail+0xd55/0x19a0 [i915]
|  intel_atomic_commit+0x25d/0x2a0 [i915]
|  drm_atomic_commit+0xad/0xe0 [drm]
|  intel_initial_commit+0x16c/0x200 [i915]
|  intel_display_driver_probe+0x2e/0x80 [i915]
|  i915_driver_probe+0x791/0xc10 [i915]
|  i915_pci_probe+0xd7/0x190 [i915]

Reported-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d721a72072300..bf37511f9ab21 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -3013,8 +3013,9 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
 
 	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
 
-	intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
-	intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
+	intel_de_write_fw(display, TRANSCONF(display, cpu_transcoder), val);
+	/* posting read */
+	intel_de_read_fw(display, TRANSCONF(display, cpu_transcoder));
 }
 
 static enum intel_output_format
@@ -3209,8 +3210,9 @@ void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
 	val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
 	val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
 
-	intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
-	intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
+	intel_de_write_fw(display, TRANSCONF(display, cpu_transcoder), val);
+	/* posting read */
+	intel_de_read_fw(display, TRANSCONF(display, cpu_transcoder));
 }
 
 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
-- 
2.51.0

RE: [i915-rt v5 04/21] drm/i915/display: Make set_pipeconf use the fw variants

[Shankar, Uma]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Maarten
> Lankhorst
> Sent: Wednesday, January 21, 2026 7:23 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Maarten Lankhorst <dev@lankhorst.se>; Sebastian Andrzej Siewior
> <bigeasy@linutronix.de>
> Subject: [i915-rt v5 04/21] drm/i915/display: Make set_pipeconf use the fw
> variants
> 
> The calls are used inside the critical section when updating the gamma mode, and
> thus should use the _fw variants to prevent locks.

Looks good to me, but limit it to RT.

> Fixes following splat:
> | BUG: sleeping function called from invalid context at
> | kernel/locking/spinlock_rt.c:48
> | in_atomic(): 0, irqs_disabled(): 1, non_block: 0, pid: 2115, name:
> | modprobe
> | preempt_count: 0, expected: 0
> | RCU nest depth: 0, expected: 0
> | 4 locks held by modprobe/2115:
> |  #0: ffff99b9425161a0 (&dev->mutex){....}-{4:4}, at:
> | __driver_attach+0xaf/0x1c0
> |  #1: ffffaa224810f6c0 (crtc_ww_class_acquire){+.+.}-{0:0}, at:
> | intel_initial_commit+0x4c/0x200 [i915]
> |  #2: ffffaa224810f6e8 (crtc_ww_class_mutex){+.+.}-{4:4}, at:
> | intel_initial_commit+0x4c/0x200 [i915]
> |  #3: ffff99b94a6c9030 (&uncore->lock){+.+.}-{3:3}, at:
> | gen6_write32+0x50/0x290 [i915] irq event stamp: 513344 hardirqs last
> | enabled at (513343): [<ffffffff8ba8d84c>]
> | _raw_spin_unlock_irqrestore+0x4c/0x60
> | hardirqs last disabled at (513344): [<ffffffffc1543646>]
> | intel_pipe_update_start+0x216/0x2c0 [i915] softirqs last  enabled at
> | (512766): [<ffffffff8af045cf>] __local_bh_enable_ip+0x10f/0x170 softirqs last
> disabled at (512712): [<ffffffffc14dfb6a>] __i915_request_queue+0x3a/0x70 [i915]
> | CPU: 3 UID: 0 PID: 2115 Comm: modprobe Tainted: G        W           6.18.0-rc1+
> #17 PREEMPT_{RT,(lazy)}
> | Tainted: [W]=WARN
> | Hardware name: To Be Filled By O.E.M. To Be Filled By O.E.M./Z68
> | Pro3-M, BIOS P2.30 06/29/2012 Call Trace:
> |  <TASK>
> |  dump_stack_lvl+0x68/0x90
> |  __might_resched.cold+0xf0/0x12b
> |  rt_spin_lock+0x5f/0x200
> |  gen6_write32+0x50/0x290 [i915]
> |  ilk_set_pipeconf+0x12d/0x230 [i915]
> |  ilk_color_commit_arm+0x2d/0x70 [i915]
> |  intel_update_crtc+0x15b/0x690 [i915]
> |  intel_commit_modeset_enables+0xa6/0xd0 [i915]
> |  intel_atomic_commit_tail+0xd55/0x19a0 [i915]
> |  intel_atomic_commit+0x25d/0x2a0 [i915]
> |  drm_atomic_commit+0xad/0xe0 [drm]
> |  intel_initial_commit+0x16c/0x200 [i915]
> |  intel_display_driver_probe+0x2e/0x80 [i915]
> |  i915_driver_probe+0x791/0xc10 [i915]
> |  i915_pci_probe+0xd7/0x190 [i915]
> 
> Reported-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
> Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index d721a72072300..bf37511f9ab21 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -3013,8 +3013,9 @@ void i9xx_set_pipeconf(const struct intel_crtc_state
> *crtc_state)
> 
>  	val |= TRANSCONF_FRAME_START_DELAY(crtc_state-
> >framestart_delay - 1);
> 
> -	intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
> -	intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
> +	intel_de_write_fw(display, TRANSCONF(display, cpu_transcoder), val);
> +	/* posting read */
> +	intel_de_read_fw(display, TRANSCONF(display, cpu_transcoder));
>  }
> 
>  static enum intel_output_format
> @@ -3209,8 +3210,9 @@ void ilk_set_pipeconf(const struct intel_crtc_state
> *crtc_state)
>  	val |= TRANSCONF_FRAME_START_DELAY(crtc_state-
> >framestart_delay - 1);
>  	val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state-
> >msa_timing_delay);
> 
> -	intel_de_write(display, TRANSCONF(display, cpu_transcoder), val);
> -	intel_de_posting_read(display, TRANSCONF(display, cpu_transcoder));
> +	intel_de_write_fw(display, TRANSCONF(display, cpu_transcoder), val);
> +	/* posting read */
> +	intel_de_read_fw(display, TRANSCONF(display, cpu_transcoder));
>  }
> 
>  static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
> --
> 2.51.0

[i915-rt v5 05/21] drm/i915/display: Move vblank put until after critical section

[Maarten Lankhorst]

drm_crtc_vblank_put may take some locks, this should probably
not be the first thing we do after entering the time sensitive
part.

A better place is after programming is completed. Add a flag
to put the vblank after completion.

In the case of drm_vblank_work_schedule, we may not even need
to disable the vblank interrupt any more if it takes its own
reference.

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cursor.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cursor.c b/drivers/gpu/drm/i915/display/intel_cursor.c
index 2c5d917fbd7e9..3e84a2078a0a7 100644
--- a/drivers/gpu/drm/i915/display/intel_cursor.c
+++ b/drivers/gpu/drm/i915/display/intel_cursor.c
@@ -816,6 +816,7 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 		to_intel_crtc_state(crtc->base.state);
 	struct intel_crtc_state *new_crtc_state;
 	struct intel_vblank_evade_ctx evade;
+	bool has_vblank = false;
 	int ret;
 
 	/*
@@ -913,6 +914,8 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 	intel_psr_lock(crtc_state);
 
 	if (!drm_WARN_ON(display->drm, drm_crtc_vblank_get(&crtc->base))) {
+		has_vblank = true;
+
 		/*
 		 * TODO: maybe check if we're still in PSR
 		 * and skip the vblank evasion entirely?
@@ -922,8 +925,6 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 		local_irq_disable();
 
 		intel_vblank_evade(&evade);
-
-		drm_crtc_vblank_put(&crtc->base);
 	} else {
 		local_irq_disable();
 	}
@@ -939,6 +940,9 @@ intel_legacy_cursor_update(struct drm_plane *_plane,
 
 	intel_psr_unlock(crtc_state);
 
+	if (has_vblank)
+		drm_crtc_vblank_put(&crtc->base);
+
 	if (old_plane_state->ggtt_vma != new_plane_state->ggtt_vma) {
 		drm_vblank_work_init(&old_plane_state->unpin_work, &crtc->base,
 				     intel_cursor_unpin_work);
-- 
2.51.0

[i915-rt v5 06/21] drm/i915/display: Remove locking from intel_vblank_evade critical section

[Maarten Lankhorst]

finish_wait() may take a lock, which means that it can take any amount
of time. On PREEMPT-RT we should not be taking any lock after disabling
preemption, so ensure that the completion is done before disabling
interrupts.

This also has the benefit of making vblank evasion more deterministic,
by performing the final vblank check after all locking is done.

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/display/intel_crtc.c   |  2 +-
 drivers/gpu/drm/i915/display/intel_vblank.c | 30 +++++++++------------
 drivers/gpu/drm/i915/display/intel_vblank.h |  1 +
 3 files changed, 15 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 778ebc5095c38..cb31c9c1c2525 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -684,7 +684,7 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
 	struct intel_crtc_state *new_crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	enum pipe pipe = crtc->pipe;
-	int scanline_end = intel_get_crtc_scanline(crtc);
+	int scanline_end = __intel_get_crtc_scanline(crtc);
 	u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
 	ktime_t end_vbl_time = ktime_get();
 
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index a85796f9d29ba..58c374a7530fe 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -241,7 +241,7 @@ int intel_crtc_scanline_offset(const struct intel_crtc_state *crtc_state)
  * intel_de_read_fw(), only for fast reads of display block, no need for
  * forcewake etc.
  */
-static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
+int __intel_get_crtc_scanline(struct intel_crtc *crtc)
 {
 	struct intel_display *display = to_intel_display(crtc);
 	struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base);
@@ -732,6 +732,16 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state,
 		evade->min -= vblank_delay;
 }
 
+static bool scanline_in_safe_range(struct intel_vblank_evade_ctx *evade, int *scanline, bool unlocked)
+{
+	if (unlocked)
+		*scanline = intel_get_crtc_scanline(evade->crtc);
+	else
+		*scanline = __intel_get_crtc_scanline(evade->crtc);
+
+	return *scanline < evade->min || *scanline > evade->max;
+}
+
 /* must be called with vblank interrupt already enabled! */
 int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
 {
@@ -739,24 +749,12 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
 	struct intel_display *display = to_intel_display(crtc);
 	long timeout = msecs_to_jiffies_timeout(1);
 	wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
-	DEFINE_WAIT(wait);
 	int scanline;
 
 	if (evade->min <= 0 || evade->max <= 0)
 		return 0;
 
-	for (;;) {
-		/*
-		 * prepare_to_wait() has a memory barrier, which guarantees
-		 * other CPUs can see the task state update by the time we
-		 * read the scanline.
-		 */
-		prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
-
-		scanline = intel_get_crtc_scanline(crtc);
-		if (scanline < evade->min || scanline > evade->max)
-			break;
-
+	while (!scanline_in_safe_range(evade, &scanline, false)) {
 		if (!timeout) {
 			drm_dbg_kms(display->drm,
 				    "Potential atomic update failure on pipe %c\n",
@@ -766,13 +764,11 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
 
 		local_irq_enable();
 
-		timeout = schedule_timeout(timeout);
+		timeout = wait_event_timeout(*wq, scanline_in_safe_range(evade, &scanline, true), timeout);
 
 		local_irq_disable();
 	}
 
-	finish_wait(wq, &wait);
-
 	/*
 	 * On VLV/CHV DSI the scanline counter would appear to
 	 * increment approx. 1/3 of a scanline before start of vblank.
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h b/drivers/gpu/drm/i915/display/intel_vblank.h
index 98d04cacd65f8..aa1974400e9fc 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.h
+++ b/drivers/gpu/drm/i915/display/intel_vblank.h
@@ -38,6 +38,7 @@ u32 g4x_get_vblank_counter(struct drm_crtc *crtc);
 bool intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
 				     ktime_t *vblank_time, bool in_vblank_irq);
 int intel_get_crtc_scanline(struct intel_crtc *crtc);
+int __intel_get_crtc_scanline(struct intel_crtc *crtc);
 void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc);
 void intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc);
 void intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
-- 
2.51.0

RE: [i915-rt v5 06/21] drm/i915/display: Remove locking from intel_vblank_evade critical section

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Maarten
> Lankhorst
> Sent: Wednesday, January 21, 2026 7:23 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Maarten Lankhorst <dev@lankhorst.se>
> Subject: [i915-rt v5 06/21] drm/i915/display: Remove locking from
> intel_vblank_evade critical section
> 
> finish_wait() may take a lock, which means that it can take any amount of time.
> On PREEMPT-RT we should not be taking any lock after disabling preemption, so
> ensure that the completion is done before disabling interrupts.
> 
> This also has the benefit of making vblank evasion more deterministic, by
> performing the final vblank check after all locking is done.
> 
> Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
> ---
>  drivers/gpu/drm/i915/display/intel_crtc.c   |  2 +-
>  drivers/gpu/drm/i915/display/intel_vblank.c | 30 +++++++++------------
> drivers/gpu/drm/i915/display/intel_vblank.h |  1 +
>  3 files changed, 15 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 778ebc5095c38..cb31c9c1c2525 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -684,7 +684,7 @@ void intel_pipe_update_end(struct intel_atomic_state
> *state,
>  	struct intel_crtc_state *new_crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	enum pipe pipe = crtc->pipe;
> -	int scanline_end = intel_get_crtc_scanline(crtc);
> +	int scanline_end = __intel_get_crtc_scanline(crtc);
>  	u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
>  	ktime_t end_vbl_time = ktime_get();
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c
> b/drivers/gpu/drm/i915/display/intel_vblank.c
> index a85796f9d29ba..58c374a7530fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -241,7 +241,7 @@ int intel_crtc_scanline_offset(const struct intel_crtc_state
> *crtc_state)
>   * intel_de_read_fw(), only for fast reads of display block, no need for
>   * forcewake etc.
>   */
> -static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
> +int __intel_get_crtc_scanline(struct intel_crtc *crtc)
>  {
>  	struct intel_display *display = to_intel_display(crtc);
>  	struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(&crtc->base);
> @@ -732,6 +732,16 @@ void intel_vblank_evade_init(const struct
> intel_crtc_state *old_crtc_state,
>  		evade->min -= vblank_delay;
>  }
> 
> +static bool scanline_in_safe_range(struct intel_vblank_evade_ctx
> +*evade, int *scanline, bool unlocked) {
> +	if (unlocked)
> +		*scanline = intel_get_crtc_scanline(evade->crtc);
> +	else
> +		*scanline = __intel_get_crtc_scanline(evade->crtc);
> +
> +	return *scanline < evade->min || *scanline > evade->max; }
> +
>  /* must be called with vblank interrupt already enabled! */  int
> intel_vblank_evade(struct intel_vblank_evade_ctx *evade)  { @@ -739,24 +749,12
> @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
>  	struct intel_display *display = to_intel_display(crtc);
>  	long timeout = msecs_to_jiffies_timeout(1);
>  	wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
> -	DEFINE_WAIT(wait);
>  	int scanline;
> 
>  	if (evade->min <= 0 || evade->max <= 0)
>  		return 0;
> 
> -	for (;;) {
> -		/*
> -		 * prepare_to_wait() has a memory barrier, which guarantees
> -		 * other CPUs can see the task state update by the time we
> -		 * read the scanline.
> -		 */
> -		prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
> -
> -		scanline = intel_get_crtc_scanline(crtc);
> -		if (scanline < evade->min || scanline > evade->max)
> -			break;
> -
> +	while (!scanline_in_safe_range(evade, &scanline, false)) {
>  		if (!timeout) {
>  			drm_dbg_kms(display->drm,
>  				    "Potential atomic update failure on pipe %c\n",
> @@ -766,13 +764,11 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx
> *evade)
> 
>  		local_irq_enable();
> 
> -		timeout = schedule_timeout(timeout);
> +		timeout = wait_event_timeout(*wq, scanline_in_safe_range(evade,
> +&scanline, true), timeout);
> 
>  		local_irq_disable();
>  	}
> 
> -	finish_wait(wq, &wait);

Changes look good to me, but I would still suggest to have a RT variant for evade handling.
Once we resolve all corner cases, the relevant pieces of code can be made generic to apply for both.

Regards,
Uma Shankar

> -
>  	/*
>  	 * On VLV/CHV DSI the scanline counter would appear to
>  	 * increment approx. 1/3 of a scanline before start of vblank.
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.h
> b/drivers/gpu/drm/i915/display/intel_vblank.h
> index 98d04cacd65f8..aa1974400e9fc 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.h
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.h
> @@ -38,6 +38,7 @@ u32 g4x_get_vblank_counter(struct drm_crtc *crtc);  bool
> intel_crtc_get_vblank_timestamp(struct drm_crtc *crtc, int *max_error,
>  				     ktime_t *vblank_time, bool in_vblank_irq);  int
> intel_get_crtc_scanline(struct intel_crtc *crtc);
> +int __intel_get_crtc_scanline(struct intel_crtc *crtc);
>  void intel_wait_for_pipe_scanline_stopped(struct intel_crtc *crtc);  void
> intel_wait_for_pipe_scanline_moving(struct intel_crtc *crtc);  void
> intel_crtc_update_active_timings(const struct intel_crtc_state *crtc_state,
> --
> 2.51.0

[i915-rt v5 07/21] drm/i915/display: Handle vlv dsi workaround in scanline_in_safe_range too

[Maarten Lankhorst]

Now that we have a macro, might as well handle the VLV dsi workaround
too.

This makes the vblank evasion code slightly more deterministic, by not
looping with interrupts disabled.

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/display/intel_vblank.c | 36 ++++++++++-----------
 1 file changed, 18 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 58c374a7530fe..6bc784563a7c1 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -739,6 +739,24 @@ static bool scanline_in_safe_range(struct intel_vblank_evade_ctx *evade, int *sc
 	else
 		*scanline = __intel_get_crtc_scanline(evade->crtc);
 
+	/*
+	 * On VLV/CHV DSI the scanline counter would appear to
+	 * increment approx. 1/3 of a scanline before start of vblank.
+	 * The registers still get latched at start of vblank however.
+	 * This means we must not write any registers on the first
+	 * line of vblank (since not the whole line is actually in
+	 * vblank). And unfortunately we can't use the interrupt to
+	 * wait here since it will fire too soon. We could use the
+	 * frame start interrupt instead since it will fire after the
+	 * critical scanline, but that would require more changes
+	 * in the interrupt code. So for now we'll just do the nasty
+	 * thing and poll for the bad scanline to pass us by.
+	 *
+	 * FIXME figure out if BXT+ DSI suffers from this as well
+	 */
+	if (evade->need_vlv_dsi_wa && *scanline == evade->vblank_start)
+		return false;
+
 	return *scanline < evade->min || *scanline > evade->max;
 }
 
@@ -769,24 +787,6 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx *evade)
 		local_irq_disable();
 	}
 
-	/*
-	 * On VLV/CHV DSI the scanline counter would appear to
-	 * increment approx. 1/3 of a scanline before start of vblank.
-	 * The registers still get latched at start of vblank however.
-	 * This means we must not write any registers on the first
-	 * line of vblank (since not the whole line is actually in
-	 * vblank). And unfortunately we can't use the interrupt to
-	 * wait here since it will fire too soon. We could use the
-	 * frame start interrupt instead since it will fire after the
-	 * critical scanline, but that would require more changes
-	 * in the interrupt code. So for now we'll just do the nasty
-	 * thing and poll for the bad scanline to pass us by.
-	 *
-	 * FIXME figure out if BXT+ DSI suffers from this as well
-	 */
-	while (evade->need_vlv_dsi_wa && scanline == evade->vblank_start)
-		scanline = intel_get_crtc_scanline(crtc);
-
 	return scanline;
 }
 
-- 
2.51.0

RE: [i915-rt v5 07/21] drm/i915/display: Handle vlv dsi workaround in scanline_in_safe_range too

[Shankar, Uma]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Maarten
> Lankhorst
> Sent: Wednesday, January 21, 2026 7:23 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Maarten Lankhorst <dev@lankhorst.se>
> Subject: [i915-rt v5 07/21] drm/i915/display: Handle vlv dsi workaround in
> scanline_in_safe_range too
> 
> Now that we have a macro, might as well handle the VLV dsi workaround too.
> 
> This makes the vblank evasion code slightly more deterministic, by not looping
> with interrupts disabled.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
> ---
>  drivers/gpu/drm/i915/display/intel_vblank.c | 36 ++++++++++-----------
>  1 file changed, 18 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c
> b/drivers/gpu/drm/i915/display/intel_vblank.c
> index 58c374a7530fe..6bc784563a7c1 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -739,6 +739,24 @@ static bool scanline_in_safe_range(struct
> intel_vblank_evade_ctx *evade, int *sc
>  	else
>  		*scanline = __intel_get_crtc_scanline(evade->crtc);
> 
> +	/*
> +	 * On VLV/CHV DSI the scanline counter would appear to
> +	 * increment approx. 1/3 of a scanline before start of vblank.
> +	 * The registers still get latched at start of vblank however.
> +	 * This means we must not write any registers on the first
> +	 * line of vblank (since not the whole line is actually in
> +	 * vblank). And unfortunately we can't use the interrupt to
> +	 * wait here since it will fire too soon. We could use the
> +	 * frame start interrupt instead since it will fire after the
> +	 * critical scanline, but that would require more changes
> +	 * in the interrupt code. So for now we'll just do the nasty
> +	 * thing and poll for the bad scanline to pass us by.
> +	 *
> +	 * FIXME figure out if BXT+ DSI suffers from this as well
> +	 */
> +	if (evade->need_vlv_dsi_wa && *scanline == evade->vblank_start)
> +		return false;
> +
>  	return *scanline < evade->min || *scanline > evade->max;  }
> 
> @@ -769,24 +787,6 @@ int intel_vblank_evade(struct intel_vblank_evade_ctx
> *evade)
>  		local_irq_disable();
>  	}
> 
> -	/*
> -	 * On VLV/CHV DSI the scanline counter would appear to
> -	 * increment approx. 1/3 of a scanline before start of vblank.
> -	 * The registers still get latched at start of vblank however.
> -	 * This means we must not write any registers on the first
> -	 * line of vblank (since not the whole line is actually in
> -	 * vblank). And unfortunately we can't use the interrupt to
> -	 * wait here since it will fire too soon. We could use the
> -	 * frame start interrupt instead since it will fire after the
> -	 * critical scanline, but that would require more changes
> -	 * in the interrupt code. So for now we'll just do the nasty
> -	 * thing and poll for the bad scanline to pass us by.
> -	 *
> -	 * FIXME figure out if BXT+ DSI suffers from this as well
> -	 */
> -	while (evade->need_vlv_dsi_wa && scanline == evade->vblank_start)
> -		scanline = intel_get_crtc_scanline(crtc);
> -
>  	return scanline;
>  }
> 
> --
> 2.51.0

[i915-rt v5 08/21] drm/i915/display: Make icl_dsi_frame_update use _fw too

[Maarten Lankhorst]

Don't use the dmc lock inside the vblank critical section,
not even as last call.

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index c8e0333706c1e..1df2f347a13be 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -243,8 +243,8 @@ void icl_dsi_frame_update(struct intel_crtc_state *crtc_state)
 	else
 		return;
 
-	intel_de_rmw(display, DSI_CMD_FRMCTL(port), 0,
-		     DSI_FRAME_UPDATE_REQUEST);
+	intel_de_rmw_fw(display, DSI_CMD_FRMCTL(port), 0,
+			DSI_FRAME_UPDATE_REQUEST);
 }
 
 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
-- 
2.51.0

RE: [i915-rt v5 08/21] drm/i915/display: Make icl_dsi_frame_update use _fw too

[Shankar, Uma]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Maarten
> Lankhorst
> Sent: Wednesday, January 21, 2026 7:23 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Maarten Lankhorst <dev@lankhorst.se>
> Subject: [i915-rt v5 08/21] drm/i915/display: Make icl_dsi_frame_update use _fw
> too
> 
> Don't use the dmc lock inside the vblank critical section, not even as last call.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index c8e0333706c1e..1df2f347a13be 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -243,8 +243,8 @@ void icl_dsi_frame_update(struct intel_crtc_state
> *crtc_state)
>  	else
>  		return;
> 
> -	intel_de_rmw(display, DSI_CMD_FRMCTL(port), 0,
> -		     DSI_FRAME_UPDATE_REQUEST);
> +	intel_de_rmw_fw(display, DSI_CMD_FRMCTL(port), 0,
> +			DSI_FRAME_UPDATE_REQUEST);
>  }
> 
>  static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
> --
> 2.51.0

[i915-rt v5 09/21] drm/i915/display: Enable interrupts earlier on PREEMPT_RT

[Maarten Lankhorst]

The last part of the vblank evasion is about updating bookkeeping,
not programming hardware registers.

The interrupts cannot stay disabled here on PREEMPT_RT since the
spinlocks get converted to mutexes.

There's still a small race in VRR that needs to be addressed, and
in the other worst case there is a delay of a vblank completion if
the vblank is fired and we schedule on the next vblank, this needs
to be addressed separately.

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/display/intel_crtc.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index cb31c9c1c2525..84ab737c50918 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -703,6 +703,14 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
 	    intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
 		icl_dsi_frame_update(new_crtc_state);
 
+#if IS_ENABLED(CONFIG_PREEMPT_RT)
+	/*
+	 * Timing sensitive register writing completed, non-deterministic
+	 * locking from here on out.
+	 */
+	local_irq_enable();
+#endif
+
 	/* We're still in the vblank-evade critical section, this can't race.
 	 * Would be slightly nice to just grab the vblank count and arm the
 	 * event outside of the critical section - the spinlock might spin for a
@@ -750,7 +758,9 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
 	if (!state->base.legacy_cursor_update)
 		intel_vrr_send_push(NULL, new_crtc_state);
 
+#if !IS_ENABLED(CONFIG_PREEMPT_RT)
 	local_irq_enable();
+#endif
 
 	if (intel_parent_vgpu_active(display))
 		goto out;
-- 
2.51.0

RE: [i915-rt v5 09/21] drm/i915/display: Enable interrupts earlier on PREEMPT_RT

[Shankar, Uma]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Maarten
> Lankhorst
> Sent: Wednesday, January 21, 2026 7:23 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Maarten Lankhorst <dev@lankhorst.se>
> Subject: [i915-rt v5 09/21] drm/i915/display: Enable interrupts earlier on
> PREEMPT_RT
> 
> The last part of the vblank evasion is about updating bookkeeping, not
> programming hardware registers.
> 
> The interrupts cannot stay disabled here on PREEMPT_RT since the spinlocks get
> converted to mutexes.
> 
> There's still a small race in VRR that needs to be addressed, and in the other
> worst case there is a delay of a vblank completion if the vblank is fired and we
> schedule on the next vblank, this needs to be addressed separately.
> 
> Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
> ---
>  drivers/gpu/drm/i915/display/intel_crtc.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c
> b/drivers/gpu/drm/i915/display/intel_crtc.c
> index cb31c9c1c2525..84ab737c50918 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -703,6 +703,14 @@ void intel_pipe_update_end(struct intel_atomic_state
> *state,
>  	    intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
>  		icl_dsi_frame_update(new_crtc_state);
> 
> +#if IS_ENABLED(CONFIG_PREEMPT_RT)
> +	/*
> +	 * Timing sensitive register writing completed, non-deterministic
> +	 * locking from here on out.
> +	 */
> +	local_irq_enable();
> +#endif
> +
>  	/* We're still in the vblank-evade critical section, this can't race.
>  	 * Would be slightly nice to just grab the vblank count and arm the
>  	 * event outside of the critical section - the spinlock might spin for a @@ -
> 750,7 +758,9 @@ void intel_pipe_update_end(struct intel_atomic_state *state,
>  	if (!state->base.legacy_cursor_update)
>  		intel_vrr_send_push(NULL, new_crtc_state);

Yeah, we need to check for the VRR case as this will not work out for VRR.
For other non VRR case as well, potential of missed frame is there, but we can check on
CI with some stress test as to how much it impacts practically. Maybe limit to
Non VRR in first phase and then plan for VRR enabling on RT as separate change.

Regards,
Uma Shankar

> +#if !IS_ENABLED(CONFIG_PREEMPT_RT)
>  	local_irq_enable();
> +#endif
> 
>  	if (intel_parent_vgpu_active(display))
>  		goto out;
> --
> 2.51.0

[i915-rt v5 10/21] drm/i915: Use preempt_disable/enable_rt() where recommended

[Maarten Lankhorst]

From: Mike Galbraith <umgwanakikbuti@gmail.com>

Mario Kleiner suggest in commit
  ad3543ede630f ("drm/intel: Push get_scanout_position() timestamping into kms driver.")

a spots where preemption should be disabled on PREEMPT_RT. The
difference is that on PREEMPT_RT the intel_uncore::lock disables neither
preemption nor interrupts and so region remains preemptible.

The area covers only register reads and writes. The part that worries me
is:
- __intel_get_crtc_scanline() the worst case is 100us if no match is
  found.

- intel_crtc_scanlines_since_frame_timestamp() not sure how long this
  may take in the worst case.

It was in the RT queue for a while and nobody complained.
Disable preemption on PREEPMPT_RT during timestamping.

[bigeasy: patch description.]

Cc: Mario Kleiner <mario.kleiner.de@gmail.com>
Signed-off-by: Mike Galbraith <umgwanakikbuti@gmail.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/display/intel_vblank.c | 43 ++++++++++++++++-----
 1 file changed, 33 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index 6bc784563a7c1..e204c260b9aef 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -316,6 +316,20 @@ static void intel_vblank_section_exit(struct intel_display *display)
 	struct intel_uncore *uncore = to_intel_uncore(display->drm);
 	spin_unlock(&uncore->lock);
 }
+
+static void intel_vblank_section_enter_irqf(struct intel_display *display, unsigned long *flags)
+	__acquires(i915->uncore.lock)
+{
+	struct intel_uncore *uncore = to_intel_uncore(display->drm);
+	spin_lock_irqsave(&uncore->lock, *flags);
+}
+
+static void intel_vblank_section_exit_irqf(struct intel_display *display, unsigned long flags)
+	__releases(i915->uncore.lock)
+{
+	struct intel_uncore *uncore = to_intel_uncore(display->drm);
+	spin_unlock_irqrestore(&uncore->lock, flags);
+}
 #else
 static void intel_vblank_section_enter(struct intel_display *display)
 {
@@ -324,6 +338,17 @@ static void intel_vblank_section_enter(struct intel_display *display)
 static void intel_vblank_section_exit(struct intel_display *display)
 {
 }
+
+static void intel_vblank_section_enter_irqf(struct intel_display *display, unsigned long *flags)
+{
+	*flags = 0;
+}
+
+static void intel_vblank_section_exit_irqf(struct intel_display *display, unsigned long flags)
+{
+	if (flags)
+		return;
+}
 #endif
 
 static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
@@ -360,10 +385,10 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
 	 * timing critical raw register reads, potentially with
 	 * preemption disabled, so the following code must not block.
 	 */
-	local_irq_save(irqflags);
-	intel_vblank_section_enter(display);
+	intel_vblank_section_enter_irqf(display, &irqflags);
 
-	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
+	if (IS_ENABLED(CONFIG_PREEMPT_RT))
+		preempt_disable();
 
 	/* Get optional system timestamp before query. */
 	if (stime)
@@ -427,10 +452,10 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
 	if (etime)
 		*etime = ktime_get();
 
-	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
+	if (IS_ENABLED(CONFIG_PREEMPT_RT))
+		preempt_enable();
 
-	intel_vblank_section_exit(display);
-	local_irq_restore(irqflags);
+	intel_vblank_section_exit_irqf(display, irqflags);
 
 	/*
 	 * While in vblank, position will be negative
@@ -468,13 +493,11 @@ int intel_get_crtc_scanline(struct intel_crtc *crtc)
 	unsigned long irqflags;
 	int position;
 
-	local_irq_save(irqflags);
-	intel_vblank_section_enter(display);
+	intel_vblank_section_enter_irqf(display, &irqflags);
 
 	position = __intel_get_crtc_scanline(crtc);
 
-	intel_vblank_section_exit(display);
-	local_irq_restore(irqflags);
+	intel_vblank_section_exit_irqf(display, irqflags);
 
 	return position;
 }
-- 
2.51.0

RE: [i915-rt v5 10/21] drm/i915: Use preempt_disable/enable_rt() where recommended

[Shankar, Uma]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Maarten
> Lankhorst
> Sent: Wednesday, January 21, 2026 7:23 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Mike Galbraith <umgwanakikbuti@gmail.com>; Mario Kleiner
> <mario.kleiner.de@gmail.com>; Thomas Gleixner <tglx@linutronix.de>; Sebastian
> Andrzej Siewior <bigeasy@linutronix.de>; Maarten Lankhorst
> <dev@lankhorst.se>
> Subject: [i915-rt v5 10/21] drm/i915: Use preempt_disable/enable_rt() where
> recommended
> 
> From: Mike Galbraith <umgwanakikbuti@gmail.com>
> 
> Mario Kleiner suggest in commit
>   ad3543ede630f ("drm/intel: Push get_scanout_position() timestamping into kms
> driver.")
> 
> a spots where preemption should be disabled on PREEMPT_RT. The difference is
> that on PREEMPT_RT the intel_uncore::lock disables neither preemption nor
> interrupts and so region remains preemptible.
> 
> The area covers only register reads and writes. The part that worries me
> is:
> - __intel_get_crtc_scanline() the worst case is 100us if no match is
>   found.
> 
> - intel_crtc_scanlines_since_frame_timestamp() not sure how long this
>   may take in the worst case.
> 
> It was in the RT queue for a while and nobody complained.
> Disable preemption on PREEPMPT_RT during timestamping.

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> [bigeasy: patch description.]
> 
> Cc: Mario Kleiner <mario.kleiner.de@gmail.com>
> Signed-off-by: Mike Galbraith <umgwanakikbuti@gmail.com>
> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
> Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
> ---
>  drivers/gpu/drm/i915/display/intel_vblank.c | 43 ++++++++++++++++-----
>  1 file changed, 33 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c
> b/drivers/gpu/drm/i915/display/intel_vblank.c
> index 6bc784563a7c1..e204c260b9aef 100644
> --- a/drivers/gpu/drm/i915/display/intel_vblank.c
> +++ b/drivers/gpu/drm/i915/display/intel_vblank.c
> @@ -316,6 +316,20 @@ static void intel_vblank_section_exit(struct intel_display
> *display)
>  	struct intel_uncore *uncore = to_intel_uncore(display->drm);
>  	spin_unlock(&uncore->lock);
>  }
> +
> +static void intel_vblank_section_enter_irqf(struct intel_display *display, unsigned
> long *flags)
> +	__acquires(i915->uncore.lock)
> +{
> +	struct intel_uncore *uncore = to_intel_uncore(display->drm);
> +	spin_lock_irqsave(&uncore->lock, *flags); }
> +
> +static void intel_vblank_section_exit_irqf(struct intel_display *display, unsigned
> long flags)
> +	__releases(i915->uncore.lock)
> +{
> +	struct intel_uncore *uncore = to_intel_uncore(display->drm);
> +	spin_unlock_irqrestore(&uncore->lock, flags); }
>  #else
>  static void intel_vblank_section_enter(struct intel_display *display)  { @@ -324,6
> +338,17 @@ static void intel_vblank_section_enter(struct intel_display *display)
> static void intel_vblank_section_exit(struct intel_display *display)  {  }
> +
> +static void intel_vblank_section_enter_irqf(struct intel_display
> +*display, unsigned long *flags) {
> +	*flags = 0;
> +}
> +
> +static void intel_vblank_section_exit_irqf(struct intel_display
> +*display, unsigned long flags) {
> +	if (flags)
> +		return;
> +}
>  #endif
> 
>  static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc, @@ -360,10
> +385,10 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc *_crtc,
>  	 * timing critical raw register reads, potentially with
>  	 * preemption disabled, so the following code must not block.
>  	 */
> -	local_irq_save(irqflags);
> -	intel_vblank_section_enter(display);
> +	intel_vblank_section_enter_irqf(display, &irqflags);
> 
> -	/* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
> +	if (IS_ENABLED(CONFIG_PREEMPT_RT))
> +		preempt_disable();
> 
>  	/* Get optional system timestamp before query. */
>  	if (stime)
> @@ -427,10 +452,10 @@ static bool i915_get_crtc_scanoutpos(struct drm_crtc
> *_crtc,
>  	if (etime)
>  		*etime = ktime_get();
> 
> -	/* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
> +	if (IS_ENABLED(CONFIG_PREEMPT_RT))
> +		preempt_enable();
> 
> -	intel_vblank_section_exit(display);
> -	local_irq_restore(irqflags);
> +	intel_vblank_section_exit_irqf(display, irqflags);
> 
>  	/*
>  	 * While in vblank, position will be negative @@ -468,13 +493,11 @@ int
> intel_get_crtc_scanline(struct intel_crtc *crtc)
>  	unsigned long irqflags;
>  	int position;
> 
> -	local_irq_save(irqflags);
> -	intel_vblank_section_enter(display);
> +	intel_vblank_section_enter_irqf(display, &irqflags);
> 
>  	position = __intel_get_crtc_scanline(crtc);
> 
> -	intel_vblank_section_exit(display);
> -	local_irq_restore(irqflags);
> +	intel_vblank_section_exit_irqf(display, irqflags);
> 
>  	return position;
>  }
> --
> 2.51.0

[i915-rt v5 11/21] drm/i915/display: Use intel_de_read/write_fw in colorops

[Maarten Lankhorst]

Using the _fw variants fixes a module load error on PTL:

<4> [363.690050] Call Trace:
<4> [363.690052]  <TASK>
<4> [363.690055]  dump_stack_lvl+0x91/0xf0
<4> [363.690067]  dump_stack+0x10/0x20
<4> [363.690074]  __might_resched+0x174/0x260
<4> [363.690087]  rt_spin_lock+0x63/0x200
<4> [363.690092]  ? intel_dmc_wl_get+0x3c/0x140 [xe]
<4> [363.690470]  ? __lock_acquire+0x1195/0x2860
<4> [363.690487]  intel_dmc_wl_get+0x3c/0x140 [xe]
<4> [363.690842]  intel_color_plane_commit_arm+0xbc/0x140 [xe]
<4> [363.691246]  icl_plane_update_arm+0x23f/0x280 [xe]
<4> [363.691605]  intel_plane_update_arm+0x74/0x170 [xe]
<4> [363.691970]  intel_crtc_planes_update_arm+0x3cb/0x4c0 [xe]
<4> [363.692338]  intel_update_crtc+0x1c3/0x840 [xe]
<4> [363.692742]  ? intel_pre_update_crtc+0x2ce/0x470 [xe]
<4> [363.693125]  ? intel_enable_crtc+0x123/0x150 [xe]
<4> [363.693508]  skl_commit_modeset_enables+0x4c4/0x720 [xe]
<4> [363.693888]  intel_atomic_commit_tail+0xd9d/0x1b30 [xe]
<4> [363.694274]  intel_atomic_commit+0x2e8/0x330 [xe]
<4> [363.694621]  ? intel_atomic_commit+0x2e8/0x330 [xe]
<4> [363.694956]  drm_atomic_commit+0xaf/0xf0
<4> [363.694962]  ? __pfx___drm_printfn_info+0x10/0x10
<4> [363.694978]  drm_client_modeset_commit_atomic+0x25c/0x2b0
<4> [363.695018]  drm_client_modeset_commit_locked+0x63/0x1b0
<4> [363.695029]  drm_client_modeset_commit+0x26/0x50
<4> [363.695035]  __drm_fb_helper_restore_fbdev_mode_unlocked+0xdc/0x110
<4> [363.695045]  drm_fb_helper_set_par+0x2f/0x50
<4> [363.695052]  intel_fbdev_set_par+0x39/0x90 [xe]
<4> [363.695365]  fbcon_init+0x283/0x680
<4> [363.695382]  visual_init+0xf2/0x190
<4> [363.695396]  do_bind_con_driver.isra.0+0x1f1/0x4c0
<4> [363.695416]  do_take_over_console+0x181/0x220
<4> [363.695422]  ? vprintk_default+0x1d/0x30
<4> [363.695436]  do_fbcon_takeover+0x85/0x160
<4> [363.695447]  do_fb_registered+0x24c/0x2b0
<4> [363.695460]  fbcon_fb_registered+0x3a/0x90
<4> [363.695469]  do_register_framebuffer+0x216/0x320
<4> [363.695488]  register_framebuffer+0x23/0x50
<4> [363.695494]  __drm_fb_helper_initial_config_and_unlock+0x3ea/0x670
<4> [363.695502]  ? trace_hardirqs_on+0x1e/0xd0
<4> [363.695526]  drm_fb_helper_initial_config+0x3f/0x50
<4> [363.695534]  drm_fbdev_client_hotplug+0x80/0xd0
<4> [363.695543]  drm_client_register+0x8a/0xe0
<4> [363.695556]  drm_fbdev_client_setup+0x127/0x1f0
<4> [363.695563]  drm_client_setup+0xa7/0xe0
<4> [363.695569]  drm_client_setup_with_color_mode+0x24/0x40
<4> [363.695575]  intel_fbdev_setup+0x1c6/0x510 [xe]
<4> [363.695857]  intel_display_driver_register+0xb5/0x100 [xe]
<4> [363.696188]  ? __pfx___drm_printfn_dbg+0x10/0x10
<4> [363.696194]  ? intel_display_driver_register+0x2e/0x100 [xe]
<4> [363.696515]  xe_display_register+0x29/0x40 [xe]
<4> [363.696858]  xe_device_probe+0x51a/0x9e0 [xe]
<4> [363.697102]  ? __drmm_add_action+0x98/0x110
<4> [363.697108]  ? __pfx___drmm_mutex_release+0x10/0x10
<4> [363.697116]  ? __drmm_add_action_or_reset+0x1e/0x50
<4> [363.697130]  xe_pci_probe+0x396/0x620 [xe]
<4> [363.697423]  local_pci_probe+0x47/0xb0
<4> [363.697431]  pci_device_probe+0xf3/0x260
<4> [363.697444]  really_probe+0xf1/0x3c0
<4> [363.697451]  __driver_probe_device+0x8c/0x180
<4> [363.697458]  driver_probe_device+0x24/0xd0
<4> [363.697464]  __driver_attach+0x10f/0x220
<4> [363.697468]  ? __pfx___driver_attach+0x10/0x10
<4> [363.697472]  bus_for_each_dev+0x7f/0xe0
<4> [363.697484]  driver_attach+0x1e/0x30
<4> [363.697487]  bus_add_driver+0x154/0x290
<4> [363.697498]  driver_register+0x5e/0x130
<4> [363.697504]  __pci_register_driver+0x84/0xa0
<4> [363.697509]  xe_register_pci_driver+0x23/0x30 [xe]
<4> [363.697762]  xe_init+0x2c/0x110 [xe]
<4> [363.698007]  ? __pfx_xe_init+0x10/0x10 [xe]
<4> [363.698239]  do_one_initcall+0x60/0x3f0
<4> [363.698250]  ? __kmalloc_cache_noprof+0x470/0x690
<4> [363.698267]  do_init_module+0x97/0x2b0
<4> [363.698275]  load_module+0x2d08/0x2e30
<4> [363.698280]  ? __kernel_read+0x164/0x310
<4> [363.698312]  ? kernel_read_file+0x2ca/0x340
<4> [363.698328]  init_module_from_file+0x96/0xe0
<4> [363.698330]  ? init_module_from_file+0x96/0xe0
<4> [363.698357]  idempotent_init_module+0x11d/0x340
<4> [363.698384]  __x64_sys_finit_module+0x73/0xe0
<4> [363.698393]  x64_sys_call+0x1e3d/0x26a0
<4> [363.698399]  do_syscall_64+0x93/0xab0
<4> [363.698413]  ? ext4_llseek+0xc3/0x130
<4> [363.698425]  ? ksys_lseek+0x55/0xd0
<4> [363.698438]  ? do_syscall_64+0x1b7/0xab0
<4> [363.698444]  ? switch_fpu_return+0xea/0x150
<4> [363.698454]  ? do_syscall_64+0x1b7/0xab0
<4> [363.698465]  ? kernfs_fop_read_iter+0x197/0x210
<4> [363.698470]  ? rw_verify_area+0x16f/0x200
<4> [363.698482]  ? vfs_read+0x22a/0x360
<4> [363.698498]  ? do_syscall_64+0x1b7/0xab0
<4> [363.698506]  ? ksys_read+0x72/0xf0
<4> [363.698520]  ? do_syscall_64+0x1b7/0xab0
<4> [363.698526]  ? do_syscall_64+0x1b7/0xab0
<4> [363.698532]  ? do_syscall_64+0x1b7/0xab0
<4> [363.698535]  ? exc_page_fault+0xbd/0x2c0
<4> [363.698545]  entry_SYSCALL_64_after_hwframe+0x76/0x7e
<4> [363.698549] RIP: 0033:0x715af255025d

And a similar backtrace in hsw_color_commit_arm().

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/display/intel_color.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index e7950655434b8..9cbc719370456 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1050,7 +1050,7 @@ static void hsw_color_commit_arm(struct intel_dsb *dsb,
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct intel_display *display = to_intel_display(crtc);
 
-	intel_de_write(display, GAMMA_MODE(crtc->pipe),
+	intel_de_write_fw(display, GAMMA_MODE(crtc->pipe),
 		       crtc_state->gamma_mode);
 
 	intel_de_write_fw(display, PIPE_CSC_MODE(crtc->pipe),
@@ -4078,7 +4078,7 @@ static void glk_load_lut_3d(struct intel_dsb *dsb,
 	int i, lut_size = drm_color_lut32_size(blob);
 	enum pipe pipe = crtc->pipe;
 
-	if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) & LUT_3D_READY) {
+	if (!dsb && intel_de_read_fw(display, LUT_3D_CTL(pipe)) & LUT_3D_READY) {
 		drm_err(display->drm, "[CRTC:%d:%s] 3D LUT not ready, not loading LUTs\n",
 			crtc->base.base.id, crtc->base.name);
 		return;
@@ -4096,7 +4096,7 @@ static void glk_lut_3d_commit(struct intel_dsb *dsb, struct intel_crtc *crtc, bo
 	enum pipe pipe = crtc->pipe;
 	u32 val = 0;
 
-	if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) & LUT_3D_READY) {
+	if (!dsb && intel_de_read_fw(display, LUT_3D_CTL(pipe)) & LUT_3D_READY) {
 		drm_err(display->drm, "[CRTC:%d:%s] 3D LUT not ready, not committing change\n",
 			crtc->base.base.id, crtc->base.name);
 		return;
-- 
2.51.0

RE: [i915-rt v5 11/21] drm/i915/display: Use intel_de_read/write_fw in colorops

[Shankar, Uma]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces@lists.freedesktop.org> On Behalf Of Maarten
> Lankhorst
> Sent: Wednesday, January 21, 2026 7:23 PM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Maarten Lankhorst <dev@lankhorst.se>
> Subject: [i915-rt v5 11/21] drm/i915/display: Use intel_de_read/write_fw in
> colorops
> 
> Using the _fw variants fixes a module load error on PTL:

Looks Good to me.
Reviewed-by: Uma Shankar <uma.shankar@intel.com>

> <4> [363.690050] Call Trace:
> <4> [363.690052]  <TASK>
> <4> [363.690055]  dump_stack_lvl+0x91/0xf0 <4> [363.690067]
> dump_stack+0x10/0x20 <4> [363.690074]  __might_resched+0x174/0x260 <4>
> [363.690087]  rt_spin_lock+0x63/0x200 <4> [363.690092]  ?
> intel_dmc_wl_get+0x3c/0x140 [xe] <4> [363.690470]  ?
> __lock_acquire+0x1195/0x2860 <4> [363.690487]  intel_dmc_wl_get+0x3c/0x140
> [xe] <4> [363.690842]  intel_color_plane_commit_arm+0xbc/0x140 [xe] <4>
> [363.691246]  icl_plane_update_arm+0x23f/0x280 [xe] <4> [363.691605]
> intel_plane_update_arm+0x74/0x170 [xe] <4> [363.691970]
> intel_crtc_planes_update_arm+0x3cb/0x4c0 [xe] <4> [363.692338]
> intel_update_crtc+0x1c3/0x840 [xe] <4> [363.692742]  ?
> intel_pre_update_crtc+0x2ce/0x470 [xe] <4> [363.693125]  ?
> intel_enable_crtc+0x123/0x150 [xe] <4> [363.693508]
> skl_commit_modeset_enables+0x4c4/0x720 [xe] <4> [363.693888]
> intel_atomic_commit_tail+0xd9d/0x1b30 [xe] <4> [363.694274]
> intel_atomic_commit+0x2e8/0x330 [xe] <4> [363.694621]  ?
> intel_atomic_commit+0x2e8/0x330 [xe] <4> [363.694956]
> drm_atomic_commit+0xaf/0xf0 <4> [363.694962]  ?
> __pfx___drm_printfn_info+0x10/0x10
> <4> [363.694978]  drm_client_modeset_commit_atomic+0x25c/0x2b0
> <4> [363.695018]  drm_client_modeset_commit_locked+0x63/0x1b0
> <4> [363.695029]  drm_client_modeset_commit+0x26/0x50
> <4> [363.695035]  __drm_fb_helper_restore_fbdev_mode_unlocked+0xdc/0x110
> <4> [363.695045]  drm_fb_helper_set_par+0x2f/0x50 <4> [363.695052]
> intel_fbdev_set_par+0x39/0x90 [xe] <4> [363.695365]  fbcon_init+0x283/0x680
> <4> [363.695382]  visual_init+0xf2/0x190 <4> [363.695396]
> do_bind_con_driver.isra.0+0x1f1/0x4c0
> <4> [363.695416]  do_take_over_console+0x181/0x220 <4> [363.695422]  ?
> vprintk_default+0x1d/0x30 <4> [363.695436]  do_fbcon_takeover+0x85/0x160 <4>
> [363.695447]  do_fb_registered+0x24c/0x2b0 <4> [363.695460]
> fbcon_fb_registered+0x3a/0x90 <4> [363.695469]
> do_register_framebuffer+0x216/0x320
> <4> [363.695488]  register_framebuffer+0x23/0x50 <4> [363.695494]
> __drm_fb_helper_initial_config_and_unlock+0x3ea/0x670
> <4> [363.695502]  ? trace_hardirqs_on+0x1e/0xd0 <4> [363.695526]
> drm_fb_helper_initial_config+0x3f/0x50
> <4> [363.695534]  drm_fbdev_client_hotplug+0x80/0xd0
> <4> [363.695543]  drm_client_register+0x8a/0xe0 <4> [363.695556]
> drm_fbdev_client_setup+0x127/0x1f0
> <4> [363.695563]  drm_client_setup+0xa7/0xe0 <4> [363.695569]
> drm_client_setup_with_color_mode+0x24/0x40
> <4> [363.695575]  intel_fbdev_setup+0x1c6/0x510 [xe] <4> [363.695857]
> intel_display_driver_register+0xb5/0x100 [xe] <4> [363.696188]  ?
> __pfx___drm_printfn_dbg+0x10/0x10 <4> [363.696194]  ?
> intel_display_driver_register+0x2e/0x100 [xe] <4> [363.696515]
> xe_display_register+0x29/0x40 [xe] <4> [363.696858]
> xe_device_probe+0x51a/0x9e0 [xe] <4> [363.697102]  ?
> __drmm_add_action+0x98/0x110 <4> [363.697108]  ?
> __pfx___drmm_mutex_release+0x10/0x10
> <4> [363.697116]  ? __drmm_add_action_or_reset+0x1e/0x50
> <4> [363.697130]  xe_pci_probe+0x396/0x620 [xe] <4> [363.697423]
> local_pci_probe+0x47/0xb0 <4> [363.697431]  pci_device_probe+0xf3/0x260 <4>
> [363.697444]  really_probe+0xf1/0x3c0 <4> [363.697451]
> __driver_probe_device+0x8c/0x180 <4> [363.697458]
> driver_probe_device+0x24/0xd0 <4> [363.697464]  __driver_attach+0x10f/0x220
> <4> [363.697468]  ? __pfx___driver_attach+0x10/0x10 <4> [363.697472]
> bus_for_each_dev+0x7f/0xe0 <4> [363.697484]  driver_attach+0x1e/0x30 <4>
> [363.697487]  bus_add_driver+0x154/0x290 <4> [363.697498]
> driver_register+0x5e/0x130 <4> [363.697504]  __pci_register_driver+0x84/0xa0
> <4> [363.697509]  xe_register_pci_driver+0x23/0x30 [xe] <4> [363.697762]
> xe_init+0x2c/0x110 [xe] <4> [363.698007]  ? __pfx_xe_init+0x10/0x10 [xe] <4>
> [363.698239]  do_one_initcall+0x60/0x3f0 <4> [363.698250]  ?
> __kmalloc_cache_noprof+0x470/0x690
> <4> [363.698267]  do_init_module+0x97/0x2b0 <4> [363.698275]
> load_module+0x2d08/0x2e30 <4> [363.698280]  ? __kernel_read+0x164/0x310
> <4> [363.698312]  ? kernel_read_file+0x2ca/0x340 <4> [363.698328]
> init_module_from_file+0x96/0xe0 <4> [363.698330]  ?
> init_module_from_file+0x96/0xe0 <4> [363.698357]
> idempotent_init_module+0x11d/0x340
> <4> [363.698384]  __x64_sys_finit_module+0x73/0xe0 <4> [363.698393]
> x64_sys_call+0x1e3d/0x26a0 <4> [363.698399]  do_syscall_64+0x93/0xab0 <4>
> [363.698413]  ? ext4_llseek+0xc3/0x130 <4> [363.698425]  ?
> ksys_lseek+0x55/0xd0 <4> [363.698438]  ? do_syscall_64+0x1b7/0xab0 <4>
> [363.698444]  ? switch_fpu_return+0xea/0x150 <4> [363.698454]  ?
> do_syscall_64+0x1b7/0xab0 <4> [363.698465]  ?
> kernfs_fop_read_iter+0x197/0x210 <4> [363.698470]  ?
> rw_verify_area+0x16f/0x200 <4> [363.698482]  ? vfs_read+0x22a/0x360 <4>
> [363.698498]  ? do_syscall_64+0x1b7/0xab0 <4> [363.698506]  ?
> ksys_read+0x72/0xf0 <4> [363.698520]  ? do_syscall_64+0x1b7/0xab0 <4>
> [363.698526]  ? do_syscall_64+0x1b7/0xab0 <4> [363.698532]  ?
> do_syscall_64+0x1b7/0xab0 <4> [363.698535]  ? exc_page_fault+0xbd/0x2c0 <4>
> [363.698545]  entry_SYSCALL_64_after_hwframe+0x76/0x7e
> <4> [363.698549] RIP: 0033:0x715af255025d
> 
> And a similar backtrace in hsw_color_commit_arm().
> 
> Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
> ---
>  drivers/gpu/drm/i915/display/intel_color.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> b/drivers/gpu/drm/i915/display/intel_color.c
> index e7950655434b8..9cbc719370456 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1050,7 +1050,7 @@ static void hsw_color_commit_arm(struct intel_dsb
> *dsb,
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>  	struct intel_display *display = to_intel_display(crtc);
> 
> -	intel_de_write(display, GAMMA_MODE(crtc->pipe),
> +	intel_de_write_fw(display, GAMMA_MODE(crtc->pipe),
>  		       crtc_state->gamma_mode);
> 
>  	intel_de_write_fw(display, PIPE_CSC_MODE(crtc->pipe), @@ -4078,7
> +4078,7 @@ static void glk_load_lut_3d(struct intel_dsb *dsb,
>  	int i, lut_size = drm_color_lut32_size(blob);
>  	enum pipe pipe = crtc->pipe;
> 
> -	if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) & LUT_3D_READY)
> {
> +	if (!dsb && intel_de_read_fw(display, LUT_3D_CTL(pipe)) &
> +LUT_3D_READY) {
>  		drm_err(display->drm, "[CRTC:%d:%s] 3D LUT not ready, not
> loading LUTs\n",
>  			crtc->base.base.id, crtc->base.name);
>  		return;
> @@ -4096,7 +4096,7 @@ static void glk_lut_3d_commit(struct intel_dsb *dsb,
> struct intel_crtc *crtc, bo
>  	enum pipe pipe = crtc->pipe;
>  	u32 val = 0;
> 
> -	if (!dsb && intel_de_read(display, LUT_3D_CTL(pipe)) & LUT_3D_READY)
> {
> +	if (!dsb && intel_de_read_fw(display, LUT_3D_CTL(pipe)) &
> +LUT_3D_READY) {
>  		drm_err(display->drm, "[CRTC:%d:%s] 3D LUT not ready, not
> committing change\n",
>  			crtc->base.base.id, crtc->base.name);
>  		return;
> --
> 2.51.0

[i915-rt v5 12/21] drm/i915/gt: Use spin_lock_irq() instead of local_irq_disable() + spin_lock()

[Maarten Lankhorst]

From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

execlists_dequeue() is invoked from a function which uses
local_irq_disable() to disable interrupts so the spin_lock() behaves
like spin_lock_irq().
This breaks PREEMPT_RT because local_irq_disable() + spin_lock() is not
the same as spin_lock_irq().

execlists_dequeue_irq() and execlists_dequeue() has each one caller
only. If intel_engine_cs::active::lock is acquired and released with the
_irq suffix then it behaves almost as if execlists_dequeue() would be
invoked with disabled interrupts. The difference is the last part of the
function which is then invoked with enabled interrupts.
I can't tell if this makes a difference. From looking at it, it might
work to move the last unlock at the end of the function as I didn't find
anything that would acquire the lock again.

Reported-by: Clark Williams <williams@redhat.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 .../drm/i915/gt/intel_execlists_submission.c    | 17 +++++------------
 1 file changed, 5 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 3df683b0402ad..948975e72d295 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -1300,7 +1300,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 	 * and context switches) submission.
 	 */
 
-	spin_lock(&sched_engine->lock);
+	spin_lock_irq(&sched_engine->lock);
 
 	/*
 	 * If the queue is higher priority than the last
@@ -1400,7 +1400,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 				 * Even if ELSP[1] is occupied and not worthy
 				 * of timeslices, our queue might be.
 				 */
-				spin_unlock(&sched_engine->lock);
+				spin_unlock_irq(&sched_engine->lock);
 				return;
 			}
 		}
@@ -1426,7 +1426,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 
 		if (last && !can_merge_rq(last, rq)) {
 			spin_unlock(&ve->base.sched_engine->lock);
-			spin_unlock(&engine->sched_engine->lock);
+			spin_unlock_irq(&engine->sched_engine->lock);
 			return; /* leave this for another sibling */
 		}
 
@@ -1588,7 +1588,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 	 */
 	sched_engine->queue_priority_hint = queue_prio(sched_engine);
 	i915_sched_engine_reset_on_empty(sched_engine);
-	spin_unlock(&sched_engine->lock);
+	spin_unlock_irq(&sched_engine->lock);
 
 	/*
 	 * We can skip poking the HW if we ended up with exactly the same set
@@ -1614,13 +1614,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 	}
 }
 
-static void execlists_dequeue_irq(struct intel_engine_cs *engine)
-{
-	local_irq_disable(); /* Suspend interrupts across request submission */
-	execlists_dequeue(engine);
-	local_irq_enable(); /* flush irq_work (e.g. breadcrumb enabling) */
-}
-
 static void clear_ports(struct i915_request **ports, int count)
 {
 	memset_p((void **)ports, NULL, count);
@@ -2475,7 +2468,7 @@ static void execlists_submission_tasklet(struct tasklet_struct *t)
 	}
 
 	if (!engine->execlists.pending[0]) {
-		execlists_dequeue_irq(engine);
+		execlists_dequeue(engine);
 		start_timeslice(engine);
 	}
 
-- 
2.51.0

[i915-rt v5 13/21] drm/i915: Drop the irqs_disabled() check

[Maarten Lankhorst]

From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

The !irqs_disabled() check triggers on PREEMPT_RT even with
i915_sched_engine::lock acquired. The reason is the lock is transformed
into a sleeping lock on PREEMPT_RT and does not disable interrupts.

There is no need to check for disabled interrupts. The lockdep
annotation below already check if the lock has been acquired by the
caller and will yell if the interrupts are not disabled.

Remove the !irqs_disabled() check.

Reported-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Acked-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/i915_request.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index d2c7b1090df08..f66f8efc70629 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -610,7 +610,6 @@ bool __i915_request_submit(struct i915_request *request)
 
 	RQ_TRACE(request, "\n");
 
-	GEM_BUG_ON(!irqs_disabled());
 	lockdep_assert_held(&engine->sched_engine->lock);
 
 	/*
@@ -719,7 +718,6 @@ void __i915_request_unsubmit(struct i915_request *request)
 	 */
 	RQ_TRACE(request, "\n");
 
-	GEM_BUG_ON(!irqs_disabled());
 	lockdep_assert_held(&engine->sched_engine->lock);
 
 	/*
-- 
2.51.0

[i915-rt v5 14/21] drm/i915/guc: Consider also RCU depth in busy loop.

[Maarten Lankhorst]

From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

intel_guc_send_busy_loop() looks at in_atomic() and irqs_disabled() to
decide if it should busy-spin while waiting or if it may sleep.
Both checks will report false on PREEMPT_RT if sleeping spinlocks are
acquired leading to RCU splats while the function sleeps.

Check also if RCU has been disabled.

Reported-by: "John B. Wyatt IV" <jwyatt@redhat.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/gt/uc/intel_guc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.h b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
index 053780f562c1a..b25fa8f4dc4bd 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.h
@@ -362,7 +362,7 @@ static inline int intel_guc_send_busy_loop(struct intel_guc *guc,
 {
 	int err;
 	unsigned int sleep_period_ms = 1;
-	bool not_atomic = !in_atomic() && !irqs_disabled();
+	bool not_atomic = !in_atomic() && !irqs_disabled() && !rcu_preempt_depth();
 
 	/*
 	 * FIXME: Have caller pass in if we are in an atomic context to avoid
-- 
2.51.0

[i915-rt v5 15/21] Revert "drm/i915: Depend on !PREEMPT_RT."

[Maarten Lankhorst]

From: Sebastian Andrzej Siewior <bigeasy@linutronix.de>

Once the known issues are addressed, it should be safe to enable the
driver.

Acked-by: Tvrtko Ursulin <tvrtko.ursulin@igalia.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 5e939004b6463..40a9234e6e5dc 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -3,7 +3,6 @@ config DRM_I915
 	tristate "Intel 8xx/9xx/G3x/G4x/HD Graphics"
 	depends on DRM
 	depends on X86 && PCI
-	depends on !PREEMPT_RT
 	select INTEL_GTT if X86
 	select INTERVAL_TREE
 	# we need shmfs for the swappable backing store, and in particular
-- 
2.51.0

[i915-rt v5 16/21] drm/i915/gt: Fix selftests on PREEMPT_RT

[Maarten Lankhorst]

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/gt/selftest_engine_pm.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
index 10e556a7eac45..c1eff9edd8a5e 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_pm.c
@@ -277,11 +277,11 @@ static int live_engine_busy_stats(void *arg)
 		st_engine_heartbeat_disable(engine);
 
 		ENGINE_TRACE(engine, "measuring idle time\n");
-		preempt_disable();
+		migrate_disable();
 		de = intel_engine_get_busy_time(engine, &t[0]);
 		udelay(100);
 		de = ktime_sub(intel_engine_get_busy_time(engine, &t[1]), de);
-		preempt_enable();
+		migrate_enable();
 		dt = ktime_sub(t[1], t[0]);
 		if (de < 0 || de > 10) {
 			pr_err("%s: reported %lldns [%d%%] busyness while sleeping [for %lldns]\n",
@@ -316,11 +316,11 @@ static int live_engine_busy_stats(void *arg)
 		}
 
 		ENGINE_TRACE(engine, "measuring busy time\n");
-		preempt_disable();
+		migrate_disable();
 		de = intel_engine_get_busy_time(engine, &t[0]);
 		mdelay(100);
 		de = ktime_sub(intel_engine_get_busy_time(engine, &t[1]), de);
-		preempt_enable();
+		migrate_enable();
 		dt = ktime_sub(t[1], t[0]);
 		if (100 * de < 95 * dt || 95 * de > 100 * dt) {
 			pr_err("%s: reported %lldns [%d%%] busyness while spinning [for %lldns]\n",
-- 
2.51.0

[i915-rt v5 17/21] drm/i915/gt: Set stop_timeout() correctly on PREEMPT-RT

[Maarten Lankhorst]

Also check if RCU is disabled for PREEMPT-RT, which is the case when
local_bh_disable() is called.

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 98a3a7a9de502..856250b457a55 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1607,7 +1607,7 @@ u64 intel_engine_get_last_batch_head(const struct intel_engine_cs *engine)
 
 static unsigned long stop_timeout(const struct intel_engine_cs *engine)
 {
-	if (in_atomic() || irqs_disabled()) /* inside atomic preempt-reset? */
+	if (in_atomic() || irqs_disabled() || rcu_preempt_depth()) /* inside atomic preempt-reset? */
 		return 0;
 
 	/*
-- 
2.51.0

[i915-rt v5 18/21] drm/i915/display: Do not take uncore lock in i915_get_vblank_counter

[Maarten Lankhorst]

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/display/intel_de.h       |  8 ++++++
 drivers/gpu/drm/i915/display/intel_vblank.c   |  4 +--
 drivers/gpu/drm/i915/intel_uncore.h           | 26 +++++++++++++------
 .../drm/xe/compat-i915-headers/intel_uncore.h |  7 +++++
 4 files changed, 35 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index a7ce3b875e06c..e4fda91007f0a 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -63,6 +63,14 @@ intel_de_read64_2x32(struct intel_display *display,
 	return val;
 }
 
+static inline u64
+intel_de_read64_2x32_fw(struct intel_display *display,
+			i915_reg_t lower_reg, i915_reg_t upper_reg)
+{
+	return intel_uncore_read64_2x32_fw(__to_uncore(display),
+					   lower_reg, upper_reg);
+}
+
 static inline void
 intel_de_posting_read(struct intel_display *display, i915_reg_t reg)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c
index e204c260b9aef..749127ae7794c 100644
--- a/drivers/gpu/drm/i915/display/intel_vblank.c
+++ b/drivers/gpu/drm/i915/display/intel_vblank.c
@@ -109,8 +109,8 @@ u32 i915_get_vblank_counter(struct drm_crtc *crtc)
 	 * we get a low value that's stable across two reads of the high
 	 * register.
 	 */
-	frame = intel_de_read64_2x32(display, PIPEFRAMEPIXEL(display, pipe),
-				     PIPEFRAME(display, pipe));
+	frame = intel_de_read64_2x32_fw(display, PIPEFRAMEPIXEL(display, pipe),
+				        PIPEFRAME(display, pipe));
 
 	pixel = frame & PIPE_PIXEL_MASK;
 	frame = (frame >> PIPE_FRAME_LOW_SHIFT) & 0xffffff;
diff --git a/drivers/gpu/drm/i915/intel_uncore.h b/drivers/gpu/drm/i915/intel_uncore.h
index fafc2ca9a2376..507398a562649 100644
--- a/drivers/gpu/drm/i915/intel_uncore.h
+++ b/drivers/gpu/drm/i915/intel_uncore.h
@@ -449,13 +449,28 @@ static inline void intel_uncore_rmw_fw(struct intel_uncore *uncore,
 		intel_uncore_write_fw(uncore, reg, val);
 }
 
+static inline u64
+intel_uncore_read64_2x32_fw(struct intel_uncore *uncore,
+			    i915_reg_t lower_reg, i915_reg_t upper_reg)
+{
+	u32 upper, lower, old_upper, loop = 0;
+	upper = intel_uncore_read_fw(uncore, upper_reg);
+	do {
+		old_upper = upper;
+		lower = intel_uncore_read_fw(uncore, lower_reg);
+		upper = intel_uncore_read_fw(uncore, upper_reg);
+	} while (upper != old_upper && loop++ < 2);
+
+	return (u64)upper << 32 | lower;
+}
+
 static inline u64
 intel_uncore_read64_2x32(struct intel_uncore *uncore,
 			 i915_reg_t lower_reg, i915_reg_t upper_reg)
 {
-	u32 upper, lower, old_upper, loop = 0;
 	enum forcewake_domains fw_domains;
 	unsigned long flags;
+	u64 ret;
 
 	fw_domains = intel_uncore_forcewake_for_reg(uncore, lower_reg,
 						    FW_REG_READ);
@@ -466,17 +481,12 @@ intel_uncore_read64_2x32(struct intel_uncore *uncore,
 	spin_lock_irqsave(&uncore->lock, flags);
 	intel_uncore_forcewake_get__locked(uncore, fw_domains);
 
-	upper = intel_uncore_read_fw(uncore, upper_reg);
-	do {
-		old_upper = upper;
-		lower = intel_uncore_read_fw(uncore, lower_reg);
-		upper = intel_uncore_read_fw(uncore, upper_reg);
-	} while (upper != old_upper && loop++ < 2);
+	ret = intel_uncore_read64_2x32_fw(uncore, lower_reg, upper_reg);
 
 	intel_uncore_forcewake_put__locked(uncore, fw_domains);
 	spin_unlock_irqrestore(&uncore->lock, flags);
 
-	return (u64)upper << 32 | lower;
+	return ret;
 }
 
 static inline int intel_uncore_write_and_verify(struct intel_uncore *uncore,
diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
index c05d4c4292d3c..b0cca68a46148 100644
--- a/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
+++ b/drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h
@@ -65,6 +65,13 @@ intel_uncore_read64_2x32(struct intel_uncore *uncore,
 	return (u64)upper << 32 | lower;
 }
 
+static inline u64
+intel_uncore_read64_2x32_fw(struct intel_uncore *uncore,
+			    i915_reg_t i915_lower_reg, i915_reg_t i915_upper_reg)
+{
+	return intel_uncore_read64_2x32(uncore, i915_lower_reg, i915_upper_reg);
+}
+
 static inline void intel_uncore_posting_read(struct intel_uncore *uncore,
 					     i915_reg_t i915_reg)
 {
-- 
2.51.0

[i915-rt v5 19/21] drm/i915/display: Remove uncore lock from vlv_atomic_update_fifo

[Maarten Lankhorst]

TODO: Grab uncore lock during entire vblank evasion before disabling
interrupts, and check what breaks?

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/display/i9xx_wm.c | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 39dfceb438ae4..62a988ce11ece 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -1863,7 +1863,6 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
 				   struct intel_crtc *crtc)
 {
 	struct intel_display *display = to_intel_display(crtc);
-	struct intel_uncore *uncore = to_intel_uncore(display->drm);
 	const struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	const struct vlv_fifo_state *fifo_state =
@@ -1892,7 +1891,6 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
 	 * intel_pipe_update_start() has already disabled interrupts
 	 * for us, so a plain spin_lock() is sufficient here.
 	 */
-	spin_lock(&uncore->lock);
 
 	switch (crtc->pipe) {
 	case PIPE_A:
@@ -1951,8 +1949,6 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
 	}
 
 	intel_de_read_fw(display, DSPARB(display));
-
-	spin_unlock(&uncore->lock);
 }
 
 #undef VLV_FIFO
-- 
2.51.0

[i915-rt v5 20/21] PREEMPT_RT injection

[Maarten Lankhorst]

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/Kconfig.debug | 15 ---------------
 drivers/gpu/drm/xe/Kconfig.debug   |  5 +++++
 kernel/Kconfig.preempt             |  4 ++--
 3 files changed, 7 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/Kconfig.debug b/drivers/gpu/drm/i915/Kconfig.debug
index 3562a02ef7adc..0ab10ff41e38d 100644
--- a/drivers/gpu/drm/i915/Kconfig.debug
+++ b/drivers/gpu/drm/i915/Kconfig.debug
@@ -233,21 +233,6 @@ config DRM_I915_LOW_LEVEL_TRACEPOINTS
 
 	  If in doubt, say "N".
 
-config DRM_I915_DEBUG_VBLANK_EVADE
-	bool "Enable extra debug warnings for vblank evasion"
-	depends on DRM_I915
-	default n
-	help
-	  Choose this option to turn on extra debug warnings for the
-	  vblank evade mechanism. This gives a warning every time the
-	  the deadline allotted for the vblank evade critical section
-	  is exceeded, even if there isn't an actual risk of missing
-	  the vblank.
-
-	  Recommended for driver developers only.
-
-	  If in doubt, say "N".
-
 config DRM_I915_DEBUG_RUNTIME_PM
 	bool "Enable extra state checking for runtime PM"
 	depends on DRM_I915
diff --git a/drivers/gpu/drm/xe/Kconfig.debug b/drivers/gpu/drm/xe/Kconfig.debug
index 01227c77f6d70..1d5f11c6e88f3 100644
--- a/drivers/gpu/drm/xe/Kconfig.debug
+++ b/drivers/gpu/drm/xe/Kconfig.debug
@@ -30,6 +30,11 @@ config DRM_XE_DEBUG
 
 	  If in doubt, say "N".
 
+config DRM_I915_DEBUG_VBLANK_EVADE
+        def_bool y
+        depends on DRM_XE
+
+
 config DRM_XE_DEBUG_VM
 	bool "Enable extra VM debugging info"
 	default n
diff --git a/kernel/Kconfig.preempt b/kernel/Kconfig.preempt
index da326800c1c9b..68a6d42c55abe 100644
--- a/kernel/Kconfig.preempt
+++ b/kernel/Kconfig.preempt
@@ -87,9 +87,9 @@ config PREEMPT_LAZY
 endchoice
 
 config PREEMPT_RT
-	bool "Fully Preemptible Kernel (Real-Time)"
-	depends on EXPERT && ARCH_SUPPORTS_RT && !COMPILE_TEST
+	def_bool y
 	select PREEMPTION
+	depends on ARCH_SUPPORTS_RT
 	help
 	  This option turns the kernel into a real-time kernel by replacing
 	  various locking primitives (spinlocks, rwlocks, etc.) with
-- 
2.51.0

Re: [i915-rt v5 20/21] PREEMPT_RT injection

[kernel test robot]

Hi Maarten,

kernel test robot noticed the following build warnings:

[auto build test WARNING on drm-i915/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20260121]
[cannot apply to drm-i915/for-linux-next-fixes drm-xe/drm-xe-next linus/master v6.19-rc6]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Maarten-Lankhorst/drm-i915-display-Fix-intel_lpe_audio_irq_handler-for-PREEMPT-RT/20260121-223353
base:   https://gitlab.freedesktop.org/drm/i915/kernel.git for-linux-next
patch link:    https://lore.kernel.org/r/20260121135318.651622-21-dev%40lankhorst.se
patch subject: [i915-rt v5 20/21] PREEMPT_RT injection
config: riscv-allyesconfig (https://download.01.org/0day-ci/archive/20260122/202601220757.XPYUi6Wb-lkp@intel.com/config)
compiler: clang version 16.0.6 (https://github.com/llvm/llvm-project 7cbf1a2591520c2491aa35339f227775f4d3adf6)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260122/202601220757.XPYUi6Wb-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601220757.XPYUi6Wb-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/virt/coco/tsm-core.c:16:22: warning: unused variable 'tsm_rwsem' [-Wunused-variable]
   static DECLARE_RWSEM(tsm_rwsem);
                        ^
   1 warning generated.


vim +/tsm_rwsem +16 drivers/virt/coco/tsm-core.c

603c646f001008e Dan Williams 2025-10-31  14  
603c646f001008e Dan Williams 2025-10-31  15  static struct class *tsm_class;
603c646f001008e Dan Williams 2025-10-31 @16  static DECLARE_RWSEM(tsm_rwsem);
603c646f001008e Dan Williams 2025-10-31  17  static DEFINE_IDA(tsm_ida);
603c646f001008e Dan Williams 2025-10-31  18  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [i915-rt v5 20/21] PREEMPT_RT injection

[kernel test robot]

Hi Maarten,

kernel test robot noticed the following build warnings:

[auto build test WARNING on drm-i915/for-linux-next]
[also build test WARNING on drm-tip/drm-tip next-20260121]
[cannot apply to drm-i915/for-linux-next-fixes drm-xe/drm-xe-next linus/master v6.19-rc6]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Maarten-Lankhorst/drm-i915-display-Fix-intel_lpe_audio_irq_handler-for-PREEMPT-RT/20260121-223353
base:   https://gitlab.freedesktop.org/drm/i915/kernel.git for-linux-next
patch link:    https://lore.kernel.org/r/20260121135318.651622-21-dev%40lankhorst.se
patch subject: [i915-rt v5 20/21] PREEMPT_RT injection
config: i386-buildonly-randconfig-002-20260122 (https://download.01.org/0day-ci/archive/20260122/202601221037.9YksOSlP-lkp@intel.com/config)
compiler: gcc-14 (Debian 14.2.0-19) 14.2.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260122/202601221037.9YksOSlP-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202601221037.9YksOSlP-lkp@intel.com/

All warnings (new ones prefixed by >>):

   In file included from include/linux/memory_hotplug.h:7,
                    from include/linux/mmzone.h:1534,
                    from include/linux/gfp.h:7,
                    from include/linux/slab.h:16,
                    from include/linux/resource_ext.h:11,
                    from include/linux/acpi.h:14,
                    from drivers/platform/x86/lenovo/wmi-gamezone.c:11:
>> drivers/platform/x86/lenovo/wmi-gamezone.c:34:31: warning: 'gz_chain_head' defined but not used [-Wunused-variable]
      34 | static BLOCKING_NOTIFIER_HEAD(gz_chain_head);
         |                               ^~~~~~~~~~~~~
   include/linux/notifier.h:119:39: note: in definition of macro 'BLOCKING_NOTIFIER_HEAD'
     119 |         struct blocking_notifier_head name =                    \
         |                                       ^~~~


vim +/gz_chain_head +34 drivers/platform/x86/lenovo/wmi-gamezone.c

22024ac5366f06 Derek J. Clark 2025-07-01  33  
22024ac5366f06 Derek J. Clark 2025-07-01 @34  static BLOCKING_NOTIFIER_HEAD(gz_chain_head);
22024ac5366f06 Derek J. Clark 2025-07-01  35  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

[i915-rt v5 21/21] FOR-CI: drm/i915: Reset lockdep after selftest unload

[Maarten Lankhorst]

We're hitting a bug in CI where MAX_STACK_TRACE_ENTRIES is set too low.
My guess is the repeated loading/unloading is creating multiples of the
same entries. As a hack just reset lockdep. This might only be necessary
for CI + PREEMPT_RT.

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 drivers/gpu/drm/i915/i915_module.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_module.c b/drivers/gpu/drm/i915/i915_module.c
index 5d9c35b5a1820..4c135688d9660 100644
--- a/drivers/gpu/drm/i915/i915_module.c
+++ b/drivers/gpu/drm/i915/i915_module.c
@@ -117,6 +117,12 @@ static void __exit i915_exit(void)
 		if (init_funcs[i].exit)
 			init_funcs[i].exit();
 	}
+
+	/* Workaround for "MAX_STACK_TRACE_ENTRIES" too low, reset all locks after exit */
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+	if (i915_selftest.live || i915_selftest.mock || i915_selftest.perf)
+		lockdep_reset();
+#endif
 }
 
 module_init(i915_init);
-- 
2.51.0

[i915-rt v5] FOR-CI: drm/i915: Reset lockdep after selftest unload

[Maarten Lankhorst]

We're hitting a bug in CI where MAX_STACK_TRACE_ENTRIES is set too low.
My guess is the repeated loading/unloading is creating multiples of the
same entries. As a hack just reset lockdep. This might only be necessary
for CI + PREEMPT_RT.

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
Forgot to commit the EXPORT_SYMBOL_GPL change.

 drivers/gpu/drm/i915/i915_module.c | 6 ++++++
 kernel/locking/lockdep.c           | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_module.c b/drivers/gpu/drm/i915/i915_module.c
index 5d9c35b5a1820..4c135688d9660 100644
--- a/drivers/gpu/drm/i915/i915_module.c
+++ b/drivers/gpu/drm/i915/i915_module.c
@@ -117,6 +117,12 @@ static void __exit i915_exit(void)
 		if (init_funcs[i].exit)
 			init_funcs[i].exit();
 	}
+
+	/* Workaround for "MAX_STACK_TRACE_ENTRIES" too low, reset all locks after exit */
+#if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
+	if (i915_selftest.live || i915_selftest.mock || i915_selftest.perf)
+		lockdep_reset();
+#endif
 }
 
 module_init(i915_init);
diff --git a/kernel/locking/lockdep.c b/kernel/locking/lockdep.c
index b9edc0339273d..d4804d94a10e8 100644
--- a/kernel/locking/lockdep.c
+++ b/kernel/locking/lockdep.c
@@ -6188,6 +6188,7 @@ void lockdep_reset(void)
 		INIT_HLIST_HEAD(chainhash_table + i);
 	raw_local_irq_restore(flags);
 }
+EXPORT_SYMBOL_GPL(lockdep_reset);
 
 /* Remove a class from a lock chain. Must be called with the graph lock held. */
 static void remove_class_from_lock_chain(struct pending_free *pf,
-- 
2.51.0

[i915-rt v5] FOR-CI: try bumping MAX_STACK_TRACE_ENTRIES?

[Maarten Lankhorst]

We're hitting a bug in CI where MAX_STACK_TRACE_ENTRIES is set too low.
My guess is the repeated loading/unloading is creating multiples of the
same entries. As a hack just reset lockdep. This might only be necessary
for CI + PREEMPT_RT.

Signed-off-by: Maarten Lankhorst <dev@lankhorst.se>
---
 lib/Kconfig.debug | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index 1e1776049a84e..e8da58d2bf5c8 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -1545,8 +1545,8 @@ config LOCKDEP_CHAINS_BITS
 config LOCKDEP_STACK_TRACE_BITS
 	int "Size for MAX_STACK_TRACE_ENTRIES (as Nth power of 2)"
 	depends on LOCKDEP && !LOCKDEP_SMALL
-	range 10 26
-	default 19
+	range 22 26
+	default 22
 	help
 	  Try increasing this value if you hit "BUG: MAX_STACK_TRACE_ENTRIES too low!" message.
 
-- 
2.51.0

✗ Fi.CI.BUILD: failure for drm/i915/display: All patches to make PREEMPT_RT work on i915 + xe. (rev9)

[Patchwork]

== Series Details ==

Series: drm/i915/display: All patches to make PREEMPT_RT work on i915 + xe. (rev9)
URL   : https://patchwork.freedesktop.org/series/159035/
State : failure

== Summary ==

Error: make failed
  CALL    scripts/checksyscalls.sh
  DESCEND objtool
  INSTALL libsubcmd_headers
  HDRTEST drivers/gpu/drm/xe/generated/xe_wa_oob.h
  HDRTEST drivers/gpu/drm/xe/generated/xe_device_wa_oob.h
  MODPOST Module.symvers
ERROR: modpost: "lockdep_reset" [drivers/gpu/drm/i915/i915.ko] undefined!
make[2]: *** [scripts/Makefile.modpost:147: Module.symvers] Error 1
make[1]: *** [/home/kbuild2/kernel/Makefile:2004: modpost] Error 2
make: *** [Makefile:248: __sub-make] Error 2
Build failed, no error log produced

✗ i915.CI.BAT: failure for drm/i915/display: All patches to make PREEMPT_RT work on i915 + xe. (rev10)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 28940 bytes --]

== Series Details ==

Series: drm/i915/display: All patches to make PREEMPT_RT work on i915 + xe. (rev10)
URL   : https://patchwork.freedesktop.org/series/159035/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_17866 -> Patchwork_159035v10
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_159035v10 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_159035v10, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/index.html

Participating hosts (42 -> 39)
------------------------------

  Additional (1): fi-ilk-650 
  Missing    (4): bat-dg2-13 bat-dg1-6 fi-snb-2520m fi-pnv-d510 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_159035v10:

### IGT changes ###

#### Possible regressions ####

  * igt@dmabuf@all-tests:
    - fi-ilk-650:         NOTRUN -> [ABORT][1] +1 other test abort
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-ilk-650/igt@dmabuf@all-tests.html

  * igt@gem_exec_fence@basic-busy:
    - bat-jsl-1:          [PASS][2] -> [ABORT][3] +1 other test abort
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-jsl-1/igt@gem_exec_fence@basic-busy.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-jsl-1/igt@gem_exec_fence@basic-busy.html

  * igt@i915_pm_rpm@module-reload:
    - fi-bsw-n3050:       [PASS][4] -> [ABORT][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-bsw-n3050/igt@i915_pm_rpm@module-reload.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-bsw-n3050/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live:
    - fi-hsw-4770:        [PASS][6] -> [ABORT][7] +1 other test abort
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-hsw-4770/igt@i915_selftest@live.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-hsw-4770/igt@i915_selftest@live.html
    - fi-ivb-3770:        [PASS][8] -> [ABORT][9] +1 other test abort
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-ivb-3770/igt@i915_selftest@live.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-ivb-3770/igt@i915_selftest@live.html
    - bat-mtlp-8:         [PASS][10] -> [ABORT][11] +1 other test abort
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-mtlp-8/igt@i915_selftest@live.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-mtlp-8/igt@i915_selftest@live.html
    - bat-dg2-8:          [PASS][12] -> [ABORT][13] +1 other test abort
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-dg2-8/igt@i915_selftest@live.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-dg2-8/igt@i915_selftest@live.html
    - bat-adls-6:         [PASS][14] -> [ABORT][15] +1 other test abort
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-adls-6/igt@i915_selftest@live.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-adls-6/igt@i915_selftest@live.html
    - bat-arlh-3:         [PASS][16] -> [ABORT][17] +1 other test abort
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-arlh-3/igt@i915_selftest@live.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-arlh-3/igt@i915_selftest@live.html
    - fi-glk-j4005:       [PASS][18] -> [ABORT][19] +1 other test abort
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-glk-j4005/igt@i915_selftest@live.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-glk-j4005/igt@i915_selftest@live.html
    - bat-rpls-4:         [PASS][20] -> [ABORT][21] +1 other test abort
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-rpls-4/igt@i915_selftest@live.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-rpls-4/igt@i915_selftest@live.html
    - bat-jsl-5:          [PASS][22] -> [ABORT][23] +1 other test abort
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-jsl-5/igt@i915_selftest@live.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-jsl-5/igt@i915_selftest@live.html
    - bat-arls-5:         [PASS][24] -> [ABORT][25] +1 other test abort
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-arls-5/igt@i915_selftest@live.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-arls-5/igt@i915_selftest@live.html
    - bat-arlh-2:         [PASS][26] -> [ABORT][27] +1 other test abort
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-arlh-2/igt@i915_selftest@live.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-arlh-2/igt@i915_selftest@live.html
    - fi-rkl-11600:       [PASS][28] -> [ABORT][29] +1 other test abort
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-rkl-11600/igt@i915_selftest@live.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-rkl-11600/igt@i915_selftest@live.html
    - fi-cfl-guc:         [PASS][30] -> [ABORT][31] +1 other test abort
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-cfl-guc/igt@i915_selftest@live.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-cfl-guc/igt@i915_selftest@live.html
    - fi-kbl-x1275:       [PASS][32] -> [ABORT][33] +1 other test abort
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-kbl-x1275/igt@i915_selftest@live.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-kbl-x1275/igt@i915_selftest@live.html
    - fi-cfl-8109u:       [PASS][34] -> [ABORT][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-cfl-8109u/igt@i915_selftest@live.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-cfl-8109u/igt@i915_selftest@live.html
    - fi-skl-6600u:       [PASS][36] -> [ABORT][37]
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-skl-6600u/igt@i915_selftest@live.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-skl-6600u/igt@i915_selftest@live.html

  * igt@i915_selftest@live@active:
    - bat-mtlp-8:         [PASS][38] -> [INCOMPLETE][39]
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-mtlp-8/igt@i915_selftest@live@active.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-mtlp-8/igt@i915_selftest@live@active.html

  * igt@i915_selftest@live@client:
    - bat-adls-6:         [PASS][40] -> [DMESG-WARN][41] +4 other tests dmesg-warn
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-adls-6/igt@i915_selftest@live@client.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-adls-6/igt@i915_selftest@live@client.html
    - bat-rpls-4:         [PASS][42] -> [DMESG-WARN][43] +1 other test dmesg-warn
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-rpls-4/igt@i915_selftest@live@client.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-rpls-4/igt@i915_selftest@live@client.html
    - fi-kbl-7567u:       [PASS][44] -> [ABORT][45] +1 other test abort
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-kbl-7567u/igt@i915_selftest@live@client.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-kbl-7567u/igt@i915_selftest@live@client.html
    - fi-cfl-8109u:       [PASS][46] -> [INCOMPLETE][47]
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-cfl-8109u/igt@i915_selftest@live@client.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-cfl-8109u/igt@i915_selftest@live@client.html
    - fi-tgl-1115g4:      [PASS][48] -> [INCOMPLETE][49]
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-tgl-1115g4/igt@i915_selftest@live@client.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-tgl-1115g4/igt@i915_selftest@live@client.html

  * igt@i915_selftest@live@coherency:
    - fi-cfl-8109u:       [PASS][50] -> [DMESG-WARN][51]
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-cfl-8109u/igt@i915_selftest@live@coherency.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-cfl-8109u/igt@i915_selftest@live@coherency.html
    - bat-rplp-1:         [PASS][52] -> [INCOMPLETE][53]
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-rplp-1/igt@i915_selftest@live@coherency.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-rplp-1/igt@i915_selftest@live@coherency.html

  * igt@i915_selftest@live@dmabuf:
    - bat-jsl-5:          [PASS][54] -> [DMESG-WARN][55] +1 other test dmesg-warn
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-jsl-5/igt@i915_selftest@live@dmabuf.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-jsl-5/igt@i915_selftest@live@dmabuf.html

  * igt@i915_selftest@live@evict:
    - fi-kbl-7567u:       [PASS][56] -> [DMESG-WARN][57] +2 other tests dmesg-warn
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-kbl-7567u/igt@i915_selftest@live@evict.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-kbl-7567u/igt@i915_selftest@live@evict.html
    - bat-jsl-5:          [PASS][58] -> [INCOMPLETE][59]
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-jsl-5/igt@i915_selftest@live@evict.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-jsl-5/igt@i915_selftest@live@evict.html

  * igt@i915_selftest@live@gem:
    - fi-skl-6600u:       [PASS][60] -> [DMESG-FAIL][61]
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-skl-6600u/igt@i915_selftest@live@gem.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-skl-6600u/igt@i915_selftest@live@gem.html

  * igt@i915_selftest@live@gem_contexts:
    - fi-kbl-x1275:       [PASS][62] -> [DMESG-WARN][63] +2 other tests dmesg-warn
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-kbl-x1275/igt@i915_selftest@live@gem_contexts.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-kbl-x1275/igt@i915_selftest@live@gem_contexts.html
    - fi-kbl-8809g:       [PASS][64] -> [INCOMPLETE][65] +1 other test incomplete
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-kbl-8809g/igt@i915_selftest@live@gem_contexts.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-kbl-8809g/igt@i915_selftest@live@gem_contexts.html
    - bat-kbl-2:          [PASS][66] -> [ABORT][67] +1 other test abort
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-kbl-2/igt@i915_selftest@live@gem_contexts.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-kbl-2/igt@i915_selftest@live@gem_contexts.html
    - bat-atsm-1:         [PASS][68] -> [ABORT][69]
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-atsm-1/igt@i915_selftest@live@gem_contexts.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-atsm-1/igt@i915_selftest@live@gem_contexts.html
    - bat-dg2-8:          [PASS][70] -> [INCOMPLETE][71]
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-dg2-8/igt@i915_selftest@live@gem_contexts.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-dg2-8/igt@i915_selftest@live@gem_contexts.html

  * igt@i915_selftest@live@gem_migrate:
    - bat-atsm-1:         [PASS][72] -> [DMESG-FAIL][73]
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-atsm-1/igt@i915_selftest@live@gem_migrate.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-atsm-1/igt@i915_selftest@live@gem_migrate.html

  * igt@i915_selftest@live@gt_heartbeat:
    - bat-arlh-2:         [PASS][74] -> [DMESG-WARN][75] +5 other tests dmesg-warn
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-arlh-2/igt@i915_selftest@live@gt_heartbeat.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-arlh-2/igt@i915_selftest@live@gt_heartbeat.html
    - bat-twl-2:          [PASS][76] -> [ABORT][77]
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-twl-2/igt@i915_selftest@live@gt_heartbeat.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-twl-2/igt@i915_selftest@live@gt_heartbeat.html
    - bat-dg2-14:         [PASS][78] -> [INCOMPLETE][79]
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-dg2-14/igt@i915_selftest@live@gt_heartbeat.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-dg2-14/igt@i915_selftest@live@gt_heartbeat.html
    - bat-mtlp-9:         [PASS][80] -> [INCOMPLETE][81]
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-mtlp-9/igt@i915_selftest@live@gt_heartbeat.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-mtlp-9/igt@i915_selftest@live@gt_heartbeat.html

  * igt@i915_selftest@live@gt_lrc:
    - bat-dg2-14:         [PASS][82] -> [ABORT][83] +1 other test abort
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-dg2-14/igt@i915_selftest@live@gt_lrc.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-dg2-14/igt@i915_selftest@live@gt_lrc.html

  * igt@i915_selftest@live@gt_mocs:
    - bat-mtlp-9:         [PASS][84] -> [ABORT][85] +1 other test abort
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-mtlp-9/igt@i915_selftest@live@gt_mocs.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-mtlp-9/igt@i915_selftest@live@gt_mocs.html

  * igt@i915_selftest@live@gt_pm:
    - bat-twl-2:          [PASS][86] -> [DMESG-WARN][87]
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-twl-2/igt@i915_selftest@live@gt_pm.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-twl-2/igt@i915_selftest@live@gt_pm.html
    - bat-dg1-7:          [PASS][88] -> [INCOMPLETE][89]
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-dg1-7/igt@i915_selftest@live@gt_pm.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-dg1-7/igt@i915_selftest@live@gt_pm.html
    - bat-twl-1:          [PASS][90] -> [ABORT][91]
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-twl-1/igt@i915_selftest@live@gt_pm.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-twl-1/igt@i915_selftest@live@gt_pm.html

  * igt@i915_selftest@live@gt_tlb:
    - bat-dg2-9:          [PASS][92] -> [INCOMPLETE][93]
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-dg2-9/igt@i915_selftest@live@gt_tlb.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-dg2-9/igt@i915_selftest@live@gt_tlb.html
    - bat-mtlp-8:         [PASS][94] -> [DMESG-WARN][95]
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-mtlp-8/igt@i915_selftest@live@gt_tlb.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-mtlp-8/igt@i915_selftest@live@gt_tlb.html

  * igt@i915_selftest@live@gtt:
    - bat-arlh-2:         [PASS][96] -> [INCOMPLETE][97]
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-arlh-2/igt@i915_selftest@live@gtt.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-arlh-2/igt@i915_selftest@live@gtt.html
    - bat-adlp-11:        [PASS][98] -> [INCOMPLETE][99]
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-adlp-11/igt@i915_selftest@live@gtt.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-adlp-11/igt@i915_selftest@live@gtt.html

  * igt@i915_selftest@live@hugepages:
    - fi-glk-j4005:       [PASS][100] -> [INCOMPLETE][101]
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-glk-j4005/igt@i915_selftest@live@hugepages.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-glk-j4005/igt@i915_selftest@live@hugepages.html

  * igt@i915_selftest@live@migrate:
    - bat-adlp-9:         [PASS][102] -> [ABORT][103]
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-adlp-9/igt@i915_selftest@live@migrate.html
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-adlp-9/igt@i915_selftest@live@migrate.html
    - bat-apl-1:          [PASS][104] -> [DMESG-FAIL][105]
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-apl-1/igt@i915_selftest@live@migrate.html
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-apl-1/igt@i915_selftest@live@migrate.html
    - bat-arls-5:         [PASS][106] -> [DMESG-FAIL][107]
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-arls-5/igt@i915_selftest@live@migrate.html
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-arls-5/igt@i915_selftest@live@migrate.html
    - bat-adlp-6:         [PASS][108] -> [ABORT][109]
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-adlp-6/igt@i915_selftest@live@migrate.html
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-adlp-6/igt@i915_selftest@live@migrate.html
    - bat-twl-2:          [PASS][110] -> [INCOMPLETE][111]
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-twl-2/igt@i915_selftest@live@migrate.html
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-twl-2/igt@i915_selftest@live@migrate.html
    - fi-bsw-nick:        [PASS][112] -> [DMESG-FAIL][113]
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-bsw-nick/igt@i915_selftest@live@migrate.html
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-bsw-nick/igt@i915_selftest@live@migrate.html
    - bat-arls-6:         [PASS][114] -> [ABORT][115] +1 other test abort
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-arls-6/igt@i915_selftest@live@migrate.html
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-arls-6/igt@i915_selftest@live@migrate.html

  * igt@i915_selftest@live@mman:
    - bat-adlp-9:         [PASS][116] -> [INCOMPLETE][117]
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-adlp-9/igt@i915_selftest@live@mman.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-adlp-9/igt@i915_selftest@live@mman.html
    - bat-apl-1:          [PASS][118] -> [ABORT][119] +1 other test abort
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-apl-1/igt@i915_selftest@live@mman.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-apl-1/igt@i915_selftest@live@mman.html
    - bat-adlp-11:        [PASS][120] -> [ABORT][121]
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-adlp-11/igt@i915_selftest@live@mman.html
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-adlp-11/igt@i915_selftest@live@mman.html
    - fi-tgl-1115g4:      [PASS][122] -> [ABORT][123] +1 other test abort
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-tgl-1115g4/igt@i915_selftest@live@mman.html
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-tgl-1115g4/igt@i915_selftest@live@mman.html
    - fi-bsw-nick:        [PASS][124] -> [ABORT][125] +1 other test abort
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-bsw-nick/igt@i915_selftest@live@mman.html
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-bsw-nick/igt@i915_selftest@live@mman.html

  * igt@i915_selftest@live@objects:
    - bat-adlp-6:         [PASS][126] -> [INCOMPLETE][127]
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-adlp-6/igt@i915_selftest@live@objects.html
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-adlp-6/igt@i915_selftest@live@objects.html
    - fi-skl-6600u:       [PASS][128] -> [DMESG-WARN][129] +3 other tests dmesg-warn
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-skl-6600u/igt@i915_selftest@live@objects.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-skl-6600u/igt@i915_selftest@live@objects.html
    - bat-arls-6:         [PASS][130] -> [DMESG-FAIL][131]
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-arls-6/igt@i915_selftest@live@objects.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-arls-6/igt@i915_selftest@live@objects.html

  * igt@i915_selftest@live@requests:
    - bat-dg2-8:          [PASS][132] -> [DMESG-WARN][133] +3 other tests dmesg-warn
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-dg2-8/igt@i915_selftest@live@requests.html
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-dg2-8/igt@i915_selftest@live@requests.html
    - bat-arlh-3:         [PASS][134] -> [DMESG-FAIL][135]
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-arlh-3/igt@i915_selftest@live@requests.html
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-arlh-3/igt@i915_selftest@live@requests.html
    - bat-rplp-1:         [PASS][136] -> [ABORT][137]
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-rplp-1/igt@i915_selftest@live@requests.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-rplp-1/igt@i915_selftest@live@requests.html
    - bat-adlp-6:         [PASS][138] -> [DMESG-WARN][139]
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-adlp-6/igt@i915_selftest@live@requests.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-adlp-6/igt@i915_selftest@live@requests.html

  * igt@i915_selftest@live@reset:
    - fi-cfl-8700k:       [PASS][140] -> [ABORT][141] +1 other test abort
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-cfl-8700k/igt@i915_selftest@live@reset.html
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-cfl-8700k/igt@i915_selftest@live@reset.html
    - bat-kbl-2:          [PASS][142] -> [DMESG-FAIL][143]
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-kbl-2/igt@i915_selftest@live@reset.html
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-kbl-2/igt@i915_selftest@live@reset.html
    - bat-rpls-4:         [PASS][144] -> [DMESG-FAIL][145]
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-rpls-4/igt@i915_selftest@live@reset.html
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-rpls-4/igt@i915_selftest@live@reset.html
    - fi-kbl-7567u:       [PASS][146] -> [DMESG-FAIL][147]
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-kbl-7567u/igt@i915_selftest@live@reset.html
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-kbl-7567u/igt@i915_selftest@live@reset.html
    - bat-twl-1:          [PASS][148] -> [DMESG-FAIL][149]
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-twl-1/igt@i915_selftest@live@reset.html
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-twl-1/igt@i915_selftest@live@reset.html
    - bat-apl-1:          [PASS][150] -> [INCOMPLETE][151]
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-apl-1/igt@i915_selftest@live@reset.html
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-apl-1/igt@i915_selftest@live@reset.html

  * igt@i915_selftest@live@workarounds:
    - bat-dg1-7:          [PASS][152] -> [ABORT][153] +1 other test abort
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-dg1-7/igt@i915_selftest@live@workarounds.html
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-dg1-7/igt@i915_selftest@live@workarounds.html
    - bat-dg2-9:          [PASS][154] -> [ABORT][155] +1 other test abort
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-dg2-9/igt@i915_selftest@live@workarounds.html
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-dg2-9/igt@i915_selftest@live@workarounds.html

  
#### Warnings ####

  * igt@i915_selftest@live:
    - bat-atsm-1:         [DMESG-FAIL][156] ([i915#12061] / [i915#14204]) -> [ABORT][157]
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-atsm-1/igt@i915_selftest@live.html
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-atsm-1/igt@i915_selftest@live.html

  
Known issues
------------

  Here are the changes found in Patchwork_159035v10 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live:
    - bat-adlp-9:         [PASS][158] -> [ABORT][159] ([i915#14365])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-adlp-9/igt@i915_selftest@live.html
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-adlp-9/igt@i915_selftest@live.html
    - bat-twl-1:          [PASS][160] -> [ABORT][161] ([i915#14365])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-twl-1/igt@i915_selftest@live.html
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-twl-1/igt@i915_selftest@live.html
    - bat-rplp-1:         [PASS][162] -> [ABORT][163] ([i915#14365])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-rplp-1/igt@i915_selftest@live.html
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-rplp-1/igt@i915_selftest@live.html
    - bat-adlp-11:        [PASS][164] -> [ABORT][165] ([i915#14365])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-adlp-11/igt@i915_selftest@live.html
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-adlp-11/igt@i915_selftest@live.html
    - bat-adlp-6:         [PASS][166] -> [ABORT][167] ([i915#14365])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-adlp-6/igt@i915_selftest@live.html
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-adlp-6/igt@i915_selftest@live.html
    - bat-twl-2:          [PASS][168] -> [ABORT][169] ([i915#14365])
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-twl-2/igt@i915_selftest@live.html
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-twl-2/igt@i915_selftest@live.html

  * igt@i915_selftest@live@vma:
    - fi-cfl-8109u:       [PASS][170] -> [ABORT][171] ([i915#11814])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-cfl-8109u/igt@i915_selftest@live@vma.html
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-cfl-8109u/igt@i915_selftest@live@vma.html
    - fi-skl-6600u:       [PASS][172] -> [ABORT][173] ([i915#11814])
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/fi-skl-6600u/igt@i915_selftest@live@vma.html
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-skl-6600u/igt@i915_selftest@live@vma.html

  * igt@kms_pm_rpm@basic-pci-d3-state:
    - fi-ilk-650:         NOTRUN -> [SKIP][174] +25 other tests skip
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/fi-ilk-650/igt@kms_pm_rpm@basic-pci-d3-state.html

  
#### Warnings ####

  * igt@i915_selftest@live@mman:
    - bat-atsm-1:         [DMESG-FAIL][175] ([i915#14204]) -> [DMESG-FAIL][176] ([i915#13929])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17866/bat-atsm-1/igt@i915_selftest@live@mman.html
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/bat-atsm-1/igt@i915_selftest@live@mman.html

  
  [i915#11814]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11814
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#13929]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13929
  [i915#14204]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14204
  [i915#14365]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14365


Build changes
-------------

  * Linux: CI_DRM_17866 -> Patchwork_159035v10

  CI-20190529: 20190529
  CI_DRM_17866: d081bd6774793057d23d5e7942dbc6dbd1c20bd3 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8709: 16ce286cac6acc9669a1c758572ae9fceb483c46 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_159035v10: d081bd6774793057d23d5e7942dbc6dbd1c20bd3 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v10/index.html

[-- Attachment #2: Type: text/html, Size: 30965 bytes --]

✗ i915.CI.BAT: failure for drm/i915/display: All patches to make PREEMPT_RT work on i915 + xe. (rev11)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 15195 bytes --]

== Series Details ==

Series: drm/i915/display: All patches to make PREEMPT_RT work on i915 + xe. (rev11)
URL   : https://patchwork.freedesktop.org/series/159035/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_17867 -> Patchwork_159035v11
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_159035v11 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_159035v11, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/index.html

Participating hosts (42 -> 39)
------------------------------

  Additional (1): fi-pnv-d510 
  Missing    (4): bat-rplp-1 bat-dg2-13 fi-cfl-8109u fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_159035v11:

### IGT changes ###

#### Possible regressions ####

  * igt@dmabuf@all-tests:
    - fi-ilk-650:         [PASS][1] -> [ABORT][2] +1 other test abort
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/fi-ilk-650/igt@dmabuf@all-tests.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/fi-ilk-650/igt@dmabuf@all-tests.html

  * igt@gem_render_tiled_blits@basic:
    - fi-bsw-n3050:       [PASS][3] -> [ABORT][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/fi-bsw-n3050/igt@gem_render_tiled_blits@basic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/fi-bsw-n3050/igt@gem_render_tiled_blits@basic.html

  * igt@i915_selftest@live:
    - fi-hsw-4770:        [PASS][5] -> [ABORT][6] +1 other test abort
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/fi-hsw-4770/igt@i915_selftest@live.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/fi-hsw-4770/igt@i915_selftest@live.html
    - fi-ivb-3770:        [PASS][7] -> [ABORT][8] +1 other test abort
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/fi-ivb-3770/igt@i915_selftest@live.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/fi-ivb-3770/igt@i915_selftest@live.html
    - bat-mtlp-8:         [PASS][9] -> [ABORT][10] +1 other test abort
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-mtlp-8/igt@i915_selftest@live.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-mtlp-8/igt@i915_selftest@live.html
    - bat-dg2-8:          [PASS][11] -> [ABORT][12] +1 other test abort
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-dg2-8/igt@i915_selftest@live.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-dg2-8/igt@i915_selftest@live.html
    - bat-adls-6:         [PASS][13] -> [ABORT][14] +1 other test abort
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-adls-6/igt@i915_selftest@live.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-adls-6/igt@i915_selftest@live.html
    - bat-jsl-1:          [PASS][15] -> [ABORT][16] +1 other test abort
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-jsl-1/igt@i915_selftest@live.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-jsl-1/igt@i915_selftest@live.html
    - bat-arlh-3:         [PASS][17] -> [ABORT][18] +1 other test abort
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-arlh-3/igt@i915_selftest@live.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-arlh-3/igt@i915_selftest@live.html
    - bat-dg1-7:          [PASS][19] -> [ABORT][20] +1 other test abort
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-dg1-7/igt@i915_selftest@live.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-dg1-7/igt@i915_selftest@live.html
    - fi-glk-j4005:       [PASS][21] -> [ABORT][22] +1 other test abort
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/fi-glk-j4005/igt@i915_selftest@live.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/fi-glk-j4005/igt@i915_selftest@live.html
    - bat-adlp-9:         [PASS][23] -> [ABORT][24] +1 other test abort
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-adlp-9/igt@i915_selftest@live.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-adlp-9/igt@i915_selftest@live.html
    - bat-rpls-4:         [PASS][25] -> [ABORT][26] +1 other test abort
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-rpls-4/igt@i915_selftest@live.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-rpls-4/igt@i915_selftest@live.html
    - fi-kbl-7567u:       [PASS][27] -> [ABORT][28] +1 other test abort
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/fi-kbl-7567u/igt@i915_selftest@live.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/fi-kbl-7567u/igt@i915_selftest@live.html
    - bat-twl-1:          [PASS][29] -> [ABORT][30] +1 other test abort
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-twl-1/igt@i915_selftest@live.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-twl-1/igt@i915_selftest@live.html
    - bat-apl-1:          [PASS][31] -> [ABORT][32] +1 other test abort
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-apl-1/igt@i915_selftest@live.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-apl-1/igt@i915_selftest@live.html
    - bat-arls-5:         [PASS][33] -> [ABORT][34] +1 other test abort
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-arls-5/igt@i915_selftest@live.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-arls-5/igt@i915_selftest@live.html
    - bat-arlh-2:         [PASS][35] -> [ABORT][36] +1 other test abort
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-arlh-2/igt@i915_selftest@live.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-arlh-2/igt@i915_selftest@live.html
    - fi-rkl-11600:       [PASS][37] -> [ABORT][38] +1 other test abort
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/fi-rkl-11600/igt@i915_selftest@live.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/fi-rkl-11600/igt@i915_selftest@live.html
    - fi-cfl-guc:         [PASS][39] -> [ABORT][40] +1 other test abort
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/fi-cfl-guc/igt@i915_selftest@live.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/fi-cfl-guc/igt@i915_selftest@live.html
    - fi-kbl-x1275:       [PASS][41] -> [ABORT][42] +1 other test abort
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/fi-kbl-x1275/igt@i915_selftest@live.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/fi-kbl-x1275/igt@i915_selftest@live.html
    - bat-adlp-11:        [PASS][43] -> [ABORT][44] +1 other test abort
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-adlp-11/igt@i915_selftest@live.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-adlp-11/igt@i915_selftest@live.html
    - fi-kbl-8809g:       [PASS][45] -> [ABORT][46] +1 other test abort
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/fi-kbl-8809g/igt@i915_selftest@live.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/fi-kbl-8809g/igt@i915_selftest@live.html
    - bat-dg1-6:          [PASS][47] -> [ABORT][48] +1 other test abort
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-dg1-6/igt@i915_selftest@live.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-dg1-6/igt@i915_selftest@live.html
    - fi-tgl-1115g4:      [PASS][49] -> [ABORT][50] +1 other test abort
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/fi-tgl-1115g4/igt@i915_selftest@live.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/fi-tgl-1115g4/igt@i915_selftest@live.html
    - bat-adlp-6:         [PASS][51] -> [ABORT][52] +1 other test abort
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-adlp-6/igt@i915_selftest@live.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-adlp-6/igt@i915_selftest@live.html
    - fi-skl-6600u:       [PASS][53] -> [ABORT][54] +1 other test abort
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/fi-skl-6600u/igt@i915_selftest@live.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/fi-skl-6600u/igt@i915_selftest@live.html

  * igt@i915_selftest@live@migrate:
    - bat-apl-1:          [PASS][55] -> [DMESG-FAIL][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-apl-1/igt@i915_selftest@live@migrate.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-apl-1/igt@i915_selftest@live@migrate.html
    - fi-bsw-nick:        [PASS][57] -> [DMESG-FAIL][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/fi-bsw-nick/igt@i915_selftest@live@migrate.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/fi-bsw-nick/igt@i915_selftest@live@migrate.html

  * igt@i915_selftest@live@reset:
    - bat-twl-2:          [PASS][59] -> [ABORT][60] +1 other test abort
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-twl-2/igt@i915_selftest@live@reset.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-twl-2/igt@i915_selftest@live@reset.html
    - fi-cfl-8700k:       [PASS][61] -> [ABORT][62] +1 other test abort
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/fi-cfl-8700k/igt@i915_selftest@live@reset.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/fi-cfl-8700k/igt@i915_selftest@live@reset.html
    - bat-dg2-14:         [PASS][63] -> [ABORT][64] +1 other test abort
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-dg2-14/igt@i915_selftest@live@reset.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-dg2-14/igt@i915_selftest@live@reset.html
    - fi-bsw-nick:        [PASS][65] -> [ABORT][66] +1 other test abort
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/fi-bsw-nick/igt@i915_selftest@live@reset.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/fi-bsw-nick/igt@i915_selftest@live@reset.html
    - bat-kbl-2:          [PASS][67] -> [ABORT][68] +1 other test abort
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-kbl-2/igt@i915_selftest@live@reset.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-kbl-2/igt@i915_selftest@live@reset.html
    - bat-atsm-1:         [PASS][69] -> [ABORT][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-atsm-1/igt@i915_selftest@live@reset.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-atsm-1/igt@i915_selftest@live@reset.html
    - bat-mtlp-9:         [PASS][71] -> [ABORT][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-mtlp-9/igt@i915_selftest@live@reset.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-mtlp-9/igt@i915_selftest@live@reset.html
    - bat-arls-6:         [PASS][73] -> [ABORT][74] +1 other test abort
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-arls-6/igt@i915_selftest@live@reset.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-arls-6/igt@i915_selftest@live@reset.html
    - bat-dg2-9:          [PASS][75] -> [ABORT][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-dg2-9/igt@i915_selftest@live@reset.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-dg2-9/igt@i915_selftest@live@reset.html

  
#### Warnings ####

  * igt@i915_selftest@live:
    - bat-dg2-9:          [DMESG-FAIL][77] ([i915#12061]) -> [ABORT][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-dg2-9/igt@i915_selftest@live.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-dg2-9/igt@i915_selftest@live.html
    - bat-atsm-1:         [DMESG-FAIL][79] ([i915#12061] / [i915#13929]) -> [ABORT][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-atsm-1/igt@i915_selftest@live.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-atsm-1/igt@i915_selftest@live.html
    - bat-mtlp-9:         [DMESG-FAIL][81] ([i915#12061]) -> [ABORT][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-mtlp-9/igt@i915_selftest@live.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-mtlp-9/igt@i915_selftest@live.html

  
Known issues
------------

  Here are the changes found in Patchwork_159035v11 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live:
    - bat-jsl-5:          [PASS][83] -> [ABORT][84] ([i915#15603]) +1 other test abort
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-jsl-5/igt@i915_selftest@live.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-jsl-5/igt@i915_selftest@live.html

  * igt@kms_psr@psr-primary-mmap-gtt:
    - fi-pnv-d510:        NOTRUN -> [SKIP][85] +35 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/fi-pnv-d510/igt@kms_psr@psr-primary-mmap-gtt.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-9:          [DMESG-FAIL][86] ([i915#12061]) -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-dg2-9/igt@i915_selftest@live@workarounds.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-dg2-9/igt@i915_selftest@live@workarounds.html
    - bat-mtlp-9:         [DMESG-FAIL][88] ([i915#12061]) -> [PASS][89]
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17867/bat-mtlp-9/igt@i915_selftest@live@workarounds.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/bat-mtlp-9/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#13929]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13929
  [i915#15603]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15603


Build changes
-------------

  * Linux: CI_DRM_17867 -> Patchwork_159035v11

  CI-20190529: 20190529
  CI_DRM_17867: ad2a046603cba140214aed34015ed5027441e85a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8709: 16ce286cac6acc9669a1c758572ae9fceb483c46 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_159035v11: ad2a046603cba140214aed34015ed5027441e85a @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_159035v11/index.html

[-- Attachment #2: Type: text/html, Size: 16479 bytes --]