* [PATCH 0/2] Update the PHY timeouts
@ 2026-02-12 4:14 Arun R Murthy
2026-02-12 4:14 ` [PATCH 1/2] drm/i915/display/cx0_phy_regs: Include Soc and os turnaround time Arun R Murthy
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Arun R Murthy @ 2026-02-12 4:14 UTC (permalink / raw)
To: Jani Nikula, uma.shankar, suraj.kandpal, ankit.k.nautiyal
Cc: intel-gfx, intel-xe, Arun R Murthy
The timeouts mentioned in the spec is the recommendation from the PHY
and doesnt include the turnaround time of SoC and the OS. So ensure that
sufficient overhead is added for SoC and OS along with the PHY
recommended timeouts.
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
Arun R Murthy (2):
drm/i915/display/cx0_phy_regs: Include Soc and os turnaround time
drm/i915/display/lt_phy_regs: Add SoC/OS turnaround time
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++--
drivers/gpu/drm/i915/display/intel_lt_phy_regs.h | 8 ++++----
2 files changed, 6 insertions(+), 6 deletions(-)
---
base-commit: b4bfe7d753afaf6ea4950111a309a4e2ef5aef68
change-id: 20260212-timeout-06cb232f71af
Best regards,
--
Arun R Murthy <arun.r.murthy@intel.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] drm/i915/display/cx0_phy_regs: Include Soc and os turnaround time
2026-02-12 4:14 [PATCH 0/2] Update the PHY timeouts Arun R Murthy
@ 2026-02-12 4:14 ` Arun R Murthy
2026-02-12 4:32 ` Kandpal, Suraj
2026-02-12 4:14 ` [PATCH 2/2] drm/i915/display/lt_phy_regs: Add SoC/OS " Arun R Murthy
2026-02-12 5:14 ` ✓ i915.CI.BAT: success for Update the PHY timeouts Patchwork
2 siblings, 1 reply; 6+ messages in thread
From: Arun R Murthy @ 2026-02-12 4:14 UTC (permalink / raw)
To: Jani Nikula, uma.shankar, suraj.kandpal, ankit.k.nautiyal
Cc: intel-gfx, intel-xe, Arun R Murthy
The port refclk enable timeout and the soc ready timeout value mentioned
in the spec is the PHY timings and doesn't include the turnaround time
from the SoC or OS. So add an overhead timeout value on top of the
recommended timeouts from the PHY spec.
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index 658890f7351530e5686c23e067deb359b3283d59..152a4e751bdcf216a95714a2bd2d6612cbbd4698 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -78,10 +78,10 @@
#define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200
#define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20
#define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100
-#define XELPDP_PORT_RESET_START_TIMEOUT_US 5
+#define XELPDP_PORT_RESET_START_TIMEOUT_US 10
#define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS 2
#define XELPDP_PORT_RESET_END_TIMEOUT_MS 15
-#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 1
+#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 10
#define _XELPDP_PORT_BUF_CTL1_LN0_A 0x64004
#define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/i915/display/lt_phy_regs: Add SoC/OS turnaround time
2026-02-12 4:14 [PATCH 0/2] Update the PHY timeouts Arun R Murthy
2026-02-12 4:14 ` [PATCH 1/2] drm/i915/display/cx0_phy_regs: Include Soc and os turnaround time Arun R Murthy
@ 2026-02-12 4:14 ` Arun R Murthy
2026-02-12 4:34 ` Kandpal, Suraj
2026-02-12 5:14 ` ✓ i915.CI.BAT: success for Update the PHY timeouts Patchwork
2 siblings, 1 reply; 6+ messages in thread
From: Arun R Murthy @ 2026-02-12 4:14 UTC (permalink / raw)
To: Jani Nikula, uma.shankar, suraj.kandpal, ankit.k.nautiyal
Cc: intel-gfx, intel-xe, Arun R Murthy
On top the timeouts mentioned in the spec which includes only the PHY
timeouts include the SoC and the OS turnaround time.
Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
---
drivers/gpu/drm/i915/display/intel_lt_phy_regs.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
index 37e46fb9abde4156ebd7ad1eb6cbbc12e7026b23..ff6d7829dbb9c50b2001d079b435b894faf9659e 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
@@ -6,12 +6,12 @@
#ifndef __INTEL_LT_PHY_REGS_H__
#define __INTEL_LT_PHY_REGS_H__
-#define XE3PLPD_MSGBUS_TIMEOUT_FAST_US 500
+#define XE3PLPD_MSGBUS_TIMEOUT_FAST_US 500
#define XE3PLPD_MACCLK_TURNON_LATENCY_MS 2
-#define XE3PLPD_MACCLK_TURNOFF_LATENCY_US 1
+#define XE3PLPD_MACCLK_TURNOFF_LATENCY_US 10
#define XE3PLPD_RATE_CALIB_DONE_LATENCY_MS 1
-#define XE3PLPD_RESET_START_LATENCY_US 10
-#define XE3PLPD_PWRDN_TO_RDY_LATENCY_US 4
+#define XE3PLPD_RESET_START_LATENCY_US 10
+#define XE3PLPD_PWRDN_TO_RDY_LATENCY_US 10
#define XE3PLPD_RESET_END_LATENCY_MS 2
/* LT Phy MAC Register */
--
2.25.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* RE: [PATCH 1/2] drm/i915/display/cx0_phy_regs: Include Soc and os turnaround time
2026-02-12 4:14 ` [PATCH 1/2] drm/i915/display/cx0_phy_regs: Include Soc and os turnaround time Arun R Murthy
@ 2026-02-12 4:32 ` Kandpal, Suraj
0 siblings, 0 replies; 6+ messages in thread
From: Kandpal, Suraj @ 2026-02-12 4:32 UTC (permalink / raw)
To: Murthy, Arun R, Jani Nikula, Shankar, Uma, Nautiyal, Ankit K
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
> Subject: [PATCH 1/2] drm/i915/display/cx0_phy_regs: Include Soc and os
* SoC & * OS
> turnaround time
Nit: This can be just drm/i915/cx0:
You can keep cx0_phy_regs if you like but you need to drop the display
>
> The port refclk enable timeout and the soc ready timeout value mentioned in
* SoC
> the spec is the PHY timings and doesn't include the turnaround time from the
> SoC or OS. So add an overhead timeout value on top of the recommended
> timeouts from the PHY spec.
>
We can perhaps mention something like the timeout is increased based on stress testing
Where we observed the move PHY stability
With the above fixed,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> index
> 658890f7351530e5686c23e067deb359b3283d59..152a4e751bdcf216a95714
> a2bd2d6612cbbd4698 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
> @@ -78,10 +78,10 @@
> #define XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US 3200
> #define XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US 20
> #define XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US 100
> -#define XELPDP_PORT_RESET_START_TIMEOUT_US 5
> +#define XELPDP_PORT_RESET_START_TIMEOUT_US 10
> #define XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_MS
> 2
> #define XELPDP_PORT_RESET_END_TIMEOUT_MS 15
> -#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 1
> +#define XELPDP_REFCLK_ENABLE_TIMEOUT_US 10
>
> #define _XELPDP_PORT_BUF_CTL1_LN0_A 0x64004
> #define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104
>
> --
> 2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH 2/2] drm/i915/display/lt_phy_regs: Add SoC/OS turnaround time
2026-02-12 4:14 ` [PATCH 2/2] drm/i915/display/lt_phy_regs: Add SoC/OS " Arun R Murthy
@ 2026-02-12 4:34 ` Kandpal, Suraj
0 siblings, 0 replies; 6+ messages in thread
From: Kandpal, Suraj @ 2026-02-12 4:34 UTC (permalink / raw)
To: Murthy, Arun R, Jani Nikula, Shankar, Uma, Nautiyal, Ankit K
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
Kahola, Mika
> Subject: [PATCH 2/2] drm/i915/display/lt_phy_regs: Add SoC/OS turnaround
> time
Same comment as the first patch drop display, make it ltphy or keep it lt_phy_regs that
Is okay either way
>
> On top the timeouts mentioned in the spec which includes only the PHY
> timeouts include the SoC and the OS turnaround time.
Same here you can mention based on what we increased the time.
With these fixed LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
>
> Signed-off-by: Arun R Murthy <arun.r.murthy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_lt_phy_regs.h | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> index
> 37e46fb9abde4156ebd7ad1eb6cbbc12e7026b23..ff6d7829dbb9c50b2001d07
> 9b435b894faf9659e 100644
> --- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
> @@ -6,12 +6,12 @@
> #ifndef __INTEL_LT_PHY_REGS_H__
> #define __INTEL_LT_PHY_REGS_H__
>
> -#define XE3PLPD_MSGBUS_TIMEOUT_FAST_US 500
> +#define XE3PLPD_MSGBUS_TIMEOUT_FAST_US 500
> #define XE3PLPD_MACCLK_TURNON_LATENCY_MS 2
> -#define XE3PLPD_MACCLK_TURNOFF_LATENCY_US 1
> +#define XE3PLPD_MACCLK_TURNOFF_LATENCY_US 10
> #define XE3PLPD_RATE_CALIB_DONE_LATENCY_MS 1
> -#define XE3PLPD_RESET_START_LATENCY_US 10
> -#define XE3PLPD_PWRDN_TO_RDY_LATENCY_US 4
> +#define XE3PLPD_RESET_START_LATENCY_US 10
> +#define XE3PLPD_PWRDN_TO_RDY_LATENCY_US 10
> #define XE3PLPD_RESET_END_LATENCY_MS 2
>
> /* LT Phy MAC Register */
>
> --
> 2.25.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* ✓ i915.CI.BAT: success for Update the PHY timeouts
2026-02-12 4:14 [PATCH 0/2] Update the PHY timeouts Arun R Murthy
2026-02-12 4:14 ` [PATCH 1/2] drm/i915/display/cx0_phy_regs: Include Soc and os turnaround time Arun R Murthy
2026-02-12 4:14 ` [PATCH 2/2] drm/i915/display/lt_phy_regs: Add SoC/OS " Arun R Murthy
@ 2026-02-12 5:14 ` Patchwork
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2026-02-12 5:14 UTC (permalink / raw)
To: Arun R Murthy; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 2094 bytes --]
== Series Details ==
Series: Update the PHY timeouts
URL : https://patchwork.freedesktop.org/series/161527/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_17977 -> Patchwork_161527v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161527v1/index.html
Participating hosts (43 -> 41)
------------------------------
Missing (2): bat-dg2-13 fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_161527v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@client:
- fi-kbl-7567u: [PASS][1] -> [DMESG-WARN][2] ([i915#13735]) +13 other tests dmesg-warn
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17977/fi-kbl-7567u/igt@i915_selftest@live@client.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161527v1/fi-kbl-7567u/igt@i915_selftest@live@client.html
#### Possible fixes ####
* igt@i915_selftest@live@workarounds:
- bat-dg2-9: [DMESG-FAIL][3] ([i915#12061]) -> [PASS][4] +1 other test pass
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_17977/bat-dg2-9/igt@i915_selftest@live@workarounds.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161527v1/bat-dg2-9/igt@i915_selftest@live@workarounds.html
[i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
[i915#13735]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13735
Build changes
-------------
* Linux: CI_DRM_17977 -> Patchwork_161527v1
CI-20190529: 20190529
CI_DRM_17977: b4bfe7d753afaf6ea4950111a309a4e2ef5aef68 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_8751: af788251f1ef729d17c802aec2c4547b52059e58 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_161527v1: b4bfe7d753afaf6ea4950111a309a4e2ef5aef68 @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161527v1/index.html
[-- Attachment #2: Type: text/html, Size: 2704 bytes --]
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2026-02-12 4:14 [PATCH 0/2] Update the PHY timeouts Arun R Murthy
2026-02-12 4:14 ` [PATCH 1/2] drm/i915/display/cx0_phy_regs: Include Soc and os turnaround time Arun R Murthy
2026-02-12 4:32 ` Kandpal, Suraj
2026-02-12 4:14 ` [PATCH 2/2] drm/i915/display/lt_phy_regs: Add SoC/OS " Arun R Murthy
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2026-02-12 5:14 ` ✓ i915.CI.BAT: success for Update the PHY timeouts Patchwork
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