[PATCH] drm/i915/display: Enable VRR/HDR over MST

[PATCH] drm/i915/display: Enable VRR/HDR over MST

[Xiao Lu]

VRR over MST:
- Remove the hard MST block in intel_vrr_is_capable(); check the
  downstream port's MSA timing par ignore capability via REMOTE_DPCD_READ
  and cache it in connector->dp.mst_msa_timing_par_ignore to avoid hot
  path sideband round-trips.
- Attach vrr_capable property to MST connectors and update it after EDID
  read; enable AS-SDP computation and transmission for MST streams.

HDR metadata over MST:
- Add VSC SDP, HDR metadata infoframe SDP and AS-SDP computation to
  mst_stream_compute_config() and enable their transmission in
  mst_stream_enable() and intel_ddi_update_pipe().
- Lift the hard 8bpc pipe_bpp cap and use the bpp capability from sink EDID
  for MST streams to allow 10bpc, relying on
  intel_dp_mst_atomic_check_link()'s BW retry loop to fall back if the
  link cannot fit it.
Signed-off-by: Xiao Lu <xiaolu.xie@intel.com>
---
 drivers/gpu/drm/display/drm_dp_mst_topology.c |  2 +
 drivers/gpu/drm/i915/display/intel_ddi.c      |  3 +
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 23 ++++---
 drivers/gpu/drm/i915/display/intel_dp.h       |  8 +++
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 65 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.c      | 23 ++++++-
 7 files changed, 113 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 7ce9e212770a..174fa62cb0dc 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -2164,6 +2164,7 @@ ssize_t drm_dp_mst_dpcd_read(struct drm_dp_aux *aux,
 	return drm_dp_send_dpcd_read(port->mgr, port,
 				     offset, size, buffer);
 }
+EXPORT_SYMBOL(drm_dp_mst_dpcd_read);
 
 /**
  * drm_dp_mst_dpcd_write() - write a series of bytes to the DPCD via sideband
@@ -2187,6 +2188,7 @@ ssize_t drm_dp_mst_dpcd_write(struct drm_dp_aux *aux,
 	return drm_dp_send_dpcd_write(port->mgr, port,
 				      offset, size, buffer);
 }
+EXPORT_SYMBOL(drm_dp_mst_dpcd_write);
 
 static int drm_dp_check_mstb_guid(struct drm_dp_mst_branch *mstb, guid_t *guid)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 2b7eb010511b..09e8a7335a05 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3649,6 +3649,9 @@ void intel_ddi_update_pipe(struct intel_atomic_state *state,
 		intel_ddi_update_pipe_dp(state, encoder, crtc_state,
 					 conn_state);
 
+	if (intel_encoder_is_mst(encoder))
+		intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
+
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		intel_ddi_update_pipe_hdmi(encoder, crtc_state,
 					   conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index adde53dc9dce..246a2c05efc2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -564,6 +564,7 @@ struct intel_connector {
 		u8 dsc_hblank_expansion_quirk:1;
 		u8 dsc_throughput_quirk:1;
 		u8 dsc_decompression_enabled:1;
+		u8 mst_msa_timing_par_ignore:1; /* cached from MST virtual DPCD 0x007 */
 
 		struct {
 			struct {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 61ae83857cd6..52d5c09a608c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2682,15 +2682,18 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 
 	limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
 	if (is_mst) {
+		struct intel_connector *mst_connector =
+			to_intel_connector(conn_state->connector);
+		int sink_bpc = mst_connector->base.display_info.bpc ?: 8;
+
 		/*
-		 * FIXME: If all the streams can't fit into the link with their
-		 * current pipe_bpp we should reduce pipe_bpp across the board
-		 * until things start to fit. Until then we limit to <= 8bpc
-		 * since that's what was hardcoded for all MST streams
-		 * previously. This hack should be removed once we have the
-		 * proper retry logic in place.
+		 * For MST streams, use the sink's EDID-reported color depth
+		 * as the max bpp, rather than the pipe_bpp from a previous
+		 * modeset (which may be stale) or a hardcoded 8bpc cap.
+		 * The BW retry loop in intel_dp_mst_atomic_check_link() will
+		 * reduce bpp if the aggregate link bandwidth is insufficient.
 		 */
-		limits->pipe.max_bpp = min(crtc_state->max_pipe_bpp, 24);
+		limits->pipe.max_bpp = sink_bpc * 3;
 	} else {
 		limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
 							respect_downstream_limits);
@@ -3105,7 +3108,7 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
 	return intel_vrr_possible(crtc_state);
 }
 
-static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
+void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 				    struct intel_crtc_state *crtc_state)
 {
 	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
@@ -3155,7 +3158,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 		as_sdp->coasting_vtotal = crtc_state->vrr.vmax;
 }
 
-static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
+void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
 				     struct intel_crtc_state *crtc_state,
 				     const struct drm_connector_state *conn_state)
 {
@@ -3216,7 +3219,7 @@ intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state)
 	return hdr_metadata->hdmi_metadata_type1.eotf == HDMI_EOTF_SMPTE_ST2084;
 }
 
-static void
+void
 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
 					    struct intel_crtc_state *crtc_state,
 					    const struct drm_connector_state *conn_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 0ec519fa1236..0b01634d907c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -77,6 +77,8 @@ int intel_dp_compute_config(struct intel_atomic_state *state,
 			    struct intel_encoder *encoder,
 			    struct intel_crtc_state *pipe_config,
 			    struct drm_connector_state *conn_state);
+void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
+				    struct intel_crtc_state *crtc_state);
 bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state,
 			      bool dsc_enabled_on_crtc);
 void intel_dp_dsc_reset_config(struct intel_crtc_state *crtc_state);
@@ -130,6 +132,12 @@ bool intel_dp_joiner_needs_dsc(struct intel_display *display,
 bool intel_dp_has_joiner(struct intel_dp *intel_dp);
 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state,
 			    const struct drm_connector_state *conn_state);
+void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
+			      struct intel_crtc_state *crtc_state,
+			      const struct drm_connector_state *conn_state);
+void intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
+					    struct intel_crtc_state *crtc_state,
+					    const struct drm_connector_state *conn_state);
 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
 			     const struct intel_crtc_state *crtc_state,
 			     const struct drm_connector_state *conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 7cbef16ab38b..173e91482f0a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -793,6 +793,9 @@ static int mst_stream_compute_config(struct intel_atomic_state *state,
 			bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
 
 	intel_vrr_compute_config(pipe_config, conn_state);
+	intel_dp_compute_as_sdp(intel_dp, pipe_config);
+	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
+	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
 
 	intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
 
@@ -1157,6 +1160,24 @@ static void mst_stream_post_disable(struct intel_atomic_state *state,
 	 * Power down mst path before disabling the port, otherwise we end
 	 * up getting interrupts from the sink upon detecting link loss.
 	 */
+	if (intel_vrr_is_capable(connector)) {
+		u8 val;
+		ssize_t ret;
+
+		ret = drm_dp_mst_dpcd_read(&connector->mst.port->aux,
+					   DP_DOWNSPREAD_CTRL, &val, 1);
+		if (ret < 0) {
+			drm_dbg_kms(display->drm,
+				    "[CONNECTOR:%d:%s] Failed to read DP_DOWNSPREAD_CTRL: %zd\n",
+				    connector->base.base.id,
+				    connector->base.name, ret);
+		} else {
+			val &= ~DP_MSA_TIMING_PAR_IGNORE_EN;
+			drm_dp_mst_dpcd_write(&connector->mst.port->aux,
+					      DP_DOWNSPREAD_CTRL, &val, 1);
+		}
+	}
+
 	drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port,
 				     false);
 
@@ -1274,6 +1295,24 @@ static void mst_stream_pre_enable(struct intel_atomic_state *state,
 
 	drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port, true);
 
+	if (intel_vrr_is_capable(connector)) {
+		u8 val;
+		ssize_t ret;
+
+		ret = drm_dp_mst_dpcd_read(&connector->mst.port->aux,
+					   DP_DOWNSPREAD_CTRL, &val, 1);
+		if (ret < 0) {
+			drm_dbg_kms(display->drm,
+				    "[CONNECTOR:%d:%s] Failed to read DP_DOWNSPREAD_CTRL: %zd\n",
+				    connector->base.base.id,
+				    connector->base.name, ret);
+		} else {
+			val |= DP_MSA_TIMING_PAR_IGNORE_EN;
+			drm_dp_mst_dpcd_write(&connector->mst.port->aux,
+					      DP_DOWNSPREAD_CTRL, &val, 1);
+		}
+	}
+
 	intel_dp_sink_enable_decompression(state, connector, pipe_config);
 
 	if (first_mst_stream) {
@@ -1397,6 +1436,8 @@ static void mst_stream_enable(struct intel_atomic_state *state,
 
 	intel_enable_transcoder(pipe_config);
 
+	intel_dp_set_infoframes(encoder, true, pipe_config, conn_state);
+
 	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, pipe_config) {
 		const struct intel_crtc_state *pipe_crtc_state =
 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
@@ -1451,6 +1492,15 @@ static int mst_connector_get_ddc_modes(struct drm_connector *_connector)
 
 	ret = intel_connector_update_modes(&connector->base, drm_edid);
 
+	if (HAS_VRR(display)) {
+		bool vrr_capable = intel_vrr_is_capable(connector);
+
+		drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
+			    connector->base.base.id, connector->base.name,
+			    str_yes_no(vrr_capable));
+		drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
+	}
+
 	drm_edid_free(drm_edid);
 
 	if (intel_dp_tunnel_uhbr_lanes_wa_setup(intel_dp)) {
@@ -1735,6 +1785,10 @@ static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,
 
 	intel_attach_force_audio_property(&connector->base);
 	intel_attach_broadcast_rgb_property(&connector->base);
+	intel_attach_dp_colorspace_property(&connector->base);
+
+	if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
+		drm_connector_attach_hdr_output_metadata_property(&connector->base);
 
 	/*
 	 * Reuse the prop from the SST connector because we're
@@ -1745,6 +1799,14 @@ static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,
 	if (connector->base.max_bpc_property)
 		drm_connector_attach_max_bpc_property(&connector->base, 6, 12);
 
+	/*
+	 * Reuse the vrr_capable prop from the eDP connector (which is always
+	 * initialized during driver load before device registration), because
+	 * we're not allowed to create new props after device registration.
+	 */
+	if (HAS_VRR(display))
+		drm_connector_attach_vrr_capable_property(&connector->base);
+
 	return drm_connector_set_path_property(&connector->base, pathprop);
 }
 
@@ -1761,6 +1823,9 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
 	if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd_caps) < 0)
 		return;
 
+	connector->dp.mst_msa_timing_par_ignore =
+		drm_dp_sink_can_do_video_without_timing_msa(dpcd_caps);
+
 	if (drm_dp_read_desc(connector->dp.dsc_decompression_aux, &desc,
 			     drm_dp_is_branch(dpcd_caps)) < 0)
 		return;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index bffbdee76ee1..d7d4a23cdf74 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -54,8 +54,27 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
 			return false;
 		fallthrough;
 	case DRM_MODE_CONNECTOR_DisplayPort:
-		if (connector->mst.dp)
-			return false;
+		if (connector->mst.dp) {
+			u8 dpcd[DP_RECEIVER_CAP_SIZE];
+
+			/*
+			 * Use cached MSA timing ignore capability from the DFP
+			 * sink's virtual DPCD, set during connector init.
+			 */
+			if (!connector->dp.mst_msa_timing_par_ignore)
+				return false;
+
+			/*
+			 * Also verify live via LCT=2 REMOTE_DPCD_READ to the
+			 * DFP sink's actual DPCD 0x007.
+			 */
+			if (drm_dp_read_dpcd_caps(&connector->mst.port->aux, dpcd) < 0)
+				return false;
+			if (!drm_dp_sink_can_do_video_without_timing_msa(dpcd))
+				return false;
+
+			break;
+		}
 		intel_dp = intel_attached_dp(connector);
 		/*
 		 * Among non-MST DP branch devices, only an HDMI 2.1 sink connected
-- 
2.43.0

✗ Fi.CI.BUILD: failure for drm/i915/display: Enable VRR/HDR over MST

[Patchwork]

== Series Details ==

Series: drm/i915/display: Enable VRR/HDR over MST
URL   : https://patchwork.freedesktop.org/series/173155/
State : failure

== Summary ==

Error: patch https://patchwork.freedesktop.org/api/1.0/series/173155/revisions/1/mbox/ not applied
Applying: drm/i915/display: Enable VRR/HDR over MST
error: sha1 information is lacking or useless (drivers/gpu/drm/i915/display/intel_display_types.h).
error: could not build fake ancestor
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 drm/i915/display: Enable VRR/HDR over MST
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Build failed, no error log produced

[PATCH v2] drm/i915/display: Enable VRR/HDR over MST

[Xiao Lu]

VRR over MST:
- Remove the hard MST block in intel_vrr_is_capable(); check the
  downstream port's MSA timing par ignore capability via REMOTE_DPCD_READ
  and cache it in connector->dp.mst_msa_timing_par_ignore to avoid hot
  path sideband round-trips.
- Attach vrr_capable property to MST connectors and update it after EDID
  read; enable AS-SDP computation and transmission for MST streams.

HDR metadata over MST:
- Add VSC SDP, HDR metadata infoframe SDP and AS-SDP computation to
  mst_stream_compute_config() and enable their transmission in
  mst_stream_enable() and intel_ddi_update_pipe().
- Lift the hard 8bpc pipe_bpp cap and use the bpp capability from sink EDID
  for MST streams to allow 10bpc, relying on
  intel_dp_mst_atomic_check_link()'s BW retry loop to fall back if the
  link cannot fit it.
Signed-off-by: Xiao Lu <xiaolu.xie@intel.com>
---
 drivers/gpu/drm/display/drm_dp_mst_topology.c |  2 +
 drivers/gpu/drm/i915/display/intel_ddi.c      |  3 +
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 23 ++++---
 drivers/gpu/drm/i915/display/intel_dp.h       |  8 +++
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 65 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.c      | 23 ++++++-
 7 files changed, 113 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 7ce9e212770a..174fa62cb0dc 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -2164,6 +2164,7 @@ ssize_t drm_dp_mst_dpcd_read(struct drm_dp_aux *aux,
 	return drm_dp_send_dpcd_read(port->mgr, port,
 				     offset, size, buffer);
 }
+EXPORT_SYMBOL(drm_dp_mst_dpcd_read);
 
 /**
  * drm_dp_mst_dpcd_write() - write a series of bytes to the DPCD via sideband
@@ -2187,6 +2188,7 @@ ssize_t drm_dp_mst_dpcd_write(struct drm_dp_aux *aux,
 	return drm_dp_send_dpcd_write(port->mgr, port,
 				      offset, size, buffer);
 }
+EXPORT_SYMBOL(drm_dp_mst_dpcd_write);
 
 static int drm_dp_check_mstb_guid(struct drm_dp_mst_branch *mstb, guid_t *guid)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b8985e1e0a81..f345d9a2154d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3651,6 +3651,9 @@ void intel_ddi_update_pipe(struct intel_atomic_state *state,
 		intel_ddi_update_pipe_dp(state, encoder, crtc_state,
 					 conn_state);
 
+	if (intel_encoder_is_mst(encoder))
+		intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
+
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		intel_ddi_update_pipe_hdmi(encoder, crtc_state,
 					   conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b7cc361fd955..d09cf18f5376 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -564,6 +564,7 @@ struct intel_connector {
 		u8 dsc_hblank_expansion_quirk:1;
 		u8 dsc_throughput_quirk:1;
 		u8 dsc_decompression_enabled:1;
+		u8 mst_msa_timing_par_ignore:1; /* cached from MST virtual DPCD 0x007 */
 
 		struct {
 			struct {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 113d767e62e9..7efb89f7e5f7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2682,15 +2682,18 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 
 	limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
 	if (is_mst) {
+		struct intel_connector *mst_connector =
+			to_intel_connector(conn_state->connector);
+		int sink_bpc = mst_connector->base.display_info.bpc ?: 8;
+
 		/*
-		 * FIXME: If all the streams can't fit into the link with their
-		 * current pipe_bpp we should reduce pipe_bpp across the board
-		 * until things start to fit. Until then we limit to <= 8bpc
-		 * since that's what was hardcoded for all MST streams
-		 * previously. This hack should be removed once we have the
-		 * proper retry logic in place.
+		 * For MST streams, use the sink's EDID-reported color depth
+		 * as the max bpp, rather than the pipe_bpp from a previous
+		 * modeset (which may be stale) or a hardcoded 8bpc cap.
+		 * The BW retry loop in intel_dp_mst_atomic_check_link() will
+		 * reduce bpp if the aggregate link bandwidth is insufficient.
 		 */
-		limits->pipe.max_bpp = min(crtc_state->max_pipe_bpp, 24);
+		limits->pipe.max_bpp = sink_bpc * 3;
 	} else {
 		limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
 							respect_downstream_limits);
@@ -3119,7 +3122,7 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
 	return intel_vrr_possible(crtc_state);
 }
 
-static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
+void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 				    struct intel_crtc_state *crtc_state)
 {
 	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
@@ -3169,7 +3172,7 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 		as_sdp->coasting_vtotal = crtc_state->vrr.vmax;
 }
 
-static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
+void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
 				     struct intel_crtc_state *crtc_state,
 				     const struct drm_connector_state *conn_state)
 {
@@ -3228,7 +3231,7 @@ intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state)
 	return hdr_metadata->hdmi_metadata_type1.eotf == HDMI_EOTF_SMPTE_ST2084;
 }
 
-static void
+void
 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
 					    struct intel_crtc_state *crtc_state,
 					    const struct drm_connector_state *conn_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 04fae203bb69..ca3ddad6fd9d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -77,6 +77,8 @@ int intel_dp_compute_config(struct intel_atomic_state *state,
 			    struct intel_encoder *encoder,
 			    struct intel_crtc_state *pipe_config,
 			    struct drm_connector_state *conn_state);
+void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
+				    struct intel_crtc_state *crtc_state);
 bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state,
 			      bool dsc_enabled_on_crtc);
 void intel_dp_dsc_reset_config(struct intel_crtc_state *crtc_state);
@@ -130,6 +132,12 @@ bool intel_dp_joiner_needs_dsc(struct intel_display *display,
 bool intel_dp_has_joiner(struct intel_dp *intel_dp);
 bool intel_dp_needs_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
 				    const struct drm_connector_state *conn_state);
+void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
+			      struct intel_crtc_state *crtc_state,
+			      const struct drm_connector_state *conn_state);
+void intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
+					    struct intel_crtc_state *crtc_state,
+					    const struct drm_connector_state *conn_state);
 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
 			     const struct intel_crtc_state *crtc_state,
 			     const struct drm_connector_state *conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 3be1643f8d03..467b072712cb 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -793,6 +793,9 @@ static int mst_stream_compute_config(struct intel_atomic_state *state,
 			bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
 
 	intel_vrr_compute_config(pipe_config, conn_state);
+	intel_dp_compute_as_sdp(intel_dp, pipe_config);
+	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
+	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
 
 	intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
 
@@ -1157,6 +1160,24 @@ static void mst_stream_post_disable(struct intel_atomic_state *state,
 	 * Power down mst path before disabling the port, otherwise we end
 	 * up getting interrupts from the sink upon detecting link loss.
 	 */
+	if (intel_vrr_is_capable(connector)) {
+		u8 val;
+		ssize_t ret;
+
+		ret = drm_dp_mst_dpcd_read(&connector->mst.port->aux,
+					   DP_DOWNSPREAD_CTRL, &val, 1);
+		if (ret < 0) {
+			drm_dbg_kms(display->drm,
+				    "[CONNECTOR:%d:%s] Failed to read DP_DOWNSPREAD_CTRL: %zd\n",
+				    connector->base.base.id,
+				    connector->base.name, ret);
+		} else {
+			val &= ~DP_MSA_TIMING_PAR_IGNORE_EN;
+			drm_dp_mst_dpcd_write(&connector->mst.port->aux,
+					      DP_DOWNSPREAD_CTRL, &val, 1);
+		}
+	}
+
 	drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port,
 				     false);
 
@@ -1274,6 +1295,24 @@ static void mst_stream_pre_enable(struct intel_atomic_state *state,
 
 	drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port, true);
 
+	if (intel_vrr_is_capable(connector)) {
+		u8 val;
+		ssize_t ret;
+
+		ret = drm_dp_mst_dpcd_read(&connector->mst.port->aux,
+					   DP_DOWNSPREAD_CTRL, &val, 1);
+		if (ret < 0) {
+			drm_dbg_kms(display->drm,
+				    "[CONNECTOR:%d:%s] Failed to read DP_DOWNSPREAD_CTRL: %zd\n",
+				    connector->base.base.id,
+				    connector->base.name, ret);
+		} else {
+			val |= DP_MSA_TIMING_PAR_IGNORE_EN;
+			drm_dp_mst_dpcd_write(&connector->mst.port->aux,
+					      DP_DOWNSPREAD_CTRL, &val, 1);
+		}
+	}
+
 	intel_dp_sink_enable_decompression(state, connector, pipe_config);
 
 	if (first_mst_stream) {
@@ -1397,6 +1436,8 @@ static void mst_stream_enable(struct intel_atomic_state *state,
 
 	intel_enable_transcoder(pipe_config);
 
+	intel_dp_set_infoframes(encoder, true, pipe_config, conn_state);
+
 	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, pipe_config) {
 		const struct intel_crtc_state *pipe_crtc_state =
 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
@@ -1451,6 +1492,15 @@ static int mst_connector_get_ddc_modes(struct drm_connector *_connector)
 
 	ret = intel_connector_update_modes(&connector->base, drm_edid);
 
+	if (HAS_VRR(display)) {
+		bool vrr_capable = intel_vrr_is_capable(connector);
+
+		drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
+			    connector->base.base.id, connector->base.name,
+			    str_yes_no(vrr_capable));
+		drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
+	}
+
 	drm_edid_free(drm_edid);
 
 	if (intel_dp_tunnel_uhbr_lanes_wa_setup(intel_dp)) {
@@ -1735,6 +1785,10 @@ static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,
 
 	intel_attach_force_audio_property(&connector->base);
 	intel_attach_broadcast_rgb_property(&connector->base);
+	intel_attach_dp_colorspace_property(&connector->base);
+
+	if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
+		drm_connector_attach_hdr_output_metadata_property(&connector->base);
 
 	/*
 	 * Reuse the prop from the SST connector because we're
@@ -1745,6 +1799,14 @@ static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,
 	if (connector->base.max_bpc_property)
 		drm_connector_attach_max_bpc_property(&connector->base, 6, 12);
 
+	/*
+	 * Reuse the vrr_capable prop from the eDP connector (which is always
+	 * initialized during driver load before device registration), because
+	 * we're not allowed to create new props after device registration.
+	 */
+	if (HAS_VRR(display))
+		drm_connector_attach_vrr_capable_property(&connector->base);
+
 	return drm_connector_set_path_property(&connector->base, pathprop);
 }
 
@@ -1761,6 +1823,9 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
 	if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd_caps) < 0)
 		return;
 
+	connector->dp.mst_msa_timing_par_ignore =
+		drm_dp_sink_can_do_video_without_timing_msa(dpcd_caps);
+
 	if (drm_dp_read_desc(connector->dp.dsc_decompression_aux, &desc,
 			     drm_dp_is_branch(dpcd_caps)) < 0)
 		return;
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 51e4f3309b8b..13cd5701bf2c 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -55,8 +55,27 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
 			return false;
 		fallthrough;
 	case DRM_MODE_CONNECTOR_DisplayPort:
-		if (connector->mst.dp)
-			return false;
+		if (connector->mst.dp) {
+			u8 dpcd[DP_RECEIVER_CAP_SIZE];
+
+			/*
+			 * Use cached MSA timing ignore capability from the DFP
+			 * sink's virtual DPCD, set during connector init.
+			 */
+			if (!connector->dp.mst_msa_timing_par_ignore)
+				return false;
+
+			/*
+			 * Also verify live via LCT=2 REMOTE_DPCD_READ to the
+			 * DFP sink's actual DPCD 0x007.
+			 */
+			if (drm_dp_read_dpcd_caps(&connector->mst.port->aux, dpcd) < 0)
+				return false;
+			if (!drm_dp_sink_can_do_video_without_timing_msa(dpcd))
+				return false;
+
+			break;
+		}
 		intel_dp = intel_attached_dp(connector);
 		/*
 		 * Among non-MST DP branch devices, only an HDMI 2.1 sink connected
-- 
2.43.0

Re: [PATCH v2] drm/i915/display: Enable VRR/HDR over MST

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [High] AS-SDP computation is broken for MST streams because the branch device check unconditionally returns false.
- [High] VRR capability caching is incorrectly tied to DSC support, silently breaking VRR on MST monitors that lack DSC.
- [High] DP_MSA_TIMING_PAR_IGNORE_EN is unconditionally enabled based on capability rather than active VRR state.
- [High] Dynamic creation of `vrr_capable_property` after device registration during MST hotplug triggers a kernel WARN_ON and leaks memory.
--

commit 67043be5215717a8902d6610575b918e36e9945a
Author: Xiao Lu <xiaolu.xie@intel.com>

drm/i915/display: Enable VRR/HDR over MST

This commit introduces VRR and HDR metadata support over MST display streams.
It caches the downstream port's MSA timing par ignore capability and enables
AS-SDP and VSC SDP computation and transmission for MST connectors.

> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 6a869d0f6ffc0..657440e2cb648 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c

[ ... ]

> @@ -793,6 +793,9 @@ static int mst_stream_compute_config(struct intel_atomic_state *state,
>  			bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
>  
>  	intel_vrr_compute_config(pipe_config, conn_state);
> +	intel_dp_compute_as_sdp(intel_dp, pipe_config);

[Severity: High]
Will this AS-SDP computation actually run for MST topologies?

In intel_dp_compute_as_sdp() (which calls intel_dp_needs_as_sdp()), there is
an existing check that unconditionally disables AS-SDP for branch devices:

drivers/gpu/drm/i915/display/intel_dp.c:intel_dp_needs_as_sdp()
    if (drm_dp_is_branch(intel_dp->dpcd))
        return false;

Since the primary DP device in an MST topology is always a branch device
(the MST hub), this check will always return false, silently aborting the
AS-SDP logic you are enabling here.

[ ... ]

> @@ -1274,6 +1295,24 @@ static void mst_stream_pre_enable(struct intel_atomic_state *state,
>  
>  	drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port, true);
>  
> +	if (intel_vrr_is_capable(connector)) {
> +		u8 val;
> +		ssize_t ret;
> +
> +		ret = drm_dp_mst_dpcd_read(&connector->mst.port->aux,
> +					   DP_DOWNSPREAD_CTRL, &val, 1);
> +		if (ret < 0) {
> +			drm_dbg_kms(display->drm,
> +				    "[CONNECTOR:%d:%s] Failed to read DP_DOWNSPREAD_CTRL: %zd\n",
> +				    connector->base.base.id,
> +				    connector->base.name, ret);
> +		} else {
> +			val |= DP_MSA_TIMING_PAR_IGNORE_EN;
> +			drm_dp_mst_dpcd_write(&connector->mst.port->aux,
> +					      DP_DOWNSPREAD_CTRL, &val, 1);
> +		}
> +	}

[Severity: High]
Does this alter the sink behavior unconditionally, even when VRR is not active?

The DP_MSA_TIMING_PAR_IGNORE_EN bit is being written based solely on
intel_vrr_is_capable(connector), bypassing any check for whether VRR is
actually enabled for this atomic state (e.g. crtc_state->vrr.enable).

This will program the sink to ignore MSA video timings even when a fixed
refresh rate is active. Could this lead to display corruption or sync loss
on monitors that expect strict MSA timings during fixed-refresh operation?

[ ... ]

> @@ -1745,6 +1799,14 @@ static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,
>  	if (connector->base.max_bpc_property)
>  		drm_connector_attach_max_bpc_property(&connector->base, 6, 12);
>  
> +	/*
> +	 * Reuse the vrr_capable prop from the eDP connector (which is always
> +	 * initialized during driver load before device registration), because
> +	 * we're not allowed to create new props after device registration.
> +	 */
> +	if (HAS_VRR(display))
> +		drm_connector_attach_vrr_capable_property(&connector->base);

[Severity: High]
Does this safely reuse the property without triggering a kernel WARN_ON?

Although the comment mentions reusing the vrr_capable property, the code
does not seed connector->base.vrr_capable_property with the shared property
pointer before calling drm_connector_attach_vrr_capable_property().

Because it is unseeded, drm_connector_attach_vrr_capable_property() will
try to allocate a new property via drm_property_create_bool(). Creating
new properties after device registration is forbidden and triggers a
WARN_ON in __drm_mode_object_add().

This will also permanently leak a DRM property object in the device's
global property list on every MST hotplug.

[ ... ]

> @@ -1761,6 +1823,9 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
>  	if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd_caps) < 0)
>  		return;
>  
> +	connector->dp.mst_msa_timing_par_ignore =
> +		drm_dp_sink_can_do_video_without_timing_msa(dpcd_caps);

[Severity: High]
Will VRR be disabled on MST monitors that do not support DSC decompression?

The flag mst_msa_timing_par_ignore is populated here, but this function has
an early return higher up:

    if (!connector->dp.dsc_decompression_aux)
        return;

For non-DSC MST displays, this flag remains uninitialized (false). Later,
intel_vrr_is_capable() relies on this cached value to determine VRR
support:

drivers/gpu/drm/i915/display/intel_vrr.c:intel_vrr_is_capable()
    if (!connector->dp.mst_msa_timing_par_ignore)
        return false;

This will cause intel_vrr_is_capable() to unconditionally reject VRR for
any MST display that lacks a DSC decompression AUX port.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260902012852.250993-1-xiaolu.xie@intel.com?part=1

✗ i915.CI.BAT: failure for drm/i915/display: Enable VRR/HDR over MST (rev2)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2882 bytes --]

== Series Details ==

Series: drm/i915/display: Enable VRR/HDR over MST (rev2)
URL   : https://patchwork.freedesktop.org/series/173155/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_19069 -> Patchwork_173155v2
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_173155v2 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_173155v2, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v2/index.html

Participating hosts (37 -> 35)
------------------------------

  Missing    (2): bat-dg2-13 fi-glk-j4005 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_173155v2:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@load:
    - bat-mtlp-9:         [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/bat-mtlp-9/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v2/bat-mtlp-9/igt@i915_module_load@load.html

  
Known issues
------------

  Here are the changes found in Patchwork_173155v2 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1:
    - fi-tgl-1115g4:      [PASS][3] -> [ABORT][4] ([i915#16876]) +1 other test abort
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/fi-tgl-1115g4/igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v2/fi-tgl-1115g4/igt@kms_flip@basic-flip-vs-dpms@c-hdmi-a1.html

  
#### Possible fixes ####

  * igt@kms_pm_rpm@basic-pci-d3-state:
    - fi-kbl-7567u:       [DMESG-WARN][5] ([i915#15673]) -> [PASS][6] +51 other tests pass
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/fi-kbl-7567u/igt@kms_pm_rpm@basic-pci-d3-state.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v2/fi-kbl-7567u/igt@kms_pm_rpm@basic-pci-d3-state.html

  
  [i915#15673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15673
  [i915#16876]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16876


Build changes
-------------

  * Linux: CI_DRM_19069 -> Patchwork_173155v2

  CI-20190529: 20190529
  CI_DRM_19069: c53467440a5196138d2d6610e269a43b6b47bf6b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_9079: 9079
  Patchwork_173155v2: c53467440a5196138d2d6610e269a43b6b47bf6b @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v2/index.html

[-- Attachment #2: Type: text/html, Size: 3533 bytes --]

[PATCH v3] drm/i915/display: Enable VRR/HDR over MST

[Xiao Lu]

VRR over MST:
- Remove the hard MST block in intel_vrr_is_capable(); check the
  downstream port's MSA timing par ignore capability via REMOTE_DPCD_READ
  and cache it in connector->dp.mst_msa_timing_par_ignore to avoid hot
  path sideband round-trips.
- Read mst_msa_timing_par_ignore unconditionally from the sink's virtual
  DPCD before the DSC decompression check, so VRR works on MST sinks
  without DSC support.
- Attach vrr_capable property by reusing the root SST connector's existing
  property object (MST connectors are created post device-registration so
  new properties cannot be created).
- Update vrr_capable after EDID read; gate AS-SDP and DP_MSA_TIMING_PAR_IGNORE_EN
  writes on pipe_config->vrr.enable (actual state) not intel_vrr_is_capable()
  (capability); allow AS-SDP through MST hubs by excluding only non-MST
  branch devices (PCONs) from the branch device check.

HDR metadata over MST:
- Add VSC SDP, HDR metadata infoframe SDP and AS-SDP computation to
  mst_stream_compute_config() and enable their transmission in
  mst_stream_enable() and intel_ddi_update_pipe().
- Lift the hard 8bpc pipe_bpp cap and use the bpp capability from sink EDID
  for MST streams to allow 10bpc, relying on
  intel_dp_mst_atomic_check_link()'s BW retry loop to fall back if the
  link cannot fit it.

Signed-off-by: Xiao Lu <xiaolu.xie@intel.com>
---
 drivers/gpu/drm/display/drm_dp_mst_topology.c |  2 +
 drivers/gpu/drm/i915/display/intel_ddi.c      |  3 +
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 36 ++++----
 drivers/gpu/drm/i915/display/intel_dp.h       |  8 ++
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 83 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.c      | 23 ++++-
 7 files changed, 139 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 7ce9e212770a..174fa62cb0dc 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -2164,6 +2164,7 @@ ssize_t drm_dp_mst_dpcd_read(struct drm_dp_aux *aux,
 	return drm_dp_send_dpcd_read(port->mgr, port,
 				     offset, size, buffer);
 }
+EXPORT_SYMBOL(drm_dp_mst_dpcd_read);
 
 /**
  * drm_dp_mst_dpcd_write() - write a series of bytes to the DPCD via sideband
@@ -2187,6 +2188,7 @@ ssize_t drm_dp_mst_dpcd_write(struct drm_dp_aux *aux,
 	return drm_dp_send_dpcd_write(port->mgr, port,
 				      offset, size, buffer);
 }
+EXPORT_SYMBOL(drm_dp_mst_dpcd_write);
 
 static int drm_dp_check_mstb_guid(struct drm_dp_mst_branch *mstb, guid_t *guid)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b8985e1e0a81..f345d9a2154d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3651,6 +3651,9 @@ void intel_ddi_update_pipe(struct intel_atomic_state *state,
 		intel_ddi_update_pipe_dp(state, encoder, crtc_state,
 					 conn_state);
 
+	if (intel_encoder_is_mst(encoder))
+		intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
+
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		intel_ddi_update_pipe_hdmi(encoder, crtc_state,
 					   conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b7cc361fd955..d09cf18f5376 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -564,6 +564,7 @@ struct intel_connector {
 		u8 dsc_hblank_expansion_quirk:1;
 		u8 dsc_throughput_quirk:1;
 		u8 dsc_decompression_enabled:1;
+		u8 mst_msa_timing_par_ignore:1; /* cached from MST virtual DPCD 0x007 */
 
 		struct {
 			struct {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 113d767e62e9..4b196d26d27f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2682,15 +2682,18 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 
 	limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
 	if (is_mst) {
+		struct intel_connector *mst_connector =
+			to_intel_connector(conn_state->connector);
+		int sink_bpc = mst_connector->base.display_info.bpc ?: 8;
+
 		/*
-		 * FIXME: If all the streams can't fit into the link with their
-		 * current pipe_bpp we should reduce pipe_bpp across the board
-		 * until things start to fit. Until then we limit to <= 8bpc
-		 * since that's what was hardcoded for all MST streams
-		 * previously. This hack should be removed once we have the
-		 * proper retry logic in place.
+		 * For MST streams, use the sink's EDID-reported color depth
+		 * as the max bpp, rather than the pipe_bpp from a previous
+		 * modeset (which may be stale) or a hardcoded 8bpc cap.
+		 * The BW retry loop in intel_dp_mst_atomic_check_link() will
+		 * reduce bpp if the aggregate link bandwidth is insufficient.
 		 */
-		limits->pipe.max_bpp = min(crtc_state->max_pipe_bpp, 24);
+		limits->pipe.max_bpp = sink_bpc * 3;
 	} else {
 		limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
 							respect_downstream_limits);
@@ -3107,9 +3110,12 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
 		return false;
 
 	/*
-	 * #TODO: Add AS SDP v1 support for PCONs (DP branch devices).
+	 * AS-SDP is not yet supported for PCONs (DP-to-HDMI converters).
+	 * MST hubs are also branch devices but do support AS-SDP forwarding
+	 * to downstream sinks; allow it for MST streams.
 	 */
-	if (drm_dp_is_branch(intel_dp->dpcd))
+	if (drm_dp_is_branch(intel_dp->dpcd) &&
+	    !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
 		return false;
 
 	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) &&
@@ -3119,8 +3125,8 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
 	return intel_vrr_possible(crtc_state);
 }
 
-static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
-				    struct intel_crtc_state *crtc_state)
+void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
+			     struct intel_crtc_state *crtc_state)
 {
 	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
 	const struct drm_display_mode *adjusted_mode =
@@ -3169,9 +3175,9 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 		as_sdp->coasting_vtotal = crtc_state->vrr.vmax;
 }
 
-static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
-				     struct intel_crtc_state *crtc_state,
-				     const struct drm_connector_state *conn_state)
+void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
+			      struct intel_crtc_state *crtc_state,
+			      const struct drm_connector_state *conn_state)
 {
 	struct drm_dp_vsc_sdp *vsc;
 
@@ -3228,7 +3234,7 @@ intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state)
 	return hdr_metadata->hdmi_metadata_type1.eotf == HDMI_EOTF_SMPTE_ST2084;
 }
 
-static void
+void
 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
 					    struct intel_crtc_state *crtc_state,
 					    const struct drm_connector_state *conn_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 04fae203bb69..bb68bc3876d6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -77,6 +77,8 @@ int intel_dp_compute_config(struct intel_atomic_state *state,
 			    struct intel_encoder *encoder,
 			    struct intel_crtc_state *pipe_config,
 			    struct drm_connector_state *conn_state);
+void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
+			     struct intel_crtc_state *crtc_state);
 bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state,
 			      bool dsc_enabled_on_crtc);
 void intel_dp_dsc_reset_config(struct intel_crtc_state *crtc_state);
@@ -130,6 +132,12 @@ bool intel_dp_joiner_needs_dsc(struct intel_display *display,
 bool intel_dp_has_joiner(struct intel_dp *intel_dp);
 bool intel_dp_needs_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
 				    const struct drm_connector_state *conn_state);
+void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
+			      struct intel_crtc_state *crtc_state,
+			      const struct drm_connector_state *conn_state);
+void intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
+						  struct intel_crtc_state *crtc_state,
+						  const struct drm_connector_state *conn_state);
 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
 			     const struct intel_crtc_state *crtc_state,
 			     const struct drm_connector_state *conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 3be1643f8d03..e66f9508cb72 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -793,6 +793,9 @@ static int mst_stream_compute_config(struct intel_atomic_state *state,
 			bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
 
 	intel_vrr_compute_config(pipe_config, conn_state);
+	intel_dp_compute_as_sdp(intel_dp, pipe_config);
+	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
+	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
 
 	intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
 
@@ -1157,6 +1160,24 @@ static void mst_stream_post_disable(struct intel_atomic_state *state,
 	 * Power down mst path before disabling the port, otherwise we end
 	 * up getting interrupts from the sink upon detecting link loss.
 	 */
+	if (old_crtc_state->vrr.enable) {
+		u8 val;
+		ssize_t ret;
+
+		ret = drm_dp_mst_dpcd_read(&connector->mst.port->aux,
+					   DP_DOWNSPREAD_CTRL, &val, 1);
+		if (ret < 0) {
+			drm_dbg_kms(display->drm,
+				    "[CONNECTOR:%d:%s] Failed to read DP_DOWNSPREAD_CTRL: %zd\n",
+				    connector->base.base.id,
+				    connector->base.name, ret);
+		} else {
+			val &= ~DP_MSA_TIMING_PAR_IGNORE_EN;
+			drm_dp_mst_dpcd_write(&connector->mst.port->aux,
+					      DP_DOWNSPREAD_CTRL, &val, 1);
+		}
+	}
+
 	drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port,
 				     false);
 
@@ -1274,6 +1295,24 @@ static void mst_stream_pre_enable(struct intel_atomic_state *state,
 
 	drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port, true);
 
+	if (pipe_config->vrr.enable) {
+		u8 val;
+		ssize_t ret;
+
+		ret = drm_dp_mst_dpcd_read(&connector->mst.port->aux,
+					   DP_DOWNSPREAD_CTRL, &val, 1);
+		if (ret < 0) {
+			drm_dbg_kms(display->drm,
+				    "[CONNECTOR:%d:%s] Failed to read DP_DOWNSPREAD_CTRL: %zd\n",
+				    connector->base.base.id,
+				    connector->base.name, ret);
+		} else {
+			val |= DP_MSA_TIMING_PAR_IGNORE_EN;
+			drm_dp_mst_dpcd_write(&connector->mst.port->aux,
+					      DP_DOWNSPREAD_CTRL, &val, 1);
+		}
+	}
+
 	intel_dp_sink_enable_decompression(state, connector, pipe_config);
 
 	if (first_mst_stream) {
@@ -1397,6 +1436,8 @@ static void mst_stream_enable(struct intel_atomic_state *state,
 
 	intel_enable_transcoder(pipe_config);
 
+	intel_dp_set_infoframes(encoder, true, pipe_config, conn_state);
+
 	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, pipe_config) {
 		const struct intel_crtc_state *pipe_crtc_state =
 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
@@ -1451,6 +1492,15 @@ static int mst_connector_get_ddc_modes(struct drm_connector *_connector)
 
 	ret = intel_connector_update_modes(&connector->base, drm_edid);
 
+	if (HAS_VRR(display)) {
+		bool vrr_capable = intel_vrr_is_capable(connector);
+
+		drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
+			    connector->base.base.id, connector->base.name,
+			    str_yes_no(vrr_capable));
+		drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
+	}
+
 	drm_edid_free(drm_edid);
 
 	if (intel_dp_tunnel_uhbr_lanes_wa_setup(intel_dp)) {
@@ -1735,6 +1785,10 @@ static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,
 
 	intel_attach_force_audio_property(&connector->base);
 	intel_attach_broadcast_rgb_property(&connector->base);
+	intel_attach_dp_colorspace_property(&connector->base);
+
+	if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
+		drm_connector_attach_hdr_output_metadata_property(&connector->base);
 
 	/*
 	 * Reuse the prop from the SST connector because we're
@@ -1745,6 +1799,23 @@ static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,
 	if (connector->base.max_bpc_property)
 		drm_connector_attach_max_bpc_property(&connector->base, 6, 12);
 
+	/*
+	 * Reuse the vrr_capable prop from the eDP connector (which is always
+	 * initialized during driver load before device registration), because
+	 * we're not allowed to create new props after device registration.
+	 */
+	/*
+	 * Reuse the vrr_capable property from the root intel_dp SST connector
+	 * which was created during driver load (before device registration).
+	 * MST connectors are created after device registration, so we cannot
+	 * create new properties here - we must attach the existing one.
+	 */
+	if (HAS_VRR(display) && intel_dp->attached_connector &&
+	    intel_dp->attached_connector->base.vrr_capable_property)
+		drm_object_attach_property(&connector->base.base,
+					   intel_dp->attached_connector->base.vrr_capable_property,
+					   0);
+
 	return drm_connector_set_path_property(&connector->base, pathprop);
 }
 
@@ -1755,6 +1826,18 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
 	u8 dpcd_caps[DP_RECEIVER_CAP_SIZE];
 	struct drm_dp_desc desc;
 
+	/*
+	 * Read MSA timing par ignore capability from the sink's virtual DPCD.
+	 * This is independent of DSC support so read it before the DSC check.
+	 */
+	{
+		u8 mst_dpcd[DP_RECEIVER_CAP_SIZE];
+
+		if (drm_dp_read_dpcd_caps(&connector->mst.port->aux, mst_dpcd) == 0)
+			connector->dp.mst_msa_timing_par_ignore =
+				drm_dp_sink_can_do_video_without_timing_msa(mst_dpcd);
+	}
+
 	if (!connector->dp.dsc_decompression_aux)
 		return;
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 51e4f3309b8b..13cd5701bf2c 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -55,8 +55,27 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
 			return false;
 		fallthrough;
 	case DRM_MODE_CONNECTOR_DisplayPort:
-		if (connector->mst.dp)
-			return false;
+		if (connector->mst.dp) {
+			u8 dpcd[DP_RECEIVER_CAP_SIZE];
+
+			/*
+			 * Use cached MSA timing ignore capability from the DFP
+			 * sink's virtual DPCD, set during connector init.
+			 */
+			if (!connector->dp.mst_msa_timing_par_ignore)
+				return false;
+
+			/*
+			 * Also verify live via LCT=2 REMOTE_DPCD_READ to the
+			 * DFP sink's actual DPCD 0x007.
+			 */
+			if (drm_dp_read_dpcd_caps(&connector->mst.port->aux, dpcd) < 0)
+				return false;
+			if (!drm_dp_sink_can_do_video_without_timing_msa(dpcd))
+				return false;
+
+			break;
+		}
 		intel_dp = intel_attached_dp(connector);
 		/*
 		 * Among non-MST DP branch devices, only an HDMI 2.1 sink connected
-- 
2.43.0

Re: [PATCH v3] drm/i915/display: Enable VRR/HDR over MST

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Live hardware DPCD read over MST sideband during the atomic check phase causes severe latency and potential Denial of Service.
- [Medium] The `vrr_capable` property value cannot be updated for MST connectors because `connector->base.vrr_capable_property` is never assigned.
- [Medium] VRR and AS-SDP are incorrectly allowed for PCONs (DP-to-HDMI adapters) connected via MST hubs, bypassing the explicit restriction against branch devices.
--

commit a21faad85b4c3ba1fae63f3e870858e7080a68a3
Author: Xiao Lu <xiaolu.xie@intel.com>

drm/i915/display: Enable VRR/HDR over MST

This commit enables Variable Refresh Rate (VRR) and HDR metadata over MST
in the i915 driver. It retrieves the downstream port's MSA timing
capabilities to support VRR and transmits AS-SDP and HDR metadata
infoframes over MST streams.

> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 113d767e62e9c..4b196d26d27f8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c

[ ... ]

> @@ -3107,9 +3110,12 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
>  		return false;
>  
>  	/*
> -	 * #TODO: Add AS SDP v1 support for PCONs (DP branch devices).
> +	 * AS-SDP is not yet supported for PCONs (DP-to-HDMI converters).
> +	 * MST hubs are also branch devices but do support AS-SDP forwarding
> +	 * to downstream sinks; allow it for MST streams.
>  	 */
> -	if (drm_dp_is_branch(intel_dp->dpcd))
> +	if (drm_dp_is_branch(intel_dp->dpcd) &&
> +	    !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
>  		return false;

[Severity: Medium]
Does this blanket exception for MST streams allow AS-SDP to be sent to
explicitly unsupported branch devices (like PCONs) that are downstream of an
MST hub?

[ ... ]

> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 3be1643f8d030..e66f9508cb720 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c

[ ... ]

> @@ -1451,6 +1492,15 @@ static int mst_connector_get_ddc_modes(struct drm_connector *_connector)
>  
>  	ret = intel_connector_update_modes(&connector->base, drm_edid);
>  
> +	if (HAS_VRR(display)) {
> +		bool vrr_capable = intel_vrr_is_capable(connector);
> +
> +		drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
> +			    connector->base.base.id, connector->base.name,
> +			    str_yes_no(vrr_capable));
> +		drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
> +	}
> +

[Severity: Medium]
Will this call to drm_connector_set_vrr_capable_property() silently do
nothing because connector->base.vrr_capable_property is never assigned for
MST connectors?

The property is attached to the DRM object in
mst_topology_add_connector_properties(), but the pointer itself remains
NULL, which makes the feature invisible to userspace.

[ ... ]

> @@ -1745,6 +1799,23 @@ static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,
>  	if (connector->base.max_bpc_property)
>  		drm_connector_attach_max_bpc_property(&connector->base, 6, 12);
>  
> +	/*
> +	 * Reuse the vrr_capable prop from the eDP connector (which is always
> +	 * initialized during driver load before device registration), because
> +	 * we're not allowed to create new props after device registration.
> +	 */
> +	/*
> +	 * Reuse the vrr_capable property from the root intel_dp SST connector
> +	 * which was created during driver load (before device registration).
> +	 * MST connectors are created after device registration, so we cannot
> +	 * create new properties here - we must attach the existing one.
> +	 */
> +	if (HAS_VRR(display) && intel_dp->attached_connector &&
> +	    intel_dp->attached_connector->base.vrr_capable_property)
> +		drm_object_attach_property(&connector->base.base,
> +					   intel_dp->attached_connector->base.vrr_capable_property,
> +					   0);
> +

[Severity: Medium]
Should this also explicitly assign connector->base.vrr_capable_property so
that later updates to the property work correctly?

[ ... ]

> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 51e4f3309b8b1..13cd5701bf2c1 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c

[ ... ]

> @@ -55,8 +55,27 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
>  			return false;
>  		fallthrough;
>  	case DRM_MODE_CONNECTOR_DisplayPort:
> -		if (connector->mst.dp)
> -			return false;
> +		if (connector->mst.dp) {
> +			u8 dpcd[DP_RECEIVER_CAP_SIZE];
> +
> +			/*
> +			 * Use cached MSA timing ignore capability from the DFP
> +			 * sink's virtual DPCD, set during connector init.
> +			 */
> +			if (!connector->dp.mst_msa_timing_par_ignore)
> +				return false;
> +
> +			/*
> +			 * Also verify live via LCT=2 REMOTE_DPCD_READ to the
> +			 * DFP sink's actual DPCD 0x007.
> +			 */
> +			if (drm_dp_read_dpcd_caps(&connector->mst.port->aux, dpcd) < 0)
> +				return false;

[Severity: High]
Can this live hardware DPCD read over the MST sideband cause latency and
potential Denial of Service during the atomic check phase?

Since mst_stream_compute_config() calls intel_vrr_compute_config(), which
in turn calls intel_vrr_is_capable(), this adds a blocking sideband I/O
transaction to the hot KMS atomic_check path. Untrusted userspace
applications spamming DRM_IOCTL_MODE_ATOMIC with the TEST_ONLY flag could
exploit this to saturate the CPU and MST sideband communication channel.

> +			if (!drm_dp_sink_can_do_video_without_timing_msa(dpcd))
> +				return false;
> +
> +			break;

[Severity: Medium]
Is there a missing check for drm_dp_is_branch(dpcd) here?

By omitting it for MST streams, branch devices like PCONs connected behind
MST hubs might be incorrectly considered VRR-capable, bypassing the explicit
restriction against branch devices.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260902030042.258193-1-xiaolu.xie@intel.com?part=1

[PATCH v4] drm/i915/display: Enable VRR/HDR over MST

[Xiao Lu]

VRR over MST:
- Remove the hard MST block in intel_vrr_is_capable(); check the
  downstream port's MSA timing par ignore capability via REMOTE_DPCD_READ
  and cache it in connector->dp.mst_msa_timing_par_ignore to avoid hot
  path sideband round-trips.
- Read mst_msa_timing_par_ignore unconditionally from the sink's virtual
  DPCD before the DSC decompression check, so VRR works on MST sinks
  without DSC support.
- Attach vrr_capable property by reusing the root SST connector's existing
  property object (MST connectors are created post device-registration so
  new properties cannot be created).
- Update vrr_capable after EDID read; gate AS-SDP and DP_MSA_TIMING_PAR_IGNORE_EN
  writes on pipe_config->vrr.enable (actual state) not intel_vrr_is_capable()
  (capability); allow AS-SDP through MST hubs by excluding only non-MST
  branch devices (PCONs) from the branch device check.

HDR metadata over MST:
- Add VSC SDP, HDR metadata infoframe SDP and AS-SDP computation to
  mst_stream_compute_config() and enable their transmission in
  mst_stream_enable() and intel_ddi_update_pipe().
- Lift the hard 8bpc pipe_bpp cap and use the bpp capability from sink EDID
  for MST streams to allow 10bpc, relying on
  intel_dp_mst_atomic_check_link()'s BW retry loop to fall back if the
  link cannot fit it.

Signed-off-by: Xiao Lu <xiaolu.xie@intel.com>
---
 drivers/gpu/drm/display/drm_dp_mst_topology.c |  2 +
 drivers/gpu/drm/i915/display/intel_ddi.c      |  3 +
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 36 ++++---
 drivers/gpu/drm/i915/display/intel_dp.h       |  8 ++
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 94 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.c      | 15 ++-
 7 files changed, 142 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 7ce9e212770a..174fa62cb0dc 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -2164,6 +2164,7 @@ ssize_t drm_dp_mst_dpcd_read(struct drm_dp_aux *aux,
 	return drm_dp_send_dpcd_read(port->mgr, port,
 				     offset, size, buffer);
 }
+EXPORT_SYMBOL(drm_dp_mst_dpcd_read);
 
 /**
  * drm_dp_mst_dpcd_write() - write a series of bytes to the DPCD via sideband
@@ -2187,6 +2188,7 @@ ssize_t drm_dp_mst_dpcd_write(struct drm_dp_aux *aux,
 	return drm_dp_send_dpcd_write(port->mgr, port,
 				      offset, size, buffer);
 }
+EXPORT_SYMBOL(drm_dp_mst_dpcd_write);
 
 static int drm_dp_check_mstb_guid(struct drm_dp_mst_branch *mstb, guid_t *guid)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b8985e1e0a81..f345d9a2154d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3651,6 +3651,9 @@ void intel_ddi_update_pipe(struct intel_atomic_state *state,
 		intel_ddi_update_pipe_dp(state, encoder, crtc_state,
 					 conn_state);
 
+	if (intel_encoder_is_mst(encoder))
+		intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
+
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		intel_ddi_update_pipe_hdmi(encoder, crtc_state,
 					   conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b7cc361fd955..d09cf18f5376 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -564,6 +564,7 @@ struct intel_connector {
 		u8 dsc_hblank_expansion_quirk:1;
 		u8 dsc_throughput_quirk:1;
 		u8 dsc_decompression_enabled:1;
+		u8 mst_msa_timing_par_ignore:1; /* cached from MST virtual DPCD 0x007 */
 
 		struct {
 			struct {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 113d767e62e9..4b196d26d27f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2682,15 +2682,18 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 
 	limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
 	if (is_mst) {
+		struct intel_connector *mst_connector =
+			to_intel_connector(conn_state->connector);
+		int sink_bpc = mst_connector->base.display_info.bpc ?: 8;
+
 		/*
-		 * FIXME: If all the streams can't fit into the link with their
-		 * current pipe_bpp we should reduce pipe_bpp across the board
-		 * until things start to fit. Until then we limit to <= 8bpc
-		 * since that's what was hardcoded for all MST streams
-		 * previously. This hack should be removed once we have the
-		 * proper retry logic in place.
+		 * For MST streams, use the sink's EDID-reported color depth
+		 * as the max bpp, rather than the pipe_bpp from a previous
+		 * modeset (which may be stale) or a hardcoded 8bpc cap.
+		 * The BW retry loop in intel_dp_mst_atomic_check_link() will
+		 * reduce bpp if the aggregate link bandwidth is insufficient.
 		 */
-		limits->pipe.max_bpp = min(crtc_state->max_pipe_bpp, 24);
+		limits->pipe.max_bpp = sink_bpc * 3;
 	} else {
 		limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
 							respect_downstream_limits);
@@ -3107,9 +3110,12 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
 		return false;
 
 	/*
-	 * #TODO: Add AS SDP v1 support for PCONs (DP branch devices).
+	 * AS-SDP is not yet supported for PCONs (DP-to-HDMI converters).
+	 * MST hubs are also branch devices but do support AS-SDP forwarding
+	 * to downstream sinks; allow it for MST streams.
 	 */
-	if (drm_dp_is_branch(intel_dp->dpcd))
+	if (drm_dp_is_branch(intel_dp->dpcd) &&
+	    !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
 		return false;
 
 	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) &&
@@ -3119,8 +3125,8 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
 	return intel_vrr_possible(crtc_state);
 }
 
-static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
-				    struct intel_crtc_state *crtc_state)
+void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
+			     struct intel_crtc_state *crtc_state)
 {
 	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
 	const struct drm_display_mode *adjusted_mode =
@@ -3169,9 +3175,9 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 		as_sdp->coasting_vtotal = crtc_state->vrr.vmax;
 }
 
-static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
-				     struct intel_crtc_state *crtc_state,
-				     const struct drm_connector_state *conn_state)
+void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
+			      struct intel_crtc_state *crtc_state,
+			      const struct drm_connector_state *conn_state)
 {
 	struct drm_dp_vsc_sdp *vsc;
 
@@ -3228,7 +3234,7 @@ intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state)
 	return hdr_metadata->hdmi_metadata_type1.eotf == HDMI_EOTF_SMPTE_ST2084;
 }
 
-static void
+void
 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
 					    struct intel_crtc_state *crtc_state,
 					    const struct drm_connector_state *conn_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 04fae203bb69..bb68bc3876d6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -77,6 +77,8 @@ int intel_dp_compute_config(struct intel_atomic_state *state,
 			    struct intel_encoder *encoder,
 			    struct intel_crtc_state *pipe_config,
 			    struct drm_connector_state *conn_state);
+void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
+			     struct intel_crtc_state *crtc_state);
 bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state,
 			      bool dsc_enabled_on_crtc);
 void intel_dp_dsc_reset_config(struct intel_crtc_state *crtc_state);
@@ -130,6 +132,12 @@ bool intel_dp_joiner_needs_dsc(struct intel_display *display,
 bool intel_dp_has_joiner(struct intel_dp *intel_dp);
 bool intel_dp_needs_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
 				    const struct drm_connector_state *conn_state);
+void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
+			      struct intel_crtc_state *crtc_state,
+			      const struct drm_connector_state *conn_state);
+void intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
+						  struct intel_crtc_state *crtc_state,
+						  const struct drm_connector_state *conn_state);
 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
 			     const struct intel_crtc_state *crtc_state,
 			     const struct drm_connector_state *conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 3be1643f8d03..021d86b0ed83 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -793,6 +793,9 @@ static int mst_stream_compute_config(struct intel_atomic_state *state,
 			bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
 
 	intel_vrr_compute_config(pipe_config, conn_state);
+	intel_dp_compute_as_sdp(intel_dp, pipe_config);
+	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
+	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
 
 	intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
 
@@ -1157,6 +1160,24 @@ static void mst_stream_post_disable(struct intel_atomic_state *state,
 	 * Power down mst path before disabling the port, otherwise we end
 	 * up getting interrupts from the sink upon detecting link loss.
 	 */
+	if (old_crtc_state->vrr.enable) {
+		u8 val;
+		ssize_t ret;
+
+		ret = drm_dp_mst_dpcd_read(&connector->mst.port->aux,
+					   DP_DOWNSPREAD_CTRL, &val, 1);
+		if (ret < 0) {
+			drm_dbg_kms(display->drm,
+				    "[CONNECTOR:%d:%s] Failed to read DP_DOWNSPREAD_CTRL: %zd\n",
+				    connector->base.base.id,
+				    connector->base.name, ret);
+		} else {
+			val &= ~DP_MSA_TIMING_PAR_IGNORE_EN;
+			drm_dp_mst_dpcd_write(&connector->mst.port->aux,
+					      DP_DOWNSPREAD_CTRL, &val, 1);
+		}
+	}
+
 	drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port,
 				     false);
 
@@ -1274,6 +1295,24 @@ static void mst_stream_pre_enable(struct intel_atomic_state *state,
 
 	drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port, true);
 
+	if (pipe_config->vrr.enable) {
+		u8 val;
+		ssize_t ret;
+
+		ret = drm_dp_mst_dpcd_read(&connector->mst.port->aux,
+					   DP_DOWNSPREAD_CTRL, &val, 1);
+		if (ret < 0) {
+			drm_dbg_kms(display->drm,
+				    "[CONNECTOR:%d:%s] Failed to read DP_DOWNSPREAD_CTRL: %zd\n",
+				    connector->base.base.id,
+				    connector->base.name, ret);
+		} else {
+			val |= DP_MSA_TIMING_PAR_IGNORE_EN;
+			drm_dp_mst_dpcd_write(&connector->mst.port->aux,
+					      DP_DOWNSPREAD_CTRL, &val, 1);
+		}
+	}
+
 	intel_dp_sink_enable_decompression(state, connector, pipe_config);
 
 	if (first_mst_stream) {
@@ -1397,6 +1436,8 @@ static void mst_stream_enable(struct intel_atomic_state *state,
 
 	intel_enable_transcoder(pipe_config);
 
+	intel_dp_set_infoframes(encoder, true, pipe_config, conn_state);
+
 	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, pipe_config) {
 		const struct intel_crtc_state *pipe_crtc_state =
 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
@@ -1451,6 +1492,15 @@ static int mst_connector_get_ddc_modes(struct drm_connector *_connector)
 
 	ret = intel_connector_update_modes(&connector->base, drm_edid);
 
+	if (HAS_VRR(display)) {
+		bool vrr_capable = intel_vrr_is_capable(connector);
+
+		drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
+			    connector->base.base.id, connector->base.name,
+			    str_yes_no(vrr_capable));
+		drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
+	}
+
 	drm_edid_free(drm_edid);
 
 	if (intel_dp_tunnel_uhbr_lanes_wa_setup(intel_dp)) {
@@ -1735,6 +1785,10 @@ static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,
 
 	intel_attach_force_audio_property(&connector->base);
 	intel_attach_broadcast_rgb_property(&connector->base);
+	intel_attach_dp_colorspace_property(&connector->base);
+
+	if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
+		drm_connector_attach_hdr_output_metadata_property(&connector->base);
 
 	/*
 	 * Reuse the prop from the SST connector because we're
@@ -1745,6 +1799,34 @@ static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,
 	if (connector->base.max_bpc_property)
 		drm_connector_attach_max_bpc_property(&connector->base, 6, 12);
 
+	/*
+	 * Reuse the vrr_capable prop from the eDP connector (which is always
+	 * initialized during driver load before device registration), because
+	 * we're not allowed to create new props after device registration.
+	 */
+	/*
+	 * Reuse the vrr_capable property from the root intel_dp SST connector
+	 * which was created during driver load (before device registration).
+	 * MST connectors are created after device registration, so we cannot
+	 * create new properties here - we must attach the existing one.
+	 */
+	/*
+	 * Reuse the vrr_capable property from the root intel_dp SST connector
+	 * which was created during driver load (before device registration).
+	 * MST connectors are created after device registration, so we cannot
+	 * create new properties here - we must attach the existing one.
+	 * Also assign connector->vrr_capable_property so that
+	 * drm_connector_set_vrr_capable_property() can update the value.
+	 */
+	if (HAS_VRR(display) && intel_dp->attached_connector &&
+	    intel_dp->attached_connector->base.vrr_capable_property) {
+		connector->base.vrr_capable_property =
+			intel_dp->attached_connector->base.vrr_capable_property;
+		drm_object_attach_property(&connector->base.base,
+					   connector->base.vrr_capable_property,
+					   0);
+	}
+
 	return drm_connector_set_path_property(&connector->base, pathprop);
 }
 
@@ -1755,6 +1837,18 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
 	u8 dpcd_caps[DP_RECEIVER_CAP_SIZE];
 	struct drm_dp_desc desc;
 
+	/*
+	 * Read MSA timing par ignore capability from the sink's virtual DPCD.
+	 * This is independent of DSC support so read it before the DSC check.
+	 */
+	{
+		u8 mst_dpcd[DP_RECEIVER_CAP_SIZE];
+
+		if (drm_dp_read_dpcd_caps(&connector->mst.port->aux, mst_dpcd) == 0)
+			connector->dp.mst_msa_timing_par_ignore =
+				drm_dp_sink_can_do_video_without_timing_msa(mst_dpcd);
+	}
+
 	if (!connector->dp.dsc_decompression_aux)
 		return;
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 51e4f3309b8b..9737a19c1899 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -55,8 +55,19 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
 			return false;
 		fallthrough;
 	case DRM_MODE_CONNECTOR_DisplayPort:
-		if (connector->mst.dp)
-			return false;
+		if (connector->mst.dp) {
+			/*
+			 * Use cached MSA timing ignore capability from the DFP
+			 * sink's virtual DPCD, set during connector init in
+			 * intel_dp_mst_read_decompression_port_dsc_caps().
+			 * Avoid live sideband reads here as this function is
+			 * called from the atomic check path.
+			 */
+			if (!connector->dp.mst_msa_timing_par_ignore)
+				return false;
+
+			break;
+		}
 		intel_dp = intel_attached_dp(connector);
 		/*
 		 * Among non-MST DP branch devices, only an HDMI 2.1 sink connected
-- 
2.43.0

Re: [PATCH v4] drm/i915/display: Enable VRR/HDR over MST

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [Medium] Bypassing the DP branch device check for MST streams enables VRR and AS-SDP on MST leaf ports that are PCONs, which is explicitly unsupported.
- [Low] Triply duplicated comment block explaining the reuse of the vrr_capable_property.
--

commit 0a351efb0934b17f15e6de16fd0583d3287db2d9
Author: Xiao Lu <xiaolu.xie@intel.com>
Subject: drm/i915/display: Enable VRR/HDR over MST

This commit enables Variable Refresh Rate (VRR) and HDR metadata transmission
over DisplayPort Multi-Stream Transport (MST). It introduces caching of the MSA
timing ignore capability to avoid hot path sideband reads. It also reuses SST
properties for MST streams and lifts previous pipe_bpp caps.

> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 113d767e62e9c..4b196d26d27f8 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -3107,9 +3110,12 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
>  		return false;
>  
>  	/*
> -	 * #TODO: Add AS SDP v1 support for PCONs (DP branch devices).
> +	 * AS-SDP is not yet supported for PCONs (DP-to-HDMI converters).
> +	 * MST hubs are also branch devices but do support AS-SDP forwarding
> +	 * to downstream sinks; allow it for MST streams.
>  	 */
> -	if (drm_dp_is_branch(intel_dp->dpcd))
> +	if (drm_dp_is_branch(intel_dp->dpcd) &&
> +	    !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
>  		return false;

[Severity: Medium]
Does this explicit exemption of MST streams enable AS-SDP packets even if the
downstream MST leaf port is an unsupported PCON?

Because MST streams are exempted from the branch device block here, AS-SDP
packets will be sent to MST streams even when the leaf port is a PCON that
doesn't fully support it.

> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 3be1643f8d030..021d86b0ed833 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -1745,6 +1799,34 @@ static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,
>  	if (connector->base.max_bpc_property)
>  		drm_connector_attach_max_bpc_property(&connector->base, 6, 12);
>  
> +	/*
> +	 * Reuse the vrr_capable prop from the eDP connector (which is always
> +	 * initialized during driver load before device registration), because
> +	 * we're not allowed to create new props after device registration.
> +	 */
> +	/*
> +	 * Reuse the vrr_capable property from the root intel_dp SST connector
> +	 * which was created during driver load (before device registration).
> +	 * MST connectors are created after device registration, so we cannot
> +	 * create new properties here - we must attach the existing one.
> +	 */
> +	/*
> +	 * Reuse the vrr_capable property from the root intel_dp SST connector
> +	 * which was created during driver load (before device registration).
> +	 * MST connectors are created after device registration, so we cannot
> +	 * create new properties here - we must attach the existing one.
> +	 * Also assign connector->vrr_capable_property so that
> +	 * drm_connector_set_vrr_capable_property() can update the value.
> +	 */

[Severity: Low]
This isn't a bug, but it looks like the comment block explaining the reuse of
the vrr_capable_property was duplicated three times.

> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 51e4f3309b8b1..9737a19c1899f 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -55,8 +55,19 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
>  			return false;
>  		fallthrough;
>  	case DRM_MODE_CONNECTOR_DisplayPort:
> -		if (connector->mst.dp)
> -			return false;
> +		if (connector->mst.dp) {
> +			/*
> +			 * Use cached MSA timing ignore capability from the DFP
> +			 * sink's virtual DPCD, set during connector init in
> +			 * intel_dp_mst_read_decompression_port_dsc_caps().
> +			 * Avoid live sideband reads here as this function is
> +			 * called from the atomic check path.
> +			 */
> +			if (!connector->dp.mst_msa_timing_par_ignore)
> +				return false;
> +
> +			break;
> +		}

[Severity: Medium]
Will this early break for MST streams incorrectly bypass the branch device
check for PCONs?

By breaking out early for MST streams here, the function skips the subsequent
drm_dp_is_branch() check. This means MST leaf ports that are PCONs are
treated as direct VRR-capable sinks if they advertise MSA timing ignore in
their virtual DPCD, which is explicitly unsupported.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260902032207.259156-1-xiaolu.xie@intel.com?part=1

✗ i915.CI.BAT: failure for drm/i915/display: Enable VRR/HDR over MST (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3235 bytes --]

== Series Details ==

Series: drm/i915/display: Enable VRR/HDR over MST (rev4)
URL   : https://patchwork.freedesktop.org/series/173155/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_19069 -> Patchwork_173155v4
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_173155v4 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_173155v4, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v4/index.html

Participating hosts (37 -> 36)
------------------------------

  Missing    (1): bat-dg2-13 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_173155v4:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_module_load@load:
    - bat-mtlp-9:         [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/bat-mtlp-9/igt@i915_module_load@load.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v4/bat-mtlp-9/igt@i915_module_load@load.html

  
Known issues
------------

  Here are the changes found in Patchwork_173155v4 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@ring_submission:
    - fi-cfl-8109u:       [PASS][3] -> [DMESG-WARN][4] ([i915#13735]) +32 other tests dmesg-warn
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v4/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html

  * igt@kms_pipe_crc_basic@read-crc:
    - fi-cfl-8109u:       [PASS][5] -> [DMESG-WARN][6] ([i915#15673]) +48 other tests dmesg-warn
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v4/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc.html

  
#### Possible fixes ####

  * igt@kms_pm_rpm@basic-pci-d3-state:
    - fi-kbl-7567u:       [DMESG-WARN][7] ([i915#15673]) -> [PASS][8] +51 other tests pass
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/fi-kbl-7567u/igt@kms_pm_rpm@basic-pci-d3-state.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v4/fi-kbl-7567u/igt@kms_pm_rpm@basic-pci-d3-state.html

  
  [i915#13735]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13735
  [i915#15673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15673


Build changes
-------------

  * Linux: CI_DRM_19069 -> Patchwork_173155v4

  CI-20190529: 20190529
  CI_DRM_19069: c53467440a5196138d2d6610e269a43b6b47bf6b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_9079: 9079
  Patchwork_173155v4: c53467440a5196138d2d6610e269a43b6b47bf6b @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v4/index.html

[-- Attachment #2: Type: text/html, Size: 4001 bytes --]

[PATCH v5] drm/i915/display: Enable VRR/HDR over MST

[Xiao Lu]

VRR over MST:
- Remove the hard MST block in intel_vrr_is_capable(); check the
  downstream port's MSA timing par ignore capability via REMOTE_DPCD_READ
  and cache it in connector->dp.mst_msa_timing_par_ignore to avoid hot
  path sideband round-trips.
- Read mst_msa_timing_par_ignore unconditionally from the sink's virtual
  DPCD before the DSC decompression check, so VRR works on MST sinks
  without DSC support.
- Attach vrr_capable property by reusing the root SST connector's existing
  property object (MST connectors are created post device-registration so
  new properties cannot be created).
- Update vrr_capable after EDID read; gate AS-SDP and
  DP_MSA_TIMING_PAR_IGNORE_EN writes on pipe_config->vrr.enable
  (actual state) not intel_vrr_is_capable() (capability); allow AS-SDP
  through MST hubs by excluding only non-MST branch devices (PCONs)
  from the branch device check.
- Reuse colorspace property from root SST connector for MST connectors
  to avoid WARN_ON from creating properties post device-registration.

HDR metadata over MST:
- Add VSC SDP, HDR metadata infoframe SDP and AS-SDP computation to
  mst_stream_compute_config() and enable their transmission in
  mst_stream_enable() and intel_ddi_update_pipe().
- Lift the hard 8bpc pipe_bpp cap and use the bpp capability from sink
  EDID for MST streams to allow 10bpc, relying on
  intel_dp_mst_atomic_check_link()'s BW retry loop to fall back if the
  link cannot fit it.

Signed-off-by: Xiao Lu <xiaolu.xie@intel.com>
---
 drivers/gpu/drm/display/drm_dp_mst_topology.c |   2 +
 drivers/gpu/drm/i915/display/intel_ddi.c      |   3 +
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  36 +++---
 drivers/gpu/drm/i915/display/intel_dp.h       |   8 ++
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 106 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.c      |  15 ++-
 7 files changed, 154 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 7ce9e212770a..174fa62cb0dc 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -2164,6 +2164,7 @@ ssize_t drm_dp_mst_dpcd_read(struct drm_dp_aux *aux,
 	return drm_dp_send_dpcd_read(port->mgr, port,
 				     offset, size, buffer);
 }
+EXPORT_SYMBOL(drm_dp_mst_dpcd_read);
 
 /**
  * drm_dp_mst_dpcd_write() - write a series of bytes to the DPCD via sideband
@@ -2187,6 +2188,7 @@ ssize_t drm_dp_mst_dpcd_write(struct drm_dp_aux *aux,
 	return drm_dp_send_dpcd_write(port->mgr, port,
 				      offset, size, buffer);
 }
+EXPORT_SYMBOL(drm_dp_mst_dpcd_write);
 
 static int drm_dp_check_mstb_guid(struct drm_dp_mst_branch *mstb, guid_t *guid)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b8985e1e0a81..f345d9a2154d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3651,6 +3651,9 @@ void intel_ddi_update_pipe(struct intel_atomic_state *state,
 		intel_ddi_update_pipe_dp(state, encoder, crtc_state,
 					 conn_state);
 
+	if (intel_encoder_is_mst(encoder))
+		intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
+
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		intel_ddi_update_pipe_hdmi(encoder, crtc_state,
 					   conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b7cc361fd955..d09cf18f5376 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -564,6 +564,7 @@ struct intel_connector {
 		u8 dsc_hblank_expansion_quirk:1;
 		u8 dsc_throughput_quirk:1;
 		u8 dsc_decompression_enabled:1;
+		u8 mst_msa_timing_par_ignore:1; /* cached from MST virtual DPCD 0x007 */
 
 		struct {
 			struct {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 113d767e62e9..4b196d26d27f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2682,15 +2682,18 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 
 	limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
 	if (is_mst) {
+		struct intel_connector *mst_connector =
+			to_intel_connector(conn_state->connector);
+		int sink_bpc = mst_connector->base.display_info.bpc ?: 8;
+
 		/*
-		 * FIXME: If all the streams can't fit into the link with their
-		 * current pipe_bpp we should reduce pipe_bpp across the board
-		 * until things start to fit. Until then we limit to <= 8bpc
-		 * since that's what was hardcoded for all MST streams
-		 * previously. This hack should be removed once we have the
-		 * proper retry logic in place.
+		 * For MST streams, use the sink's EDID-reported color depth
+		 * as the max bpp, rather than the pipe_bpp from a previous
+		 * modeset (which may be stale) or a hardcoded 8bpc cap.
+		 * The BW retry loop in intel_dp_mst_atomic_check_link() will
+		 * reduce bpp if the aggregate link bandwidth is insufficient.
 		 */
-		limits->pipe.max_bpp = min(crtc_state->max_pipe_bpp, 24);
+		limits->pipe.max_bpp = sink_bpc * 3;
 	} else {
 		limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
 							respect_downstream_limits);
@@ -3107,9 +3110,12 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
 		return false;
 
 	/*
-	 * #TODO: Add AS SDP v1 support for PCONs (DP branch devices).
+	 * AS-SDP is not yet supported for PCONs (DP-to-HDMI converters).
+	 * MST hubs are also branch devices but do support AS-SDP forwarding
+	 * to downstream sinks; allow it for MST streams.
 	 */
-	if (drm_dp_is_branch(intel_dp->dpcd))
+	if (drm_dp_is_branch(intel_dp->dpcd) &&
+	    !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
 		return false;
 
 	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) &&
@@ -3119,8 +3125,8 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
 	return intel_vrr_possible(crtc_state);
 }
 
-static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
-				    struct intel_crtc_state *crtc_state)
+void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
+			     struct intel_crtc_state *crtc_state)
 {
 	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
 	const struct drm_display_mode *adjusted_mode =
@@ -3169,9 +3175,9 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 		as_sdp->coasting_vtotal = crtc_state->vrr.vmax;
 }
 
-static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
-				     struct intel_crtc_state *crtc_state,
-				     const struct drm_connector_state *conn_state)
+void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
+			      struct intel_crtc_state *crtc_state,
+			      const struct drm_connector_state *conn_state)
 {
 	struct drm_dp_vsc_sdp *vsc;
 
@@ -3228,7 +3234,7 @@ intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state)
 	return hdr_metadata->hdmi_metadata_type1.eotf == HDMI_EOTF_SMPTE_ST2084;
 }
 
-static void
+void
 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
 					    struct intel_crtc_state *crtc_state,
 					    const struct drm_connector_state *conn_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 04fae203bb69..7887ba63c7a4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -77,6 +77,8 @@ int intel_dp_compute_config(struct intel_atomic_state *state,
 			    struct intel_encoder *encoder,
 			    struct intel_crtc_state *pipe_config,
 			    struct drm_connector_state *conn_state);
+void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
+			     struct intel_crtc_state *crtc_state);
 bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state,
 			      bool dsc_enabled_on_crtc);
 void intel_dp_dsc_reset_config(struct intel_crtc_state *crtc_state);
@@ -130,6 +132,12 @@ bool intel_dp_joiner_needs_dsc(struct intel_display *display,
 bool intel_dp_has_joiner(struct intel_dp *intel_dp);
 bool intel_dp_needs_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
 				    const struct drm_connector_state *conn_state);
+void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
+			      struct intel_crtc_state *crtc_state,
+			      const struct drm_connector_state *conn_state);
+void intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
+						 struct intel_crtc_state *crtc_state,
+						 const struct drm_connector_state *conn_state);
 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
 			     const struct intel_crtc_state *crtc_state,
 			     const struct drm_connector_state *conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 3be1643f8d03..2b86a0a7a687 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -793,6 +793,9 @@ static int mst_stream_compute_config(struct intel_atomic_state *state,
 			bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
 
 	intel_vrr_compute_config(pipe_config, conn_state);
+	intel_dp_compute_as_sdp(intel_dp, pipe_config);
+	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
+	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
 
 	intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
 
@@ -1157,6 +1160,24 @@ static void mst_stream_post_disable(struct intel_atomic_state *state,
 	 * Power down mst path before disabling the port, otherwise we end
 	 * up getting interrupts from the sink upon detecting link loss.
 	 */
+	if (old_crtc_state->vrr.enable) {
+		u8 val;
+		ssize_t ret;
+
+		ret = drm_dp_mst_dpcd_read(&connector->mst.port->aux,
+					   DP_DOWNSPREAD_CTRL, &val, 1);
+		if (ret < 0) {
+			drm_dbg_kms(display->drm,
+				    "[CONNECTOR:%d:%s] Failed to read DP_DOWNSPREAD_CTRL: %zd\n",
+				    connector->base.base.id,
+				    connector->base.name, ret);
+		} else {
+			val &= ~DP_MSA_TIMING_PAR_IGNORE_EN;
+			drm_dp_mst_dpcd_write(&connector->mst.port->aux,
+					      DP_DOWNSPREAD_CTRL, &val, 1);
+		}
+	}
+
 	drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port,
 				     false);
 
@@ -1274,6 +1295,24 @@ static void mst_stream_pre_enable(struct intel_atomic_state *state,
 
 	drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port, true);
 
+	if (pipe_config->vrr.enable) {
+		u8 val;
+		ssize_t ret;
+
+		ret = drm_dp_mst_dpcd_read(&connector->mst.port->aux,
+					   DP_DOWNSPREAD_CTRL, &val, 1);
+		if (ret < 0) {
+			drm_dbg_kms(display->drm,
+				    "[CONNECTOR:%d:%s] Failed to read DP_DOWNSPREAD_CTRL: %zd\n",
+				    connector->base.base.id,
+				    connector->base.name, ret);
+		} else {
+			val |= DP_MSA_TIMING_PAR_IGNORE_EN;
+			drm_dp_mst_dpcd_write(&connector->mst.port->aux,
+					      DP_DOWNSPREAD_CTRL, &val, 1);
+		}
+	}
+
 	intel_dp_sink_enable_decompression(state, connector, pipe_config);
 
 	if (first_mst_stream) {
@@ -1397,6 +1436,8 @@ static void mst_stream_enable(struct intel_atomic_state *state,
 
 	intel_enable_transcoder(pipe_config);
 
+	intel_dp_set_infoframes(encoder, true, pipe_config, conn_state);
+
 	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, pipe_config) {
 		const struct intel_crtc_state *pipe_crtc_state =
 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
@@ -1451,6 +1492,15 @@ static int mst_connector_get_ddc_modes(struct drm_connector *_connector)
 
 	ret = intel_connector_update_modes(&connector->base, drm_edid);
 
+	if (HAS_VRR(display)) {
+		bool vrr_capable = intel_vrr_is_capable(connector);
+
+		drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
+			    connector->base.base.id, connector->base.name,
+			    str_yes_no(vrr_capable));
+		drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
+	}
+
 	drm_edid_free(drm_edid);
 
 	if (intel_dp_tunnel_uhbr_lanes_wa_setup(intel_dp)) {
@@ -1735,6 +1785,22 @@ static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,
 
 	intel_attach_force_audio_property(&connector->base);
 	intel_attach_broadcast_rgb_property(&connector->base);
+	/*
+	 * Reuse the colorspace property from the root SST connector.
+	 * MST connectors are created post device-registration so new
+	 * properties cannot be created here.
+	 */
+	if (intel_dp->attached_connector &&
+	    intel_dp->attached_connector->base.colorspace_property) {
+		connector->base.colorspace_property =
+			intel_dp->attached_connector->base.colorspace_property;
+		drm_object_attach_property(&connector->base.base,
+					   connector->base.colorspace_property,
+					   DRM_MODE_COLORIMETRY_DEFAULT);
+	}
+
+	if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
+		drm_connector_attach_hdr_output_metadata_property(&connector->base);
 
 	/*
 	 * Reuse the prop from the SST connector because we're
@@ -1745,6 +1811,34 @@ static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,
 	if (connector->base.max_bpc_property)
 		drm_connector_attach_max_bpc_property(&connector->base, 6, 12);
 
+	/*
+	 * Reuse the vrr_capable prop from the eDP connector (which is always
+	 * initialized during driver load before device registration), because
+	 * we're not allowed to create new props after device registration.
+	 */
+	/*
+	 * Reuse the vrr_capable property from the root intel_dp SST connector
+	 * which was created during driver load (before device registration).
+	 * MST connectors are created after device registration, so we cannot
+	 * create new properties here - we must attach the existing one.
+	 */
+	/*
+	 * Reuse the vrr_capable property from the root intel_dp SST connector
+	 * which was created during driver load (before device registration).
+	 * MST connectors are created after device registration, so we cannot
+	 * create new properties here - we must attach the existing one.
+	 * Also assign connector->vrr_capable_property so that
+	 * drm_connector_set_vrr_capable_property() can update the value.
+	 */
+	if (HAS_VRR(display) && intel_dp->attached_connector &&
+	    intel_dp->attached_connector->base.vrr_capable_property) {
+		connector->base.vrr_capable_property =
+			intel_dp->attached_connector->base.vrr_capable_property;
+		drm_object_attach_property(&connector->base.base,
+					   connector->base.vrr_capable_property,
+					   0);
+	}
+
 	return drm_connector_set_path_property(&connector->base, pathprop);
 }
 
@@ -1755,6 +1849,18 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
 	u8 dpcd_caps[DP_RECEIVER_CAP_SIZE];
 	struct drm_dp_desc desc;
 
+	/*
+	 * Read MSA timing par ignore capability from the sink's virtual DPCD.
+	 * This is independent of DSC support so read it before the DSC check.
+	 */
+	{
+		u8 mst_dpcd[DP_RECEIVER_CAP_SIZE];
+
+		if (drm_dp_read_dpcd_caps(&connector->mst.port->aux, mst_dpcd) == 0)
+			connector->dp.mst_msa_timing_par_ignore =
+				drm_dp_sink_can_do_video_without_timing_msa(mst_dpcd);
+	}
+
 	if (!connector->dp.dsc_decompression_aux)
 		return;
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 51e4f3309b8b..9737a19c1899 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -55,8 +55,19 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
 			return false;
 		fallthrough;
 	case DRM_MODE_CONNECTOR_DisplayPort:
-		if (connector->mst.dp)
-			return false;
+		if (connector->mst.dp) {
+			/*
+			 * Use cached MSA timing ignore capability from the DFP
+			 * sink's virtual DPCD, set during connector init in
+			 * intel_dp_mst_read_decompression_port_dsc_caps().
+			 * Avoid live sideband reads here as this function is
+			 * called from the atomic check path.
+			 */
+			if (!connector->dp.mst_msa_timing_par_ignore)
+				return false;
+
+			break;
+		}
 		intel_dp = intel_attached_dp(connector);
 		/*
 		 * Among non-MST DP branch devices, only an HDMI 2.1 sink connected
-- 
2.43.0

[PATCH v6] drm/i915/display: Enable VRR/HDR over MST

[Xiao Lu]

VRR over MST:
- Remove the hard MST block in intel_vrr_is_capable(); check the
  downstream port's MSA timing par ignore capability via REMOTE_DPCD_READ
  and cache it in connector->dp.mst_msa_timing_par_ignore to avoid hot
  path sideband round-trips.
- Read mst_msa_timing_par_ignore unconditionally from the sink's virtual
  DPCD before the DSC decompression check, so VRR works on MST sinks
  without DSC support.
- Attach vrr_capable property by reusing the root SST connector's existing
  property object (MST connectors are created post device-registration so
  new properties cannot be created).
- Update vrr_capable after EDID read; gate AS-SDP and
  DP_MSA_TIMING_PAR_IGNORE_EN writes on pipe_config->vrr.enable
  (actual state) not intel_vrr_is_capable() (capability); allow AS-SDP
  through MST hubs by excluding only non-MST branch devices (PCONs)
  from the branch device check.
- Reuse colorspace property from root SST connector for MST connectors
  to avoid WARN_ON from creating properties post device-registration.

HDR metadata over MST:
- Add VSC SDP, HDR metadata infoframe SDP and AS-SDP computation to
  mst_stream_compute_config() and enable their transmission in
  mst_stream_enable() and intel_ddi_update_pipe().
- Lift the hard 8bpc pipe_bpp cap and use the bpp capability from sink
  EDID for MST streams to allow 10bpc, relying on
  intel_dp_mst_atomic_check_link()'s BW retry loop to fall back if the
  link cannot fit it.

Signed-off-by: Xiao Lu <xiaolu.xie@intel.com>
---
 drivers/gpu/drm/display/drm_dp_mst_topology.c |  2 +
 drivers/gpu/drm/i915/display/intel_ddi.c      |  3 +
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_dp.c       | 36 ++++---
 drivers/gpu/drm/i915/display/intel_dp.h       |  8 ++
 drivers/gpu/drm/i915/display/intel_dp_mst.c   | 95 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vrr.c      | 15 ++-
 7 files changed, 143 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 7ce9e212770a..174fa62cb0dc 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -2164,6 +2164,7 @@ ssize_t drm_dp_mst_dpcd_read(struct drm_dp_aux *aux,
 	return drm_dp_send_dpcd_read(port->mgr, port,
 				     offset, size, buffer);
 }
+EXPORT_SYMBOL(drm_dp_mst_dpcd_read);
 
 /**
  * drm_dp_mst_dpcd_write() - write a series of bytes to the DPCD via sideband
@@ -2187,6 +2188,7 @@ ssize_t drm_dp_mst_dpcd_write(struct drm_dp_aux *aux,
 	return drm_dp_send_dpcd_write(port->mgr, port,
 				      offset, size, buffer);
 }
+EXPORT_SYMBOL(drm_dp_mst_dpcd_write);
 
 static int drm_dp_check_mstb_guid(struct drm_dp_mst_branch *mstb, guid_t *guid)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b8985e1e0a81..f345d9a2154d 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3651,6 +3651,9 @@ void intel_ddi_update_pipe(struct intel_atomic_state *state,
 		intel_ddi_update_pipe_dp(state, encoder, crtc_state,
 					 conn_state);
 
+	if (intel_encoder_is_mst(encoder))
+		intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
+
 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
 		intel_ddi_update_pipe_hdmi(encoder, crtc_state,
 					   conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b7cc361fd955..d09cf18f5376 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -564,6 +564,7 @@ struct intel_connector {
 		u8 dsc_hblank_expansion_quirk:1;
 		u8 dsc_throughput_quirk:1;
 		u8 dsc_decompression_enabled:1;
+		u8 mst_msa_timing_par_ignore:1; /* cached from MST virtual DPCD 0x007 */
 
 		struct {
 			struct {
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 113d767e62e9..4b196d26d27f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2682,15 +2682,18 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
 
 	limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
 	if (is_mst) {
+		struct intel_connector *mst_connector =
+			to_intel_connector(conn_state->connector);
+		int sink_bpc = mst_connector->base.display_info.bpc ?: 8;
+
 		/*
-		 * FIXME: If all the streams can't fit into the link with their
-		 * current pipe_bpp we should reduce pipe_bpp across the board
-		 * until things start to fit. Until then we limit to <= 8bpc
-		 * since that's what was hardcoded for all MST streams
-		 * previously. This hack should be removed once we have the
-		 * proper retry logic in place.
+		 * For MST streams, use the sink's EDID-reported color depth
+		 * as the max bpp, rather than the pipe_bpp from a previous
+		 * modeset (which may be stale) or a hardcoded 8bpc cap.
+		 * The BW retry loop in intel_dp_mst_atomic_check_link() will
+		 * reduce bpp if the aggregate link bandwidth is insufficient.
 		 */
-		limits->pipe.max_bpp = min(crtc_state->max_pipe_bpp, 24);
+		limits->pipe.max_bpp = sink_bpc * 3;
 	} else {
 		limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
 							respect_downstream_limits);
@@ -3107,9 +3110,12 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
 		return false;
 
 	/*
-	 * #TODO: Add AS SDP v1 support for PCONs (DP branch devices).
+	 * AS-SDP is not yet supported for PCONs (DP-to-HDMI converters).
+	 * MST hubs are also branch devices but do support AS-SDP forwarding
+	 * to downstream sinks; allow it for MST streams.
 	 */
-	if (drm_dp_is_branch(intel_dp->dpcd))
+	if (drm_dp_is_branch(intel_dp->dpcd) &&
+	    !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
 		return false;
 
 	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) &&
@@ -3119,8 +3125,8 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
 	return intel_vrr_possible(crtc_state);
 }
 
-static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
-				    struct intel_crtc_state *crtc_state)
+void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
+			     struct intel_crtc_state *crtc_state)
 {
 	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
 	const struct drm_display_mode *adjusted_mode =
@@ -3169,9 +3175,9 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
 		as_sdp->coasting_vtotal = crtc_state->vrr.vmax;
 }
 
-static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
-				     struct intel_crtc_state *crtc_state,
-				     const struct drm_connector_state *conn_state)
+void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
+			      struct intel_crtc_state *crtc_state,
+			      const struct drm_connector_state *conn_state)
 {
 	struct drm_dp_vsc_sdp *vsc;
 
@@ -3228,7 +3234,7 @@ intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state)
 	return hdr_metadata->hdmi_metadata_type1.eotf == HDMI_EOTF_SMPTE_ST2084;
 }
 
-static void
+void
 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
 					    struct intel_crtc_state *crtc_state,
 					    const struct drm_connector_state *conn_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 04fae203bb69..7887ba63c7a4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -77,6 +77,8 @@ int intel_dp_compute_config(struct intel_atomic_state *state,
 			    struct intel_encoder *encoder,
 			    struct intel_crtc_state *pipe_config,
 			    struct drm_connector_state *conn_state);
+void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
+			     struct intel_crtc_state *crtc_state);
 bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state,
 			      bool dsc_enabled_on_crtc);
 void intel_dp_dsc_reset_config(struct intel_crtc_state *crtc_state);
@@ -130,6 +132,12 @@ bool intel_dp_joiner_needs_dsc(struct intel_display *display,
 bool intel_dp_has_joiner(struct intel_dp *intel_dp);
 bool intel_dp_needs_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
 				    const struct drm_connector_state *conn_state);
+void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
+			      struct intel_crtc_state *crtc_state,
+			      const struct drm_connector_state *conn_state);
+void intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
+						 struct intel_crtc_state *crtc_state,
+						 const struct drm_connector_state *conn_state);
 void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
 			     const struct intel_crtc_state *crtc_state,
 			     const struct drm_connector_state *conn_state);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 3be1643f8d03..cbef63e94e2c 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -793,6 +793,9 @@ static int mst_stream_compute_config(struct intel_atomic_state *state,
 			bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
 
 	intel_vrr_compute_config(pipe_config, conn_state);
+	intel_dp_compute_as_sdp(intel_dp, pipe_config);
+	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
+	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
 
 	intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
 
@@ -1157,6 +1160,24 @@ static void mst_stream_post_disable(struct intel_atomic_state *state,
 	 * Power down mst path before disabling the port, otherwise we end
 	 * up getting interrupts from the sink upon detecting link loss.
 	 */
+	if (old_crtc_state->vrr.enable) {
+		u8 val;
+		ssize_t ret;
+
+		ret = drm_dp_mst_dpcd_read(&connector->mst.port->aux,
+					   DP_DOWNSPREAD_CTRL, &val, 1);
+		if (ret < 0) {
+			drm_dbg_kms(display->drm,
+				    "[CONNECTOR:%d:%s] Failed to read DP_DOWNSPREAD_CTRL: %zd\n",
+				    connector->base.base.id,
+				    connector->base.name, ret);
+		} else {
+			val &= ~DP_MSA_TIMING_PAR_IGNORE_EN;
+			drm_dp_mst_dpcd_write(&connector->mst.port->aux,
+					      DP_DOWNSPREAD_CTRL, &val, 1);
+		}
+	}
+
 	drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port,
 				     false);
 
@@ -1274,6 +1295,24 @@ static void mst_stream_pre_enable(struct intel_atomic_state *state,
 
 	drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port, true);
 
+	if (pipe_config->vrr.enable) {
+		u8 val;
+		ssize_t ret;
+
+		ret = drm_dp_mst_dpcd_read(&connector->mst.port->aux,
+					   DP_DOWNSPREAD_CTRL, &val, 1);
+		if (ret < 0) {
+			drm_dbg_kms(display->drm,
+				    "[CONNECTOR:%d:%s] Failed to read DP_DOWNSPREAD_CTRL: %zd\n",
+				    connector->base.base.id,
+				    connector->base.name, ret);
+		} else {
+			val |= DP_MSA_TIMING_PAR_IGNORE_EN;
+			drm_dp_mst_dpcd_write(&connector->mst.port->aux,
+					      DP_DOWNSPREAD_CTRL, &val, 1);
+		}
+	}
+
 	intel_dp_sink_enable_decompression(state, connector, pipe_config);
 
 	if (first_mst_stream) {
@@ -1397,6 +1436,8 @@ static void mst_stream_enable(struct intel_atomic_state *state,
 
 	intel_enable_transcoder(pipe_config);
 
+	intel_dp_set_infoframes(encoder, true, pipe_config, conn_state);
+
 	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, pipe_config) {
 		const struct intel_crtc_state *pipe_crtc_state =
 			intel_atomic_get_new_crtc_state(state, pipe_crtc);
@@ -1451,6 +1492,15 @@ static int mst_connector_get_ddc_modes(struct drm_connector *_connector)
 
 	ret = intel_connector_update_modes(&connector->base, drm_edid);
 
+	if (HAS_VRR(display)) {
+		bool vrr_capable = intel_vrr_is_capable(connector);
+
+		drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
+			    connector->base.base.id, connector->base.name,
+			    str_yes_no(vrr_capable));
+		drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
+	}
+
 	drm_edid_free(drm_edid);
 
 	if (intel_dp_tunnel_uhbr_lanes_wa_setup(intel_dp)) {
@@ -1735,6 +1785,22 @@ static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,
 
 	intel_attach_force_audio_property(&connector->base);
 	intel_attach_broadcast_rgb_property(&connector->base);
+	/*
+	 * Reuse the colorspace property from the root SST connector.
+	 * MST connectors are created post device-registration so new
+	 * properties cannot be created here.
+	 */
+	if (intel_dp->attached_connector &&
+	    intel_dp->attached_connector->base.colorspace_property) {
+		connector->base.colorspace_property =
+			intel_dp->attached_connector->base.colorspace_property;
+		drm_object_attach_property(&connector->base.base,
+					   connector->base.colorspace_property,
+					   DRM_MODE_COLORIMETRY_DEFAULT);
+	}
+
+	if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
+		drm_connector_attach_hdr_output_metadata_property(&connector->base);
 
 	/*
 	 * Reuse the prop from the SST connector because we're
@@ -1745,6 +1811,23 @@ static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,
 	if (connector->base.max_bpc_property)
 		drm_connector_attach_max_bpc_property(&connector->base, 6, 12);
 
+	/*
+	 * Reuse the vrr_capable property from the root intel_dp SST connector
+	 * which was created during driver load (before device registration).
+	 * MST connectors are created after device registration, so we cannot
+	 * create new properties here - we must attach the existing one.
+	 * Also assign connector->vrr_capable_property so that
+	 * drm_connector_set_vrr_capable_property() can update the value.
+	 */
+	if (HAS_VRR(display) && intel_dp->attached_connector &&
+	    intel_dp->attached_connector->base.vrr_capable_property) {
+		connector->base.vrr_capable_property =
+			intel_dp->attached_connector->base.vrr_capable_property;
+		drm_object_attach_property(&connector->base.base,
+					   connector->base.vrr_capable_property,
+					   0);
+	}
+
 	return drm_connector_set_path_property(&connector->base, pathprop);
 }
 
@@ -1755,6 +1838,18 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
 	u8 dpcd_caps[DP_RECEIVER_CAP_SIZE];
 	struct drm_dp_desc desc;
 
+	/*
+	 * Read MSA timing par ignore capability from the sink's virtual DPCD.
+	 * This is independent of DSC support so read it before the DSC check.
+	 */
+	{
+		u8 mst_dpcd[DP_RECEIVER_CAP_SIZE];
+
+		if (drm_dp_read_dpcd_caps(&connector->mst.port->aux, mst_dpcd) == 0)
+			connector->dp.mst_msa_timing_par_ignore =
+				drm_dp_sink_can_do_video_without_timing_msa(mst_dpcd);
+	}
+
 	if (!connector->dp.dsc_decompression_aux)
 		return;
 
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 51e4f3309b8b..9737a19c1899 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -55,8 +55,19 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
 			return false;
 		fallthrough;
 	case DRM_MODE_CONNECTOR_DisplayPort:
-		if (connector->mst.dp)
-			return false;
+		if (connector->mst.dp) {
+			/*
+			 * Use cached MSA timing ignore capability from the DFP
+			 * sink's virtual DPCD, set during connector init in
+			 * intel_dp_mst_read_decompression_port_dsc_caps().
+			 * Avoid live sideband reads here as this function is
+			 * called from the atomic check path.
+			 */
+			if (!connector->dp.mst_msa_timing_par_ignore)
+				return false;
+
+			break;
+		}
 		intel_dp = intel_attached_dp(connector);
 		/*
 		 * Among non-MST DP branch devices, only an HDMI 2.1 sink connected
-- 
2.43.0

Re: [PATCH v6] drm/i915/display: Enable VRR/HDR over MST

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] The patch exports and directly calls the low-level `drm_dp_mst_dpcd_read` and `drm_dp_mst_dpcd_write` functions instead of using the standard DPCD access APIs.
--

commit 79505a4fb76cee58bfa580901d6c993fd41628e1
Author: Xiao Lu <xiaolu.xie@intel.com>

drm/i915/display: Enable VRR/HDR over MST

This commit enables VRR and HDR metadata over MST. It reads the MSA timing
parameter ignore capability from the sink's virtual DPCD and updates the
VSC SDP, HDR metadata, and AS-SDP computations.

> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> @@ -2164,6 +2164,7 @@ ssize_t drm_dp_mst_dpcd_read(struct drm_dp_aux *aux,
>  	return drm_dp_send_dpcd_read(port->mgr, port,
>  				     offset, size, buffer);
>  }
> +EXPORT_SYMBOL(drm_dp_mst_dpcd_read);

[Severity: Low]
Is it necessary to export drm_dp_mst_dpcd_read directly to the core DRM
layer? The standard helpers like drm_dp_dpcd_read already check aux->is_remote
and route to the MST equivalents. Using the standard API preserves the
built-in drm_dp_dump_access debugging trace.

> @@ -2187,6 +2188,7 @@ ssize_t drm_dp_mst_dpcd_write(struct drm_dp_aux *aux,
>  	return drm_dp_send_dpcd_write(port->mgr, port,
>  				      offset, size, buffer);
>  }
> +EXPORT_SYMBOL(drm_dp_mst_dpcd_write);

[Severity: Low]
Similarly, does drm_dp_mst_dpcd_write need to be exported here, or could
we rely on the standard drm_dp_dpcd_write API instead?

> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c

[ ... ]

> @@ -1157,6 +1160,24 @@ static void mst_stream_post_disable(struct intel_atomic_state *state,
>  	 * Power down mst path before disabling the port, otherwise we end
>  	 * up getting interrupts from the sink upon detecting link loss.
>  	 */
> +	if (old_crtc_state->vrr.enable) {
> +		u8 val;
> +		ssize_t ret;
> +
> +		ret = drm_dp_mst_dpcd_read(&connector->mst.port->aux,
> +					   DP_DOWNSPREAD_CTRL, &val, 1);

[Severity: Low]
Can we use drm_dp_dpcd_read here in mst_stream_post_disable instead of
calling the low-level drm_dp_mst_dpcd_read function? Bypassing the standard
API skips the DPCD access debug tracing that is printed when DRM_UT_DP is
enabled, which can make MST debugging more difficult.

> +		if (ret < 0) {
> +			drm_dbg_kms(display->drm,
> +				    "[CONNECTOR:%d:%s] Failed to read DP_DOWNSPREAD_CTRL: %zd\n",
> +				    connector->base.base.id,
> +				    connector->base.name, ret);
> +		} else {
> +			val &= ~DP_MSA_TIMING_PAR_IGNORE_EN;
> +			drm_dp_mst_dpcd_write(&connector->mst.port->aux,
> +					      DP_DOWNSPREAD_CTRL, &val, 1);

[Severity: Low]
Does this also apply to the write operation? Calling drm_dp_dpcd_write
instead of drm_dp_mst_dpcd_write would ensure the sideband transactions are
logged consistently with the rest of the DPCD accesses.

[ ... ]

> @@ -1274,6 +1295,24 @@ static void mst_stream_pre_enable(struct intel_atomic_state *state,
>  
>  	drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port, true);
>  
> +	if (pipe_config->vrr.enable) {
> +		u8 val;
> +		ssize_t ret;
> +
> +		ret = drm_dp_mst_dpcd_read(&connector->mst.port->aux,
> +					   DP_DOWNSPREAD_CTRL, &val, 1);
> +		if (ret < 0) {
> +			drm_dbg_kms(display->drm,
> +				    "[CONNECTOR:%d:%s] Failed to read DP_DOWNSPREAD_CTRL: %zd\n",
> +				    connector->base.base.id,
> +				    connector->base.name, ret);
> +		} else {
> +			val |= DP_MSA_TIMING_PAR_IGNORE_EN;
> +			drm_dp_mst_dpcd_write(&connector->mst.port->aux,
> +					      DP_DOWNSPREAD_CTRL, &val, 1);

[Severity: Low]
For consistency, could the standard read and write helpers be used here in
mst_stream_pre_enable as well, avoiding the need to export the low-level
MST topology functions?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260902051206.264215-1-xiaolu.xie@intel.com?part=1

Re: [PATCH v5] drm/i915/display: Enable VRR/HDR over MST

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:
- [High] Sleeping in Atomic Context via DPCD reads/writes
- [Medium] Stale Cached Hardware State for MSA timing par ignore capability
- [Low] Duplicated block of comments for vrr_capable_property
--

commit 3a17e2d16d11206d1e9f75d12cdff011a2baaa07
Author: Xiao Lu <xiaolu.xie@intel.com>

drm/i915/display: Enable VRR/HDR over MST

This commit enables Variable Refresh Rate (VRR) and High Dynamic Range (HDR)
metadata over DisplayPort Multi-Stream Transport (MST). It removes the hard
MST block in the VRR capability check, utilizes DPCD reads to determine MSA
timing ignore capability, and manages related connector properties.

> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c

[ ... ]

> @@ -1157,6 +1160,24 @@ static void mst_stream_post_disable(struct intel_atomic_state *state,
>  	 * Power down mst path before disabling the port, otherwise we end
>  	 * up getting interrupts from the sink upon detecting link loss.
>  	 */
> +	if (old_crtc_state->vrr.enable) {
> +		u8 val;
> +		ssize_t ret;
> +
> +		ret = drm_dp_mst_dpcd_read(&connector->mst.port->aux,
> +					   DP_DOWNSPREAD_CTRL, &val, 1);

[Severity: High]
Encoder atomic callbacks like mst_stream_post_disable() execute in atomic
context where sleeping is forbidden. Does the new drm_dp_mst_dpcd_read()
function sleep?

It appears to rely on a call chain that can sleep:

drm_dp_mst_dpcd_read()
   drm_dp_send_dpcd_read()
      kzalloc_obj() // Uses implicit GFP_KERNEL allocations
      drm_dp_mst_wait_tx_reply() // Uses sleepable wait primitives

Will this cause a kernel splat (e.g., "BUG: sleeping function called from
invalid context") or system hang during a modeset?

[ ... ]

> @@ -1274,6 +1295,24 @@ static void mst_stream_pre_enable(struct intel_atomic_state *state,
>  
>  	drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port, true);
>  
> +	if (pipe_config->vrr.enable) {
> +		u8 val;
> +		ssize_t ret;
> +
> +		ret = drm_dp_mst_dpcd_read(&connector->mst.port->aux,
> +					   DP_DOWNSPREAD_CTRL, &val, 1);

[Severity: High]
Similarly, mst_stream_pre_enable() executes in atomic context. Does calling
drm_dp_mst_dpcd_read() here also violate the atomic context sleeping
prohibition?

[ ... ]

> @@ -1745,6 +1811,34 @@ static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,
>  	if (connector->base.max_bpc_property)
>  		drm_connector_attach_max_bpc_property(&connector->base, 6, 12);
>  
> +	/*
> +	 * Reuse the vrr_capable prop from the eDP connector (which is always
> +	 * initialized during driver load before device registration), because
> +	 * we're not allowed to create new props after device registration.
> +	 */
> +	/*
> +	 * Reuse the vrr_capable property from the root intel_dp SST connector
> +	 * which was created during driver load (before device registration).
> +	 * MST connectors are created after device registration, so we cannot
> +	 * create new properties here - we must attach the existing one.
> +	 */
> +	/*
> +	 * Reuse the vrr_capable property from the root intel_dp SST connector
> +	 * which was created during driver load (before device registration).
> +	 * MST connectors are created after device registration, so we cannot
> +	 * create new properties here - we must attach the existing one.
> +	 * Also assign connector->vrr_capable_property so that
> +	 * drm_connector_set_vrr_capable_property() can update the value.
> +	 */

[Severity: Low]
this isn't a bug, but you've duplicated this comment block multiple times.
Was this pasted by accident?

[ ... ]

> @@ -1755,6 +1849,18 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
>  	u8 dpcd_caps[DP_RECEIVER_CAP_SIZE];
>  	struct drm_dp_desc desc;
>  
> +	/*
> +	 * Read MSA timing par ignore capability from the sink's virtual DPCD.
> +	 * This is independent of DSC support so read it before the DSC check.
> +	 */
> +	{
> +		u8 mst_dpcd[DP_RECEIVER_CAP_SIZE];
> +
> +		if (drm_dp_read_dpcd_caps(&connector->mst.port->aux, mst_dpcd) == 0)
> +			connector->dp.mst_msa_timing_par_ignore =
> +				drm_dp_sink_can_do_video_without_timing_msa(mst_dpcd);
> +	}

[Severity: Medium]
Because intel_dp_mst_read_decompression_port_dsc_caps() is only called during
connector initialization, can this result in stale capabilities being cached?

If a user hot-swaps a downstream sink on an MST branch device, the MST
topology manager might reuse the existing connector without destroying it or
re-running its initialization callbacks.

Will connector->dp.mst_msa_timing_par_ignore retain the stale capability of
the previously connected monitor?

> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c

[ ... ]

> @@ -55,8 +55,19 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
>  			return false;
>  		fallthrough;
>  	case DRM_MODE_CONNECTOR_DisplayPort:
> -		if (connector->mst.dp)
> -			return false;
> +		if (connector->mst.dp) {
> +			/*
> +			 * Use cached MSA timing ignore capability from the DFP
> +			 * sink's virtual DPCD, set during connector init in
> +			 * intel_dp_mst_read_decompression_port_dsc_caps().
> +			 * Avoid live sideband reads here as this function is
> +			 * called from the atomic check path.
> +			 */
> +			if (!connector->dp.mst_msa_timing_par_ignore)
> +				return false;

[Severity: Medium]
As mentioned above, if the cached mst_msa_timing_par_ignore value becomes
stale due to a hotplug event, could intel_vrr_is_capable() mistakenly enable
or disable VRR functionality for the new monitor based on the old monitor's
capabilities?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260902050926.264000-1-xiaolu.xie@intel.com?part=1

✓ i915.CI.BAT: success for drm/i915/display: Enable VRR/HDR over MST (rev6)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3076 bytes --]

== Series Details ==

Series: drm/i915/display: Enable VRR/HDR over MST (rev6)
URL   : https://patchwork.freedesktop.org/series/173155/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_19069 -> Patchwork_173155v6
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/index.html

Participating hosts (37 -> 36)
------------------------------

  Missing    (1): bat-dg2-13 

Known issues
------------

  Here are the changes found in Patchwork_173155v6 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@ring_submission:
    - fi-cfl-8109u:       [PASS][1] -> [DMESG-WARN][2] ([i915#13735]) +80 other tests dmesg-warn
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/fi-cfl-8109u/igt@i915_selftest@live@ring_submission.html

  * igt@kms_flip@basic-flip-vs-dpms@d-hdmi-a1:
    - fi-tgl-1115g4:      [PASS][3] -> [ABORT][4] ([i915#16837] / [i915#16876] / [i915#16881]) +1 other test abort
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/fi-tgl-1115g4/igt@kms_flip@basic-flip-vs-dpms@d-hdmi-a1.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/fi-tgl-1115g4/igt@kms_flip@basic-flip-vs-dpms@d-hdmi-a1.html

  * igt@kms_pipe_crc_basic@read-crc:
    - fi-cfl-8109u:       [PASS][5] -> [DMESG-WARN][6] ([i915#13735] / [i915#15673]) +49 other tests dmesg-warn
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/fi-cfl-8109u/igt@kms_pipe_crc_basic@read-crc.html

  
#### Possible fixes ####

  * igt@kms_pm_rpm@basic-pci-d3-state:
    - fi-kbl-7567u:       [DMESG-WARN][7] ([i915#15673]) -> [PASS][8] +51 other tests pass
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/fi-kbl-7567u/igt@kms_pm_rpm@basic-pci-d3-state.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/fi-kbl-7567u/igt@kms_pm_rpm@basic-pci-d3-state.html

  
  [i915#13735]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13735
  [i915#15673]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15673
  [i915#16837]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16837
  [i915#16876]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16876
  [i915#16881]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16881


Build changes
-------------

  * Linux: CI_DRM_19069 -> Patchwork_173155v6

  CI-20190529: 20190529
  CI_DRM_19069: c53467440a5196138d2d6610e269a43b6b47bf6b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_9079: 9079
  Patchwork_173155v6: c53467440a5196138d2d6610e269a43b6b47bf6b @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/index.html

[-- Attachment #2: Type: text/html, Size: 3895 bytes --]

Re: [PATCH v6] drm/i915/display: Enable VRR/HDR over MST

[Jani Nikula]

On Wed, 02 Sep 2026, Xiao Lu <xiaolu.xie@intel.com> wrote:
> VRR over MST:
> - Remove the hard MST block in intel_vrr_is_capable(); check the
>   downstream port's MSA timing par ignore capability via REMOTE_DPCD_READ
>   and cache it in connector->dp.mst_msa_timing_par_ignore to avoid hot
>   path sideband round-trips.
> - Read mst_msa_timing_par_ignore unconditionally from the sink's virtual
>   DPCD before the DSC decompression check, so VRR works on MST sinks
>   without DSC support.
> - Attach vrr_capable property by reusing the root SST connector's existing
>   property object (MST connectors are created post device-registration so
>   new properties cannot be created).
> - Update vrr_capable after EDID read; gate AS-SDP and
>   DP_MSA_TIMING_PAR_IGNORE_EN writes on pipe_config->vrr.enable
>   (actual state) not intel_vrr_is_capable() (capability); allow AS-SDP
>   through MST hubs by excluding only non-MST branch devices (PCONs)
>   from the branch device check.
> - Reuse colorspace property from root SST connector for MST connectors
>   to avoid WARN_ON from creating properties post device-registration.
>
> HDR metadata over MST:
> - Add VSC SDP, HDR metadata infoframe SDP and AS-SDP computation to
>   mst_stream_compute_config() and enable their transmission in
>   mst_stream_enable() and intel_ddi_update_pipe().
> - Lift the hard 8bpc pipe_bpp cap and use the bpp capability from sink
>   EDID for MST streams to allow 10bpc, relying on
>   intel_dp_mst_atomic_check_link()'s BW retry loop to fall back if the
>   link cannot fit it.

What changed between versions?

Please don't send a bunch of versions of a patch in quick succession.

Truth is, nobody's going to spend time looking at it, because they think
it's in a state of flux and it'll be wasted effort.


BR,
Jani.

>
> Signed-off-by: Xiao Lu <xiaolu.xie@intel.com>
> ---
>  drivers/gpu/drm/display/drm_dp_mst_topology.c |  2 +
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  3 +
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c       | 36 ++++---
>  drivers/gpu/drm/i915/display/intel_dp.h       |  8 ++
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   | 95 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_vrr.c      | 15 ++-
>  7 files changed, 143 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> index 7ce9e212770a..174fa62cb0dc 100644
> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> @@ -2164,6 +2164,7 @@ ssize_t drm_dp_mst_dpcd_read(struct drm_dp_aux *aux,
>  	return drm_dp_send_dpcd_read(port->mgr, port,
>  				     offset, size, buffer);
>  }
> +EXPORT_SYMBOL(drm_dp_mst_dpcd_read);
>  
>  /**
>   * drm_dp_mst_dpcd_write() - write a series of bytes to the DPCD via sideband
> @@ -2187,6 +2188,7 @@ ssize_t drm_dp_mst_dpcd_write(struct drm_dp_aux *aux,
>  	return drm_dp_send_dpcd_write(port->mgr, port,
>  				      offset, size, buffer);
>  }
> +EXPORT_SYMBOL(drm_dp_mst_dpcd_write);
>  
>  static int drm_dp_check_mstb_guid(struct drm_dp_mst_branch *mstb, guid_t *guid)
>  {
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index b8985e1e0a81..f345d9a2154d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3651,6 +3651,9 @@ void intel_ddi_update_pipe(struct intel_atomic_state *state,
>  		intel_ddi_update_pipe_dp(state, encoder, crtc_state,
>  					 conn_state);
>  
> +	if (intel_encoder_is_mst(encoder))
> +		intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> +
>  	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
>  		intel_ddi_update_pipe_hdmi(encoder, crtc_state,
>  					   conn_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b7cc361fd955..d09cf18f5376 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -564,6 +564,7 @@ struct intel_connector {
>  		u8 dsc_hblank_expansion_quirk:1;
>  		u8 dsc_throughput_quirk:1;
>  		u8 dsc_decompression_enabled:1;
> +		u8 mst_msa_timing_par_ignore:1; /* cached from MST virtual DPCD 0x007 */
>  
>  		struct {
>  			struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 113d767e62e9..4b196d26d27f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2682,15 +2682,18 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
>  
>  	limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
>  	if (is_mst) {
> +		struct intel_connector *mst_connector =
> +			to_intel_connector(conn_state->connector);
> +		int sink_bpc = mst_connector->base.display_info.bpc ?: 8;
> +
>  		/*
> -		 * FIXME: If all the streams can't fit into the link with their
> -		 * current pipe_bpp we should reduce pipe_bpp across the board
> -		 * until things start to fit. Until then we limit to <= 8bpc
> -		 * since that's what was hardcoded for all MST streams
> -		 * previously. This hack should be removed once we have the
> -		 * proper retry logic in place.
> +		 * For MST streams, use the sink's EDID-reported color depth
> +		 * as the max bpp, rather than the pipe_bpp from a previous
> +		 * modeset (which may be stale) or a hardcoded 8bpc cap.
> +		 * The BW retry loop in intel_dp_mst_atomic_check_link() will
> +		 * reduce bpp if the aggregate link bandwidth is insufficient.
>  		 */
> -		limits->pipe.max_bpp = min(crtc_state->max_pipe_bpp, 24);
> +		limits->pipe.max_bpp = sink_bpc * 3;
>  	} else {
>  		limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
>  							respect_downstream_limits);
> @@ -3107,9 +3110,12 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
>  		return false;
>  
>  	/*
> -	 * #TODO: Add AS SDP v1 support for PCONs (DP branch devices).
> +	 * AS-SDP is not yet supported for PCONs (DP-to-HDMI converters).
> +	 * MST hubs are also branch devices but do support AS-SDP forwarding
> +	 * to downstream sinks; allow it for MST streams.
>  	 */
> -	if (drm_dp_is_branch(intel_dp->dpcd))
> +	if (drm_dp_is_branch(intel_dp->dpcd) &&
> +	    !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
>  		return false;
>  
>  	if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) &&
> @@ -3119,8 +3125,8 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
>  	return intel_vrr_possible(crtc_state);
>  }
>  
> -static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> -				    struct intel_crtc_state *crtc_state)
> +void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> +			     struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
>  	const struct drm_display_mode *adjusted_mode =
> @@ -3169,9 +3175,9 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>  		as_sdp->coasting_vtotal = crtc_state->vrr.vmax;
>  }
>  
> -static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
> -				     struct intel_crtc_state *crtc_state,
> -				     const struct drm_connector_state *conn_state)
> +void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
> +			      struct intel_crtc_state *crtc_state,
> +			      const struct drm_connector_state *conn_state)
>  {
>  	struct drm_dp_vsc_sdp *vsc;
>  
> @@ -3228,7 +3234,7 @@ intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state)
>  	return hdr_metadata->hdmi_metadata_type1.eotf == HDMI_EOTF_SMPTE_ST2084;
>  }
>  
> -static void
> +void
>  intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
>  					    struct intel_crtc_state *crtc_state,
>  					    const struct drm_connector_state *conn_state)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 04fae203bb69..7887ba63c7a4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -77,6 +77,8 @@ int intel_dp_compute_config(struct intel_atomic_state *state,
>  			    struct intel_encoder *encoder,
>  			    struct intel_crtc_state *pipe_config,
>  			    struct drm_connector_state *conn_state);
> +void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> +			     struct intel_crtc_state *crtc_state);
>  bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state,
>  			      bool dsc_enabled_on_crtc);
>  void intel_dp_dsc_reset_config(struct intel_crtc_state *crtc_state);
> @@ -130,6 +132,12 @@ bool intel_dp_joiner_needs_dsc(struct intel_display *display,
>  bool intel_dp_has_joiner(struct intel_dp *intel_dp);
>  bool intel_dp_needs_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
>  				    const struct drm_connector_state *conn_state);
> +void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
> +			      struct intel_crtc_state *crtc_state,
> +			      const struct drm_connector_state *conn_state);
> +void intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
> +						 struct intel_crtc_state *crtc_state,
> +						 const struct drm_connector_state *conn_state);
>  void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
>  			     const struct intel_crtc_state *crtc_state,
>  			     const struct drm_connector_state *conn_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 3be1643f8d03..cbef63e94e2c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -793,6 +793,9 @@ static int mst_stream_compute_config(struct intel_atomic_state *state,
>  			bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
>  
>  	intel_vrr_compute_config(pipe_config, conn_state);
> +	intel_dp_compute_as_sdp(intel_dp, pipe_config);
> +	intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
> +	intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
>  
>  	intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
>  
> @@ -1157,6 +1160,24 @@ static void mst_stream_post_disable(struct intel_atomic_state *state,
>  	 * Power down mst path before disabling the port, otherwise we end
>  	 * up getting interrupts from the sink upon detecting link loss.
>  	 */
> +	if (old_crtc_state->vrr.enable) {
> +		u8 val;
> +		ssize_t ret;
> +
> +		ret = drm_dp_mst_dpcd_read(&connector->mst.port->aux,
> +					   DP_DOWNSPREAD_CTRL, &val, 1);
> +		if (ret < 0) {
> +			drm_dbg_kms(display->drm,
> +				    "[CONNECTOR:%d:%s] Failed to read DP_DOWNSPREAD_CTRL: %zd\n",
> +				    connector->base.base.id,
> +				    connector->base.name, ret);
> +		} else {
> +			val &= ~DP_MSA_TIMING_PAR_IGNORE_EN;
> +			drm_dp_mst_dpcd_write(&connector->mst.port->aux,
> +					      DP_DOWNSPREAD_CTRL, &val, 1);
> +		}
> +	}
> +
>  	drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port,
>  				     false);
>  
> @@ -1274,6 +1295,24 @@ static void mst_stream_pre_enable(struct intel_atomic_state *state,
>  
>  	drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port, true);
>  
> +	if (pipe_config->vrr.enable) {
> +		u8 val;
> +		ssize_t ret;
> +
> +		ret = drm_dp_mst_dpcd_read(&connector->mst.port->aux,
> +					   DP_DOWNSPREAD_CTRL, &val, 1);
> +		if (ret < 0) {
> +			drm_dbg_kms(display->drm,
> +				    "[CONNECTOR:%d:%s] Failed to read DP_DOWNSPREAD_CTRL: %zd\n",
> +				    connector->base.base.id,
> +				    connector->base.name, ret);
> +		} else {
> +			val |= DP_MSA_TIMING_PAR_IGNORE_EN;
> +			drm_dp_mst_dpcd_write(&connector->mst.port->aux,
> +					      DP_DOWNSPREAD_CTRL, &val, 1);
> +		}
> +	}
> +
>  	intel_dp_sink_enable_decompression(state, connector, pipe_config);
>  
>  	if (first_mst_stream) {
> @@ -1397,6 +1436,8 @@ static void mst_stream_enable(struct intel_atomic_state *state,
>  
>  	intel_enable_transcoder(pipe_config);
>  
> +	intel_dp_set_infoframes(encoder, true, pipe_config, conn_state);
> +
>  	for_each_pipe_crtc_modeset_enable(display, pipe_crtc, pipe_config) {
>  		const struct intel_crtc_state *pipe_crtc_state =
>  			intel_atomic_get_new_crtc_state(state, pipe_crtc);
> @@ -1451,6 +1492,15 @@ static int mst_connector_get_ddc_modes(struct drm_connector *_connector)
>  
>  	ret = intel_connector_update_modes(&connector->base, drm_edid);
>  
> +	if (HAS_VRR(display)) {
> +		bool vrr_capable = intel_vrr_is_capable(connector);
> +
> +		drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
> +			    connector->base.base.id, connector->base.name,
> +			    str_yes_no(vrr_capable));
> +		drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
> +	}
> +
>  	drm_edid_free(drm_edid);
>  
>  	if (intel_dp_tunnel_uhbr_lanes_wa_setup(intel_dp)) {
> @@ -1735,6 +1785,22 @@ static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,
>  
>  	intel_attach_force_audio_property(&connector->base);
>  	intel_attach_broadcast_rgb_property(&connector->base);
> +	/*
> +	 * Reuse the colorspace property from the root SST connector.
> +	 * MST connectors are created post device-registration so new
> +	 * properties cannot be created here.
> +	 */
> +	if (intel_dp->attached_connector &&
> +	    intel_dp->attached_connector->base.colorspace_property) {
> +		connector->base.colorspace_property =
> +			intel_dp->attached_connector->base.colorspace_property;
> +		drm_object_attach_property(&connector->base.base,
> +					   connector->base.colorspace_property,
> +					   DRM_MODE_COLORIMETRY_DEFAULT);
> +	}
> +
> +	if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
> +		drm_connector_attach_hdr_output_metadata_property(&connector->base);
>  
>  	/*
>  	 * Reuse the prop from the SST connector because we're
> @@ -1745,6 +1811,23 @@ static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,
>  	if (connector->base.max_bpc_property)
>  		drm_connector_attach_max_bpc_property(&connector->base, 6, 12);
>  
> +	/*
> +	 * Reuse the vrr_capable property from the root intel_dp SST connector
> +	 * which was created during driver load (before device registration).
> +	 * MST connectors are created after device registration, so we cannot
> +	 * create new properties here - we must attach the existing one.
> +	 * Also assign connector->vrr_capable_property so that
> +	 * drm_connector_set_vrr_capable_property() can update the value.
> +	 */
> +	if (HAS_VRR(display) && intel_dp->attached_connector &&
> +	    intel_dp->attached_connector->base.vrr_capable_property) {
> +		connector->base.vrr_capable_property =
> +			intel_dp->attached_connector->base.vrr_capable_property;
> +		drm_object_attach_property(&connector->base.base,
> +					   connector->base.vrr_capable_property,
> +					   0);
> +	}
> +
>  	return drm_connector_set_path_property(&connector->base, pathprop);
>  }
>  
> @@ -1755,6 +1838,18 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
>  	u8 dpcd_caps[DP_RECEIVER_CAP_SIZE];
>  	struct drm_dp_desc desc;
>  
> +	/*
> +	 * Read MSA timing par ignore capability from the sink's virtual DPCD.
> +	 * This is independent of DSC support so read it before the DSC check.
> +	 */
> +	{
> +		u8 mst_dpcd[DP_RECEIVER_CAP_SIZE];
> +
> +		if (drm_dp_read_dpcd_caps(&connector->mst.port->aux, mst_dpcd) == 0)
> +			connector->dp.mst_msa_timing_par_ignore =
> +				drm_dp_sink_can_do_video_without_timing_msa(mst_dpcd);
> +	}
> +
>  	if (!connector->dp.dsc_decompression_aux)
>  		return;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 51e4f3309b8b..9737a19c1899 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -55,8 +55,19 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
>  			return false;
>  		fallthrough;
>  	case DRM_MODE_CONNECTOR_DisplayPort:
> -		if (connector->mst.dp)
> -			return false;
> +		if (connector->mst.dp) {
> +			/*
> +			 * Use cached MSA timing ignore capability from the DFP
> +			 * sink's virtual DPCD, set during connector init in
> +			 * intel_dp_mst_read_decompression_port_dsc_caps().
> +			 * Avoid live sideband reads here as this function is
> +			 * called from the atomic check path.
> +			 */
> +			if (!connector->dp.mst_msa_timing_par_ignore)
> +				return false;
> +
> +			break;
> +		}
>  		intel_dp = intel_attached_dp(connector);
>  		/*
>  		 * Among non-MST DP branch devices, only an HDMI 2.1 sink connected

-- 
Jani Nikula, Intel

Re: [PATCH v6] drm/i915/display: Enable VRR/HDR over MST

[Xie, Xiaolu]

[-- Attachment #1: Type: text/plain, Size: 20488 bytes --]

Hi Jani,

Apologies for the rapid succession of versions. The repeated revisions were primarily to address CI.Checkpatch formatting warnings and i915.CI.BAT WARN_ON failures. The core logic of the patch has not changed. v6 is the final version for this patch. Happy to wait for your review at your convenience.
Thank you for the feedback.

Best regards
________________________________
From: Jani Nikula <jani.nikula@linux.intel.com>
Sent: Wednesday, September 2, 2026 4:37 PM
To: Xie, Xiaolu <xiaolu.xie@intel.com>; intel-gfx@lists.freedesktop.org <intel-gfx@lists.freedesktop.org>
Cc: ville.syrjala@linux.intel.com <ville.syrjala@linux.intel.com>; Deak, Imre <imre.deak@intel.com>; Xie, Xiaolu <xiaolu.xie@intel.com>
Subject: Re: [PATCH v6] drm/i915/display: Enable VRR/HDR over MST

On Wed, 02 Sep 2026, Xiao Lu <xiaolu.xie@intel.com> wrote:
> VRR over MST:
> - Remove the hard MST block in intel_vrr_is_capable(); check the
>   downstream port's MSA timing par ignore capability via REMOTE_DPCD_READ
>   and cache it in connector->dp.mst_msa_timing_par_ignore to avoid hot
>   path sideband round-trips.
> - Read mst_msa_timing_par_ignore unconditionally from the sink's virtual
>   DPCD before the DSC decompression check, so VRR works on MST sinks
>   without DSC support.
> - Attach vrr_capable property by reusing the root SST connector's existing
>   property object (MST connectors are created post device-registration so
>   new properties cannot be created).
> - Update vrr_capable after EDID read; gate AS-SDP and
>   DP_MSA_TIMING_PAR_IGNORE_EN writes on pipe_config->vrr.enable
>   (actual state) not intel_vrr_is_capable() (capability); allow AS-SDP
>   through MST hubs by excluding only non-MST branch devices (PCONs)
>   from the branch device check.
> - Reuse colorspace property from root SST connector for MST connectors
>   to avoid WARN_ON from creating properties post device-registration.
>
> HDR metadata over MST:
> - Add VSC SDP, HDR metadata infoframe SDP and AS-SDP computation to
>   mst_stream_compute_config() and enable their transmission in
>   mst_stream_enable() and intel_ddi_update_pipe().
> - Lift the hard 8bpc pipe_bpp cap and use the bpp capability from sink
>   EDID for MST streams to allow 10bpc, relying on
>   intel_dp_mst_atomic_check_link()'s BW retry loop to fall back if the
>   link cannot fit it.

What changed between versions?

Please don't send a bunch of versions of a patch in quick succession.

Truth is, nobody's going to spend time looking at it, because they think
it's in a state of flux and it'll be wasted effort.


BR,
Jani.

>
> Signed-off-by: Xiao Lu <xiaolu.xie@intel.com>
> ---
>  drivers/gpu/drm/display/drm_dp_mst_topology.c |  2 +
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  3 +
>  .../drm/i915/display/intel_display_types.h    |  1 +
>  drivers/gpu/drm/i915/display/intel_dp.c       | 36 ++++---
>  drivers/gpu/drm/i915/display/intel_dp.h       |  8 ++
>  drivers/gpu/drm/i915/display/intel_dp_mst.c   | 95 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_vrr.c      | 15 ++-
>  7 files changed, 143 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> index 7ce9e212770a..174fa62cb0dc 100644
> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> @@ -2164,6 +2164,7 @@ ssize_t drm_dp_mst_dpcd_read(struct drm_dp_aux *aux,
>        return drm_dp_send_dpcd_read(port->mgr, port,
>                                     offset, size, buffer);
>  }
> +EXPORT_SYMBOL(drm_dp_mst_dpcd_read);
>
>  /**
>   * drm_dp_mst_dpcd_write() - write a series of bytes to the DPCD via sideband
> @@ -2187,6 +2188,7 @@ ssize_t drm_dp_mst_dpcd_write(struct drm_dp_aux *aux,
>        return drm_dp_send_dpcd_write(port->mgr, port,
>                                      offset, size, buffer);
>  }
> +EXPORT_SYMBOL(drm_dp_mst_dpcd_write);
>
>  static int drm_dp_check_mstb_guid(struct drm_dp_mst_branch *mstb, guid_t *guid)
>  {
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index b8985e1e0a81..f345d9a2154d 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -3651,6 +3651,9 @@ void intel_ddi_update_pipe(struct intel_atomic_state *state,
>                intel_ddi_update_pipe_dp(state, encoder, crtc_state,
>                                         conn_state);
>
> +     if (intel_encoder_is_mst(encoder))
> +             intel_dp_set_infoframes(encoder, true, crtc_state, conn_state);
> +
>        if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
>                intel_ddi_update_pipe_hdmi(encoder, crtc_state,
>                                           conn_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b7cc361fd955..d09cf18f5376 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -564,6 +564,7 @@ struct intel_connector {
>                u8 dsc_hblank_expansion_quirk:1;
>                u8 dsc_throughput_quirk:1;
>                u8 dsc_decompression_enabled:1;
> +             u8 mst_msa_timing_par_ignore:1; /* cached from MST virtual DPCD 0x007 */
>
>                struct {
>                        struct {
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 113d767e62e9..4b196d26d27f 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2682,15 +2682,18 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
>
>        limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
>        if (is_mst) {
> +             struct intel_connector *mst_connector =
> +                     to_intel_connector(conn_state->connector);
> +             int sink_bpc = mst_connector->base.display_info.bpc ?: 8;
> +
>                /*
> -              * FIXME: If all the streams can't fit into the link with their
> -              * current pipe_bpp we should reduce pipe_bpp across the board
> -              * until things start to fit. Until then we limit to <= 8bpc
> -              * since that's what was hardcoded for all MST streams
> -              * previously. This hack should be removed once we have the
> -              * proper retry logic in place.
> +              * For MST streams, use the sink's EDID-reported color depth
> +              * as the max bpp, rather than the pipe_bpp from a previous
> +              * modeset (which may be stale) or a hardcoded 8bpc cap.
> +              * The BW retry loop in intel_dp_mst_atomic_check_link() will
> +              * reduce bpp if the aggregate link bandwidth is insufficient.
>                 */
> -             limits->pipe.max_bpp = min(crtc_state->max_pipe_bpp, 24);
> +             limits->pipe.max_bpp = sink_bpc * 3;
>        } else {
>                limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
>                                                        respect_downstream_limits);
> @@ -3107,9 +3110,12 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
>                return false;
>
>        /*
> -      * #TODO: Add AS SDP v1 support for PCONs (DP branch devices).
> +      * AS-SDP is not yet supported for PCONs (DP-to-HDMI converters).
> +      * MST hubs are also branch devices but do support AS-SDP forwarding
> +      * to downstream sinks; allow it for MST streams.
>         */
> -     if (drm_dp_is_branch(intel_dp->dpcd))
> +     if (drm_dp_is_branch(intel_dp->dpcd) &&
> +         !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST))
>                return false;
>
>        if (intel_psr_needs_alpm_aux_less(intel_dp, crtc_state) &&
> @@ -3119,8 +3125,8 @@ static bool intel_dp_needs_as_sdp(struct intel_dp *intel_dp,
>        return intel_vrr_possible(crtc_state);
>  }
>
> -static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> -                                 struct intel_crtc_state *crtc_state)
> +void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> +                          struct intel_crtc_state *crtc_state)
>  {
>        struct drm_dp_as_sdp *as_sdp = &crtc_state->infoframes.as_sdp;
>        const struct drm_display_mode *adjusted_mode =
> @@ -3169,9 +3175,9 @@ static void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
>                as_sdp->coasting_vtotal = crtc_state->vrr.vmax;
>  }
>
> -static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
> -                                  struct intel_crtc_state *crtc_state,
> -                                  const struct drm_connector_state *conn_state)
> +void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
> +                           struct intel_crtc_state *crtc_state,
> +                           const struct drm_connector_state *conn_state)
>  {
>        struct drm_dp_vsc_sdp *vsc;
>
> @@ -3228,7 +3234,7 @@ intel_dp_in_hdr_mode(const struct drm_connector_state *conn_state)
>        return hdr_metadata->hdmi_metadata_type1.eotf == HDMI_EOTF_SMPTE_ST2084;
>  }
>
> -static void
> +void
>  intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
>                                            struct intel_crtc_state *crtc_state,
>                                            const struct drm_connector_state *conn_state)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 04fae203bb69..7887ba63c7a4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -77,6 +77,8 @@ int intel_dp_compute_config(struct intel_atomic_state *state,
>                            struct intel_encoder *encoder,
>                            struct intel_crtc_state *pipe_config,
>                            struct drm_connector_state *conn_state);
> +void intel_dp_compute_as_sdp(struct intel_dp *intel_dp,
> +                          struct intel_crtc_state *crtc_state);
>  bool intel_dp_needs_8b10b_fec(const struct intel_crtc_state *crtc_state,
>                              bool dsc_enabled_on_crtc);
>  void intel_dp_dsc_reset_config(struct intel_crtc_state *crtc_state);
> @@ -130,6 +132,12 @@ bool intel_dp_joiner_needs_dsc(struct intel_display *display,
>  bool intel_dp_has_joiner(struct intel_dp *intel_dp);
>  bool intel_dp_needs_vsc_colorimetry(const struct intel_crtc_state *crtc_state,
>                                    const struct drm_connector_state *conn_state);
> +void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp,
> +                           struct intel_crtc_state *crtc_state,
> +                           const struct drm_connector_state *conn_state);
> +void intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp,
> +                                              struct intel_crtc_state *crtc_state,
> +                                              const struct drm_connector_state *conn_state);
>  void intel_dp_set_infoframes(struct intel_encoder *encoder, bool enable,
>                             const struct intel_crtc_state *crtc_state,
>                             const struct drm_connector_state *conn_state);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 3be1643f8d03..cbef63e94e2c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -793,6 +793,9 @@ static int mst_stream_compute_config(struct intel_atomic_state *state,
>                        bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
>
>        intel_vrr_compute_config(pipe_config, conn_state);
> +     intel_dp_compute_as_sdp(intel_dp, pipe_config);
> +     intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state);
> +     intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state);
>
>        intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
>
> @@ -1157,6 +1160,24 @@ static void mst_stream_post_disable(struct intel_atomic_state *state,
>         * Power down mst path before disabling the port, otherwise we end
>         * up getting interrupts from the sink upon detecting link loss.
>         */
> +     if (old_crtc_state->vrr.enable) {
> +             u8 val;
> +             ssize_t ret;
> +
> +             ret = drm_dp_mst_dpcd_read(&connector->mst.port->aux,
> +                                        DP_DOWNSPREAD_CTRL, &val, 1);
> +             if (ret < 0) {
> +                     drm_dbg_kms(display->drm,
> +                                 "[CONNECTOR:%d:%s] Failed to read DP_DOWNSPREAD_CTRL: %zd\n",
> +                                 connector->base.base.id,
> +                                 connector->base.name, ret);
> +             } else {
> +                     val &= ~DP_MSA_TIMING_PAR_IGNORE_EN;
> +                     drm_dp_mst_dpcd_write(&connector->mst.port->aux,
> +                                           DP_DOWNSPREAD_CTRL, &val, 1);
> +             }
> +     }
> +
>        drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port,
>                                     false);
>
> @@ -1274,6 +1295,24 @@ static void mst_stream_pre_enable(struct intel_atomic_state *state,
>
>        drm_dp_send_power_updown_phy(&intel_dp->mst.mgr, connector->mst.port, true);
>
> +     if (pipe_config->vrr.enable) {
> +             u8 val;
> +             ssize_t ret;
> +
> +             ret = drm_dp_mst_dpcd_read(&connector->mst.port->aux,
> +                                        DP_DOWNSPREAD_CTRL, &val, 1);
> +             if (ret < 0) {
> +                     drm_dbg_kms(display->drm,
> +                                 "[CONNECTOR:%d:%s] Failed to read DP_DOWNSPREAD_CTRL: %zd\n",
> +                                 connector->base.base.id,
> +                                 connector->base.name, ret);
> +             } else {
> +                     val |= DP_MSA_TIMING_PAR_IGNORE_EN;
> +                     drm_dp_mst_dpcd_write(&connector->mst.port->aux,
> +                                           DP_DOWNSPREAD_CTRL, &val, 1);
> +             }
> +     }
> +
>        intel_dp_sink_enable_decompression(state, connector, pipe_config);
>
>        if (first_mst_stream) {
> @@ -1397,6 +1436,8 @@ static void mst_stream_enable(struct intel_atomic_state *state,
>
>        intel_enable_transcoder(pipe_config);
>
> +     intel_dp_set_infoframes(encoder, true, pipe_config, conn_state);
> +
>        for_each_pipe_crtc_modeset_enable(display, pipe_crtc, pipe_config) {
>                const struct intel_crtc_state *pipe_crtc_state =
>                        intel_atomic_get_new_crtc_state(state, pipe_crtc);
> @@ -1451,6 +1492,15 @@ static int mst_connector_get_ddc_modes(struct drm_connector *_connector)
>
>        ret = intel_connector_update_modes(&connector->base, drm_edid);
>
> +     if (HAS_VRR(display)) {
> +             bool vrr_capable = intel_vrr_is_capable(connector);
> +
> +             drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] VRR capable: %s\n",
> +                         connector->base.base.id, connector->base.name,
> +                         str_yes_no(vrr_capable));
> +             drm_connector_set_vrr_capable_property(&connector->base, vrr_capable);
> +     }
> +
>        drm_edid_free(drm_edid);
>
>        if (intel_dp_tunnel_uhbr_lanes_wa_setup(intel_dp)) {
> @@ -1735,6 +1785,22 @@ static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,
>
>        intel_attach_force_audio_property(&connector->base);
>        intel_attach_broadcast_rgb_property(&connector->base);
> +     /*
> +      * Reuse the colorspace property from the root SST connector.
> +      * MST connectors are created post device-registration so new
> +      * properties cannot be created here.
> +      */
> +     if (intel_dp->attached_connector &&
> +         intel_dp->attached_connector->base.colorspace_property) {
> +             connector->base.colorspace_property =
> +                     intel_dp->attached_connector->base.colorspace_property;
> +             drm_object_attach_property(&connector->base.base,
> +                                        connector->base.colorspace_property,
> +                                        DRM_MODE_COLORIMETRY_DEFAULT);
> +     }
> +
> +     if (intel_dp_has_gamut_metadata_dip(&dp_to_dig_port(intel_dp)->base))
> +             drm_connector_attach_hdr_output_metadata_property(&connector->base);
>
>        /*
>         * Reuse the prop from the SST connector because we're
> @@ -1745,6 +1811,23 @@ static int mst_topology_add_connector_properties(struct intel_dp *intel_dp,
>        if (connector->base.max_bpc_property)
>                drm_connector_attach_max_bpc_property(&connector->base, 6, 12);
>
> +     /*
> +      * Reuse the vrr_capable property from the root intel_dp SST connector
> +      * which was created during driver load (before device registration).
> +      * MST connectors are created after device registration, so we cannot
> +      * create new properties here - we must attach the existing one.
> +      * Also assign connector->vrr_capable_property so that
> +      * drm_connector_set_vrr_capable_property() can update the value.
> +      */
> +     if (HAS_VRR(display) && intel_dp->attached_connector &&
> +         intel_dp->attached_connector->base.vrr_capable_property) {
> +             connector->base.vrr_capable_property =
> +                     intel_dp->attached_connector->base.vrr_capable_property;
> +             drm_object_attach_property(&connector->base.base,
> +                                        connector->base.vrr_capable_property,
> +                                        0);
> +     }
> +
>        return drm_connector_set_path_property(&connector->base, pathprop);
>  }
>
> @@ -1755,6 +1838,18 @@ intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
>        u8 dpcd_caps[DP_RECEIVER_CAP_SIZE];
>        struct drm_dp_desc desc;
>
> +     /*
> +      * Read MSA timing par ignore capability from the sink's virtual DPCD.
> +      * This is independent of DSC support so read it before the DSC check.
> +      */
> +     {
> +             u8 mst_dpcd[DP_RECEIVER_CAP_SIZE];
> +
> +             if (drm_dp_read_dpcd_caps(&connector->mst.port->aux, mst_dpcd) == 0)
> +                     connector->dp.mst_msa_timing_par_ignore =
> +                             drm_dp_sink_can_do_video_without_timing_msa(mst_dpcd);
> +     }
> +
>        if (!connector->dp.dsc_decompression_aux)
>                return;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 51e4f3309b8b..9737a19c1899 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -55,8 +55,19 @@ bool intel_vrr_is_capable(struct intel_connector *connector)
>                        return false;
>                fallthrough;
>        case DRM_MODE_CONNECTOR_DisplayPort:
> -             if (connector->mst.dp)
> -                     return false;
> +             if (connector->mst.dp) {
> +                     /*
> +                      * Use cached MSA timing ignore capability from the DFP
> +                      * sink's virtual DPCD, set during connector init in
> +                      * intel_dp_mst_read_decompression_port_dsc_caps().
> +                      * Avoid live sideband reads here as this function is
> +                      * called from the atomic check path.
> +                      */
> +                     if (!connector->dp.mst_msa_timing_par_ignore)
> +                             return false;
> +
> +                     break;
> +             }
>                intel_dp = intel_attached_dp(connector);
>                /*
>                 * Among non-MST DP branch devices, only an HDMI 2.1 sink connected

--
Jani Nikula, Intel

[-- Attachment #2: Type: text/html, Size: 42675 bytes --]

✗ i915.CI.Full: failure for drm/i915/display: Enable VRR/HDR over MST (rev6)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 106410 bytes --]

== Series Details ==

Series: drm/i915/display: Enable VRR/HDR over MST (rev6)
URL   : https://patchwork.freedesktop.org/series/173155/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_19069_full -> Patchwork_173155v6_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_173155v6_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_173155v6_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_173155v6_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_plane_multiple@tiling-x:
    - shard-tglu:         NOTRUN -> [ABORT][1] +1 other test abort
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_plane_multiple@tiling-x.html

  
Known issues
------------

  Here are the changes found in Patchwork_173155v6_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@api_intel_bb@blit-reloc-purge-cache:
    - shard-rkl:          NOTRUN -> [SKIP][2] ([i915#8411])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-7/igt@api_intel_bb@blit-reloc-purge-cache.html

  * igt@api_intel_bb@crc32:
    - shard-tglu-1:       NOTRUN -> [SKIP][3] ([i915#6230])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@api_intel_bb@crc32.html

  * igt@device_reset@cold-reset-bound:
    - shard-tglu:         NOTRUN -> [SKIP][4] ([i915#11078])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@device_reset@cold-reset-bound.html

  * igt@fbdev@pan:
    - shard-snb:          NOTRUN -> [FAIL][5] ([i915#15792])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-snb6/igt@fbdev@pan.html

  * igt@gem_ccs@block-copy-compressed:
    - shard-tglu-1:       NOTRUN -> [SKIP][6] ([i915#3555] / [i915#9323])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@gem_ccs@block-copy-compressed.html

  * igt@gem_ccs@block-multicopy-inplace:
    - shard-rkl:          NOTRUN -> [SKIP][7] ([i915#3555] / [i915#9323])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-4/igt@gem_ccs@block-multicopy-inplace.html
    - shard-tglu:         NOTRUN -> [SKIP][8] ([i915#3555] / [i915#9323])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@gem_ccs@block-multicopy-inplace.html

  * igt@gem_ccs@ctrl-surf-copy-new-ctx:
    - shard-tglu:         NOTRUN -> [SKIP][9] ([i915#9323])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@gem_ccs@ctrl-surf-copy-new-ctx.html

  * igt@gem_ccs@suspend-resume:
    - shard-tglu-1:       NOTRUN -> [SKIP][10] ([i915#9323])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@gem_ccs@suspend-resume.html

  * igt@gem_close_race@multigpu-basic-process:
    - shard-rkl:          NOTRUN -> [SKIP][11] ([i915#7697])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-7/igt@gem_close_race@multigpu-basic-process.html

  * igt@gem_create@create-ext-cpu-access-sanity-check:
    - shard-tglu-1:       NOTRUN -> [SKIP][12] ([i915#6335])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@gem_create@create-ext-cpu-access-sanity-check.html

  * igt@gem_create@create-ext-set-pat:
    - shard-rkl:          NOTRUN -> [SKIP][13] ([i915#8562])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-3/igt@gem_create@create-ext-set-pat.html

  * igt@gem_ctx_persistence@legacy-engines-mixed:
    - shard-snb:          NOTRUN -> [SKIP][14] ([i915#1099]) +6 other tests skip
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-snb6/igt@gem_ctx_persistence@legacy-engines-mixed.html

  * igt@gem_ctx_sseu@engines:
    - shard-rkl:          NOTRUN -> [SKIP][15] ([i915#280])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-3/igt@gem_ctx_sseu@engines.html

  * igt@gem_ctx_sseu@invalid-sseu:
    - shard-tglu:         NOTRUN -> [SKIP][16] ([i915#280])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@gem_ctx_sseu@invalid-sseu.html

  * igt@gem_eio@in-flight-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][17] ([i915#13390])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-glk5/igt@gem_eio@in-flight-suspend.html

  * igt@gem_eio@unwedge-stress:
    - shard-snb:          NOTRUN -> [FAIL][18] ([i915#8898]) +1 other test fail
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-snb5/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_balancer@parallel-ordering:
    - shard-rkl:          NOTRUN -> [SKIP][19] ([i915#4525])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-4/igt@gem_exec_balancer@parallel-ordering.html
    - shard-tglu:         NOTRUN -> [SKIP][20] ([i915#4525]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@gem_exec_balancer@parallel-ordering.html

  * igt@gem_exec_capture@capture-invisible:
    - shard-glk11:        NOTRUN -> [SKIP][21] ([i915#6334]) +1 other test skip
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-glk11/igt@gem_exec_capture@capture-invisible.html

  * igt@gem_exec_capture@capture-recoverable:
    - shard-tglu:         NOTRUN -> [SKIP][22] ([i915#6344])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@gem_exec_capture@capture-recoverable.html

  * igt@gem_exec_capture@pi@vcs1:
    - shard-dg2:          [PASS][23] -> [FAIL][24] ([i915#15587]) +1 other test fail
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-dg2-6/igt@gem_exec_capture@pi@vcs1.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-dg2-6/igt@gem_exec_capture@pi@vcs1.html

  * igt@gem_exec_reloc@basic-cpu-gtt-noreloc:
    - shard-rkl:          NOTRUN -> [SKIP][25] ([i915#3281]) +9 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-8/igt@gem_exec_reloc@basic-cpu-gtt-noreloc.html

  * igt@gem_huc_copy@huc-copy:
    - shard-rkl:          NOTRUN -> [SKIP][26] ([i915#2190])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-4/igt@gem_huc_copy@huc-copy.html
    - shard-tglu:         NOTRUN -> [SKIP][27] ([i915#2190])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@gem_huc_copy@huc-copy.html

  * igt@gem_lmem_swapping@heavy-random:
    - shard-glk:          NOTRUN -> [SKIP][28] ([i915#4613]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-glk9/igt@gem_lmem_swapping@heavy-random.html

  * igt@gem_lmem_swapping@massive-random:
    - shard-tglu-1:       NOTRUN -> [SKIP][29] ([i915#4613]) +3 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@gem_lmem_swapping@massive-random.html

  * igt@gem_lmem_swapping@parallel-multi:
    - shard-tglu:         NOTRUN -> [SKIP][30] ([i915#4613]) +3 other tests skip
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@gem_lmem_swapping@parallel-multi.html

  * igt@gem_lmem_swapping@random-engines:
    - shard-rkl:          NOTRUN -> [SKIP][31] ([i915#4613]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@gem_lmem_swapping@random-engines.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
    - shard-rkl:          NOTRUN -> [SKIP][32] ([i915#3282])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html

  * igt@gem_pread@exhaustion:
    - shard-snb:          NOTRUN -> [WARN][33] ([i915#2658])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-snb5/igt@gem_pread@exhaustion.html

  * igt@gem_pxp@hw-rejects-pxp-context:
    - shard-rkl:          NOTRUN -> [FAIL][34] ([i915#15169])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-4/igt@gem_pxp@hw-rejects-pxp-context.html
    - shard-tglu:         NOTRUN -> [SKIP][35] ([i915#13398])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@gem_pxp@hw-rejects-pxp-context.html

  * igt@gem_userptr_blits@coherency-unsync:
    - shard-rkl:          NOTRUN -> [SKIP][36] ([i915#3297]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-3/igt@gem_userptr_blits@coherency-unsync.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-tglu:         NOTRUN -> [SKIP][37] ([i915#3297]) +1 other test skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@invalid-mmap-offset-unsync:
    - shard-tglu-1:       NOTRUN -> [SKIP][38] ([i915#3297])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html

  * igt@gem_workarounds@suspend-resume:
    - shard-glk11:        NOTRUN -> [INCOMPLETE][39] ([i915#13356] / [i915#14586])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-glk11/igt@gem_workarounds@suspend-resume.html

  * igt@gen9_exec_parse@basic-rejected-ctx-param:
    - shard-snb:          NOTRUN -> [SKIP][40] +770 other tests skip
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-snb6/igt@gen9_exec_parse@basic-rejected-ctx-param.html

  * igt@gen9_exec_parse@batch-without-end:
    - shard-tglu:         NOTRUN -> [SKIP][41] ([i915#2527] / [i915#2856]) +2 other tests skip
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@gen9_exec_parse@batch-without-end.html

  * igt@gen9_exec_parse@bb-large:
    - shard-tglu-1:       NOTRUN -> [SKIP][42] ([i915#2527] / [i915#2856]) +1 other test skip
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@gen9_exec_parse@bb-large.html

  * igt@gen9_exec_parse@bb-start-far:
    - shard-rkl:          NOTRUN -> [SKIP][43] ([i915#2527])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-8/igt@gen9_exec_parse@bb-start-far.html

  * igt@gpu_buddy@gpu_buddy:
    - shard-tglu-1:       NOTRUN -> [SKIP][44] ([i915#15678])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@gpu_buddy@gpu_buddy.html

  * igt@i915_module_load@resize-bar:
    - shard-tglu-1:       NOTRUN -> [SKIP][45] ([i915#6412])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@i915_module_load@resize-bar.html

  * igt@i915_pm_freq_api@freq-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][46] ([i915#8399])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-7/igt@i915_pm_freq_api@freq-suspend.html

  * igt@i915_pm_rc6_residency@rc6-fence:
    - shard-tglu:         NOTRUN -> [WARN][47] ([i915#13790] / [i915#2681]) +1 other test warn
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@i915_pm_rc6_residency@rc6-fence.html

  * igt@i915_power@sanity:
    - shard-rkl:          NOTRUN -> [SKIP][48] ([i915#7984])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-3/igt@i915_power@sanity.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-rkl:          [PASS][49] -> [INCOMPLETE][50] ([i915#4817])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-4/igt@i915_suspend@fence-restore-untiled.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-4/igt@i915_suspend@fence-restore-untiled.html
    - shard-glk:          [PASS][51] -> [INCOMPLETE][52] ([i915#16182] / [i915#4817])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-glk5/igt@i915_suspend@fence-restore-untiled.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-glk3/igt@i915_suspend@fence-restore-untiled.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-tglu:         NOTRUN -> [SKIP][53] ([i915#1769] / [i915#3555])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [FAIL][54] ([i915#15662]) +1 other test fail
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-8/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][55] ([i915#5286]) +2 other tests skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-7/igt@kms_big_fb@4-tiled-32bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-180:
    - shard-mtlp:         [PASS][56] -> [FAIL][57] ([i915#15733] / [i915#5138])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-mtlp-4/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-mtlp-5/igt@kms_big_fb@4-tiled-64bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-8bpp-rotate-180:
    - shard-tglu:         NOTRUN -> [SKIP][58] ([i915#5286]) +2 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_big_fb@4-tiled-8bpp-rotate-180.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-tglu-1:       NOTRUN -> [SKIP][59] ([i915#5286]) +4 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@linear-64bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][60] ([i915#3638]) +1 other test skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-3/igt@kms_big_fb@linear-64bpp-rotate-90.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-tglu-1:       NOTRUN -> [SKIP][61] ([i915#3828])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-tglu:         NOTRUN -> [SKIP][62] ([i915#3828])
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-4/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0:
    - shard-tglu-1:       NOTRUN -> [SKIP][63] +78 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][64] ([i915#10307] / [i915#10434] / [i915#6095]) +4 other tests skip
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-dg2-4/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-c-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][65] ([i915#10307] / [i915#6095]) +86 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-dg2-4/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][66] ([i915#6095]) +77 other tests skip
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-7/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][67] ([i915#12313])
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-8/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2:
    - shard-glk:          NOTRUN -> [SKIP][68] +334 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-glk4/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][69] ([i915#6095]) +69 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][70] ([i915#6095]) +151 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-dg1-18/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-4.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs@pipe-c-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][71] ([i915#14098] / [i915#6095]) +46 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-8/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][72] ([i915#14098] / [i915#14544] / [i915#6095]) +1 other test skip
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_ccs@crc-sprite-planes-basic-yf-tiled-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][73] ([i915#6095]) +54 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][74] ([i915#12313])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_ccs@random-ccs-data-4-tiled-lnl-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [ABORT][75] ([i915#16852])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-8/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][76] ([i915#14544] / [i915#6095]) +3 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_ccs@random-ccs-data-yf-tiled-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_cdclk@mode-transition:
    - shard-tglu-1:       NOTRUN -> [SKIP][77] ([i915#3742])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_cdclk@mode-transition.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-tglu:         NOTRUN -> [SKIP][78] ([i915#3742])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][79] ([i915#13781]) +3 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-dg2-4/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html

  * igt@kms_chamelium_audio@dp-audio-after-suspend:
    - shard-tglu:         NOTRUN -> [SKIP][80] ([i915#11151])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_chamelium_audio@dp-audio-after-suspend.html
    - shard-rkl:          NOTRUN -> [SKIP][81] ([i915#11151])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-4/igt@kms_chamelium_audio@dp-audio-after-suspend.html

  * igt@kms_chamelium_color_pipeline@plane-lut1d-pre-ctm3x4:
    - shard-tglu-1:       NOTRUN -> [SKIP][82] ([i915#16471]) +1 other test skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_chamelium_color_pipeline@plane-lut1d-pre-ctm3x4.html

  * igt@kms_chamelium_frames@hdmi-crc-fast:
    - shard-rkl:          NOTRUN -> [SKIP][83] ([i915#11151] / [i915#7828]) +7 other tests skip
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-8/igt@kms_chamelium_frames@hdmi-crc-fast.html

  * igt@kms_chamelium_hpd@dp-hpd-storm:
    - shard-tglu-1:       NOTRUN -> [SKIP][84] ([i915#11151] / [i915#7828]) +5 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_chamelium_hpd@dp-hpd-storm.html

  * igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode:
    - shard-tglu:         NOTRUN -> [SKIP][85] ([i915#11151] / [i915#7828]) +6 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_chamelium_hpd@vga-hpd-with-enabled-mode.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-tglu:         NOTRUN -> [SKIP][86] ([i915#15330] / [i915#3116] / [i915#3299])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@mei-interface:
    - shard-tglu:         NOTRUN -> [SKIP][87] ([i915#15865]) +1 other test skip
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@srm:
    - shard-tglu-1:       NOTRUN -> [SKIP][88] ([i915#15865]) +2 other tests skip
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_content_protection@srm.html

  * igt@kms_cursor_crc@cursor-onscreen-256x85:
    - shard-tglu:         NOTRUN -> [FAIL][89] ([i915#13566]) +1 other test fail
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_cursor_crc@cursor-onscreen-256x85.html

  * igt@kms_cursor_crc@cursor-onscreen-32x32:
    - shard-rkl:          NOTRUN -> [SKIP][90] ([i915#3555]) +4 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-7/igt@kms_cursor_crc@cursor-onscreen-32x32.html

  * igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [FAIL][91] ([i915#13566])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-4/igt@kms_cursor_crc@cursor-random-256x85@pipe-a-hdmi-a-2.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-tglu-1:       NOTRUN -> [SKIP][92] ([i915#3555]) +2 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_edge_walk@256x256-top-edge@pipe-d-hdmi-a-1:
    - shard-dg1:          NOTRUN -> [ABORT][93] ([i915#16866] / [i915#16932])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-dg1-15/igt@kms_cursor_edge_walk@256x256-top-edge@pipe-d-hdmi-a-1.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
    - shard-tglu:         NOTRUN -> [SKIP][94] ([i915#4103]) +1 other test skip
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
    - shard-tglu-1:       NOTRUN -> [SKIP][95] ([i915#4103]) +1 other test skip
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html

  * igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
    - shard-glk:          NOTRUN -> [FAIL][96] ([i915#15804])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size:
    - shard-rkl:          NOTRUN -> [SKIP][97] ([i915#4103])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions-varying-size.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-tglu:         NOTRUN -> [SKIP][98] ([i915#13749])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_dp_link_training@uhbr-mst:
    - shard-tglu:         NOTRUN -> [SKIP][99] ([i915#13748])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_dp_link_training@uhbr-mst.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-tglu:         NOTRUN -> [SKIP][100] ([i915#13707])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dp_linktrain_fallback@uhbr-to-hbr-fallback:
    - shard-rkl:          NOTRUN -> [SKIP][101] ([i915#16867])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-8/igt@kms_dp_linktrain_fallback@uhbr-to-hbr-fallback.html

  * igt@kms_dsc@dsc-with-output-formats-bigjoiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][102] ([i915#16361]) +2 other tests skip
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_dsc@dsc-with-output-formats-bigjoiner.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc-bigjoiner:
    - shard-rkl:          NOTRUN -> [SKIP][103] ([i915#16361])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-4/igt@kms_dsc@dsc-with-output-formats-with-bpc-bigjoiner.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc-ultrajoiner:
    - shard-tglu:         NOTRUN -> [SKIP][104] ([i915#16361]) +2 other tests skip
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_dsc@dsc-with-output-formats-with-bpc-ultrajoiner.html

  * igt@kms_fbcon_fbt@psr-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][105] ([i915#16680])
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-3/igt@kms_fbcon_fbt@psr-suspend.html

  * igt@kms_feature_discovery@display-2x:
    - shard-rkl:          NOTRUN -> [SKIP][106] ([i915#16081])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-4/igt@kms_feature_discovery@display-2x.html
    - shard-tglu:         NOTRUN -> [SKIP][107] ([i915#16081])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_feature_discovery@display-2x.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-tglu:         NOTRUN -> [SKIP][108] ([i915#16599])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_flip@2x-flip-vs-modeset:
    - shard-tglu-1:       NOTRUN -> [SKIP][109] ([i915#3637] / [i915#9934]) +3 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_flip@2x-flip-vs-modeset.html

  * igt@kms_flip@2x-flip-vs-panning:
    - shard-rkl:          NOTRUN -> [SKIP][110] ([i915#9934]) +4 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-3/igt@kms_flip@2x-flip-vs-panning.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][111] ([i915#12745] / [i915#4839]) +1 other test incomplete
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-glk6/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@2x-plain-flip-interruptible:
    - shard-tglu:         NOTRUN -> [SKIP][112] ([i915#3637] / [i915#9934]) +8 other tests skip
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_flip@2x-plain-flip-interruptible.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank@b-vga1:
    - shard-snb:          [PASS][113] -> [FAIL][114] ([i915#14600]) +1 other test fail
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-snb7/igt@kms_flip@flip-vs-absolute-wf_vblank@b-vga1.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-snb7/igt@kms_flip@flip-vs-absolute-wf_vblank@b-vga1.html

  * igt@kms_flip@flip-vs-suspend@a-hdmi-a1:
    - shard-glk:          NOTRUN -> [INCOMPLETE][115] ([i915#12745]) +1 other test incomplete
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-glk9/igt@kms_flip@flip-vs-suspend@a-hdmi-a1.html

  * igt@kms_flip@modeset-vs-vblank-race-interruptible:
    - shard-tglu:         [PASS][116] -> [ABORT][117] ([i915#16876])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-tglu-10/igt@kms_flip@modeset-vs-vblank-race-interruptible.html
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-6/igt@kms_flip@modeset-vs-vblank-race-interruptible.html

  * igt@kms_flip@modeset-vs-vblank-race-interruptible@d-hdmi-a1:
    - shard-tglu:         [PASS][118] -> [ABORT][119] ([i915#16844] / [i915#16876])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-tglu-10/igt@kms_flip@modeset-vs-vblank-race-interruptible@d-hdmi-a1.html
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-6/igt@kms_flip@modeset-vs-vblank-race-interruptible@d-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][120] ([i915#15643]) +3 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling:
    - shard-rkl:          NOTRUN -> [SKIP][121] ([i915#15643]) +2 other tests skip
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling:
    - shard-tglu:         NOTRUN -> [SKIP][122] ([i915#15643]) +3 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-rkl:          NOTRUN -> [SKIP][123] ([i915#1825]) +6 other tests skip
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][124] ([i915#10056] / [i915#16593])
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-glk10/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-4:
    - shard-rkl:          NOTRUN -> [SKIP][125] ([i915#5439]) +1 other test skip
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
    - shard-tglu:         NOTRUN -> [SKIP][126] ([i915#5439])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_frontbuffer_tracking@fbc-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-onoff:
    - shard-rkl:          [PASS][127] -> [SKIP][128] ([i915#15989]) +10 other tests skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-onoff.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-draw-render:
    - shard-rkl:          NOTRUN -> [SKIP][129] ([i915#15989]) +18 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-3/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-shrfb-plflip-blt:
    - shard-tglu:         NOTRUN -> [SKIP][130] +81 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-4/igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render:
    - shard-glk10:        NOTRUN -> [SKIP][131] +60 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-glk10/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-spr-indfb-draw-blt:
    - shard-rkl:          NOTRUN -> [SKIP][132] ([i915#15102]) +40 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@hdr-1p-offscreen-pri-indfb-draw-blt:
    - shard-tglu:         NOTRUN -> [SKIP][133] ([i915#15989]) +17 other tests skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_frontbuffer_tracking@hdr-1p-offscreen-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-pwrite:
    - shard-tglu-1:       NOTRUN -> [SKIP][134] ([i915#15989]) +17 other tests skip
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc:
    - shard-tglu-1:       NOTRUN -> [SKIP][135] ([i915#15102]) +31 other tests skip
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
    - shard-tglu:         NOTRUN -> [SKIP][136] ([i915#15102]) +41 other tests skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-cur-indfb-move:
    - shard-rkl:          NOTRUN -> [SKIP][137] +67 other tests skip
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-8/igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psrhdr-rgb565-draw-mmap-gtt:
    - shard-glk11:        NOTRUN -> [SKIP][138] +89 other tests skip
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-glk11/igt@kms_frontbuffer_tracking@psrhdr-rgb565-draw-mmap-gtt.html

  * igt@kms_hdr@static-toggle:
    - shard-tglu-1:       NOTRUN -> [SKIP][139] ([i915#3555] / [i915#8228])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_hdr@static-toggle.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][140] ([i915#16644] / [i915#3555] / [i915#8228])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-7/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-tglu:         NOTRUN -> [SKIP][141] ([i915#3555] / [i915#8228])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-4/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][142] ([i915#15458]) +1 other test skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-7/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-tglu-1:       NOTRUN -> [SKIP][143] ([i915#15815])
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier:
    - shard-tglu:         NOTRUN -> [SKIP][144] ([i915#15709]) +2 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-ccs-modifier:
    - shard-rkl:          NOTRUN -> [SKIP][145] ([i915#15709]) +2 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-8/igt@kms_plane@pixel-format-y-tiled-ccs-modifier.html

  * igt@kms_plane@pixel-format-yf-tiled-modifier-source-clamping:
    - shard-tglu-1:       NOTRUN -> [SKIP][146] ([i915#15709]) +2 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_plane@pixel-format-yf-tiled-modifier-source-clamping.html

  * igt@kms_plane@plane-panning-bottom-right-suspend:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][147] ([i915#13026]) +1 other test incomplete
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-glk10/igt@kms_plane@plane-panning-bottom-right-suspend.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-tglu-1:       NOTRUN -> [SKIP][148] ([i915#13958])
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@kms_plane_multiple@tiling-yf:
    - shard-tglu:         NOTRUN -> [SKIP][149] ([i915#14259])
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_plane_multiple@tiling-yf.html

  * igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation:
    - shard-tglu-1:       NOTRUN -> [SKIP][150] ([i915#15329] / [i915#3555])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation.html

  * igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a:
    - shard-tglu-1:       NOTRUN -> [SKIP][151] ([i915#15329]) +8 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-rkl:          NOTRUN -> [SKIP][152] ([i915#12343] / [i915#5354])
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-3/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-tglu:         NOTRUN -> [SKIP][153] ([i915#12343] / [i915#9812])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_backlight@fade-with-suspend:
    - shard-tglu-1:       NOTRUN -> [SKIP][154] ([i915#12343] / [i915#9812])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_pm_backlight@fade-with-suspend.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-rkl:          NOTRUN -> [SKIP][155] ([i915#3828])
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-7/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-tglu:         NOTRUN -> [SKIP][156] ([i915#15073])
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp-stress:
    - shard-rkl:          NOTRUN -> [SKIP][157] ([i915#15073]) +2 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-3/igt@kms_pm_rpm@modeset-lpsp-stress.html
    - shard-dg1:          [PASS][158] -> [SKIP][159] ([i915#15073])
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-dg1-14/igt@kms_pm_rpm@modeset-lpsp-stress.html
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-dg1-18/igt@kms_pm_rpm@modeset-lpsp-stress.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-dg2:          [PASS][160] -> [SKIP][161] ([i915#15073]) +1 other test skip
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-dg2-1/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-dg2-4/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_pm_rpm@system-suspend-idle:
    - shard-rkl:          [PASS][162] -> [INCOMPLETE][163] ([i915#14419])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-3/igt@kms_pm_rpm@system-suspend-idle.html
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_pm_rpm@system-suspend-idle.html

  * igt@kms_prime@d3hot:
    - shard-tglu-1:       NOTRUN -> [SKIP][164] ([i915#6524])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_prime@d3hot.html

  * igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-rkl:          NOTRUN -> [SKIP][165] ([i915#11520]) +6 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-3/igt@kms_psr2_sf@fbc-pr-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area:
    - shard-snb:          NOTRUN -> [SKIP][166] ([i915#11520]) +14 other tests skip
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-snb5/igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-glk10:        NOTRUN -> [SKIP][167] ([i915#11520]) +4 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-glk10/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area:
    - shard-glk11:        NOTRUN -> [SKIP][168] ([i915#11520]) +2 other tests skip
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-glk11/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
    - shard-glk:          NOTRUN -> [SKIP][169] ([i915#11520]) +8 other tests skip
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-glk9/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-tglu-1:       NOTRUN -> [SKIP][170] ([i915#11520]) +5 other tests skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb:
    - shard-tglu:         NOTRUN -> [SKIP][171] ([i915#11520]) +6 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_psr2_sf@psr2-primary-plane-update-sf-dmg-area-big-fb.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-tglu-1:       NOTRUN -> [SKIP][172] ([i915#9683])
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr@psr-cursor-plane-onoff:
    - shard-tglu-1:       NOTRUN -> [SKIP][173] ([i915#9732]) +14 other tests skip
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_psr@psr-cursor-plane-onoff.html

  * igt@kms_psr@psr2-cursor-blt:
    - shard-rkl:          NOTRUN -> [SKIP][174] ([i915#1072] / [i915#9732]) +15 other tests skip
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-7/igt@kms_psr@psr2-cursor-blt.html

  * igt@kms_psr@psr2-cursor-plane-onoff:
    - shard-tglu:         NOTRUN -> [SKIP][175] ([i915#9732]) +18 other tests skip
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_psr@psr2-cursor-plane-onoff.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-tglu-1:       NOTRUN -> [SKIP][176] ([i915#15949])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rmfb@close-fd@pipe-b-hdmi-a-1:
    - shard-rkl:          [PASS][177] -> [ABORT][178] ([i915#16852]) +1 other test abort
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-2/igt@kms_rmfb@close-fd@pipe-b-hdmi-a-1.html
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-2/igt@kms_rmfb@close-fd@pipe-b-hdmi-a-1.html

  * igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
    - shard-glk:          NOTRUN -> [INCOMPLETE][179] ([i915#15500] / [i915#16184])
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-glk4/igt@kms_rotation_crc@multiplane-rotation-cropping-bottom.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180:
    - shard-tglu-1:       NOTRUN -> [SKIP][180] ([i915#5289]) +1 other test skip
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-180.html

  * igt@kms_scaling_modes@scaling-mode-full:
    - shard-tglu:         NOTRUN -> [SKIP][181] ([i915#3555]) +6 other tests skip
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_scaling_modes@scaling-mode-full.html

  * igt@kms_selftest@drm_framebuffer:
    - shard-snb:          NOTRUN -> [ABORT][182] ([i915#13179]) +1 other test abort
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-snb5/igt@kms_selftest@drm_framebuffer.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-tglu-1:       NOTRUN -> [SKIP][183] ([i915#8623])
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vblank@ts-continuation-suspend:
    - shard-glk11:        NOTRUN -> [INCOMPLETE][184] ([i915#12276]) +1 other test incomplete
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-glk11/igt@kms_vblank@ts-continuation-suspend.html
    - shard-rkl:          [PASS][185] -> [ABORT][186] ([i915#15132])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-5/igt@kms_vblank@ts-continuation-suspend.html
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-1/igt@kms_vblank@ts-continuation-suspend.html

  * igt@kms_vblank@ts-continuation-suspend@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [ABORT][187] ([i915#15132])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-1/igt@kms_vblank@ts-continuation-suspend@pipe-c-hdmi-a-2.html

  * igt@kms_vrr@flip-suspend:
    - shard-rkl:          NOTRUN -> [SKIP][188] ([i915#15243] / [i915#3555])
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-4/igt@kms_vrr@flip-suspend.html

  * igt@kms_vrr@lobf:
    - shard-tglu-1:       NOTRUN -> [SKIP][189] ([i915#11920])
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-1/igt@kms_vrr@lobf.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-tglu:         NOTRUN -> [SKIP][190] ([i915#9906])
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@prime_udl@share-import-addfb:
    - shard-rkl:          NOTRUN -> [SKIP][191] ([i915#16420])
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-4/igt@prime_udl@share-import-addfb.html
    - shard-tglu:         NOTRUN -> [SKIP][192] ([i915#16420])
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-8/igt@prime_udl@share-import-addfb.html

  * igt@prime_vgem@basic-write:
    - shard-rkl:          NOTRUN -> [SKIP][193] ([i915#3291] / [i915#3708])
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-8/igt@prime_vgem@basic-write.html

  * igt@prime_vgem@coherency-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][194] ([i915#3708]) +1 other test skip
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-3/igt@prime_vgem@coherency-gtt.html

  
#### Possible fixes ####

  * igt@gem_exec_big@single:
    - shard-mtlp:         [FAIL][195] ([i915#15871]) -> [PASS][196]
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-mtlp-8/igt@gem_exec_big@single.html
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-mtlp-1/igt@gem_exec_big@single.html

  * igt@i915_power@sanity:
    - shard-mtlp:         [SKIP][197] ([i915#7984]) -> [PASS][198]
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-mtlp-1/igt@i915_power@sanity.html
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-mtlp-7/igt@i915_power@sanity.html

  * igt@i915_suspend@debugfs-reader:
    - shard-rkl:          [INCOMPLETE][199] ([i915#4817]) -> [PASS][200]
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-3/igt@i915_suspend@debugfs-reader.html
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-7/igt@i915_suspend@debugfs-reader.html

  * igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1:
    - shard-tglu:         [FAIL][201] ([i915#15662]) -> [PASS][202] +1 other test pass
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-tglu-8/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-10/igt@kms_atomic_transition@plane-all-modeset-transition@pipe-a-hdmi-a-1.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-mtlp:         [FAIL][203] ([i915#15733] / [i915#5138]) -> [PASS][204]
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-mtlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_cursor_crc@cursor-suspend:
    - shard-rkl:          [ABORT][205] ([i915#15132]) -> [PASS][206]
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-1/igt@kms_cursor_crc@cursor-suspend.html
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-8/igt@kms_cursor_crc@cursor-suspend.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank:
    - shard-tglu:         [ABORT][207] ([i915#16857] / [i915#16876]) -> [PASS][208] +1 other test pass
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-tglu-6/igt@kms_flip@flip-vs-blocking-wf-vblank.html
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-4/igt@kms_flip@flip-vs-blocking-wf-vblank.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-rkl:          [INCOMPLETE][209] ([i915#16276] / [i915#6113]) -> [PASS][210]
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_flip@flip-vs-suspend.html
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-rkl:          [INCOMPLETE][211] ([i915#10056]) -> [PASS][212]
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-pri-indfb-draw-render:
    - shard-glk:          [SKIP][213] -> [PASS][214] +6 other tests pass
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-glk2/igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-pri-indfb-draw-render.html
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-glk8/igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@hdr-farfromfence-mmap-gtt:
    - shard-rkl:          [SKIP][215] ([i915#15989]) -> [PASS][216] +13 other tests pass
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_frontbuffer_tracking@hdr-farfromfence-mmap-gtt.html
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_frontbuffer_tracking@hdr-farfromfence-mmap-gtt.html

  * igt@kms_hdr@static-toggle:
    - shard-rkl:          [SKIP][217] ([i915#16644] / [i915#3555] / [i915#8228]) -> [PASS][218] +2 other tests pass
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_hdr@static-toggle.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_hdr@static-toggle.html

  * igt@kms_pm_rpm@i2c:
    - shard-dg1:          [DMESG-WARN][219] ([i915#4423]) -> [PASS][220] +1 other test pass
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-dg1-18/igt@kms_pm_rpm@i2c.html
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-dg1-12/igt@kms_pm_rpm@i2c.html

  * igt@kms_pm_rpm@modeset-lpsp-stress-no-wait:
    - shard-rkl:          [SKIP][221] ([i915#14544] / [i915#15073]) -> [PASS][222]
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_pm_rpm@modeset-lpsp-stress-no-wait.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-rkl:          [SKIP][223] ([i915#15073]) -> [PASS][224] +1 other test pass
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-8/igt@kms_pm_rpm@modeset-non-lpsp.html
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-3/igt@kms_pm_rpm@modeset-non-lpsp.html
    - shard-dg1:          [SKIP][225] ([i915#15073]) -> [PASS][226]
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-dg1-14/igt@kms_pm_rpm@modeset-non-lpsp.html
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-dg1-19/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@perf_pmu@busy-double-start@vcs1:
    - shard-mtlp:         [FAIL][227] ([i915#4349]) -> [PASS][228] +1 other test pass
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-mtlp-1/igt@perf_pmu@busy-double-start@vcs1.html
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-mtlp-7/igt@perf_pmu@busy-double-start@vcs1.html

  
#### Warnings ####

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-rkl:          [SKIP][229] ([i915#11078] / [i915#14544]) -> [SKIP][230] ([i915#11078])
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@device_reset@unbind-cold-reset-rebind.html
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@gem_basic@multigpu-create-close:
    - shard-rkl:          [SKIP][231] ([i915#7697]) -> [SKIP][232] ([i915#14544] / [i915#7697])
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-2/igt@gem_basic@multigpu-create-close.html
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@gem_basic@multigpu-create-close.html

  * igt@gem_ccs@large-ctrl-surf-copy:
    - shard-rkl:          [SKIP][233] ([i915#13008]) -> [SKIP][234] ([i915#13008] / [i915#14544])
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-2/igt@gem_ccs@large-ctrl-surf-copy.html
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@gem_ccs@large-ctrl-surf-copy.html

  * igt@gem_ccs@suspend-resume:
    - shard-rkl:          [SKIP][235] ([i915#9323]) -> [SKIP][236] ([i915#14544] / [i915#9323])
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@gem_ccs@suspend-resume.html
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@gem_ccs@suspend-resume.html

  * igt@gem_ctx_sseu@mmap-args:
    - shard-rkl:          [SKIP][237] ([i915#14544] / [i915#280]) -> [SKIP][238] ([i915#280])
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@gem_ctx_sseu@mmap-args.html
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@gem_ctx_sseu@mmap-args.html

  * igt@gem_eio@kms:
    - shard-dg1:          [ABORT][239] ([i915#16837] / [i915#16931]) -> [ABORT][240] ([i915#16837])
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-dg1-12/igt@gem_eio@kms.html
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-dg1-14/igt@gem_eio@kms.html
    - shard-tglu:         [ABORT][241] ([i915#16837] / [i915#16844]) -> [ABORT][242] ([i915#16837])
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-tglu-7/igt@gem_eio@kms.html
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-7/igt@gem_eio@kms.html

  * igt@gem_exec_balancer@parallel:
    - shard-rkl:          [SKIP][243] ([i915#14544] / [i915#4525]) -> [SKIP][244] ([i915#4525]) +1 other test skip
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@gem_exec_balancer@parallel.html
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_big@single:
    - shard-tglu:         [FAIL][245] ([i915#15816]) -> [FAIL][246] ([i915#15944])
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-tglu-8/igt@gem_exec_big@single.html
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-10/igt@gem_exec_big@single.html

  * igt@gem_exec_reloc@basic-gtt-wc-noreloc:
    - shard-rkl:          [SKIP][247] ([i915#3281]) -> [SKIP][248] ([i915#14544] / [i915#3281]) +2 other tests skip
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html

  * igt@gem_exec_reloc@basic-wc-gtt:
    - shard-rkl:          [SKIP][249] ([i915#14544] / [i915#3281]) -> [SKIP][250] ([i915#3281]) +3 other tests skip
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@gem_exec_reloc@basic-wc-gtt.html
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@gem_exec_reloc@basic-wc-gtt.html

  * igt@gem_lmem_swapping@heavy-verify-random:
    - shard-rkl:          [SKIP][251] ([i915#14544] / [i915#4613]) -> [SKIP][252] ([i915#4613]) +1 other test skip
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@gem_lmem_swapping@heavy-verify-random.html
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@gem_lmem_swapping@heavy-verify-random.html

  * igt@gem_lmem_swapping@parallel-random:
    - shard-rkl:          [SKIP][253] ([i915#4613]) -> [SKIP][254] ([i915#14544] / [i915#4613]) +1 other test skip
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@gem_lmem_swapping@parallel-random.html
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@gem_lmem_swapping@parallel-random.html

  * igt@gem_readwrite@beyond-eob:
    - shard-rkl:          [SKIP][255] ([i915#3282]) -> [SKIP][256] ([i915#14544] / [i915#3282]) +5 other tests skip
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-2/igt@gem_readwrite@beyond-eob.html
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@gem_readwrite@beyond-eob.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-rkl:          [SKIP][257] ([i915#14544] / [i915#8411]) -> [SKIP][258] ([i915#8411])
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-4/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_userptr_blits@invalid-mmap-offset-unsync:
    - shard-rkl:          [SKIP][259] ([i915#3297]) -> [SKIP][260] ([i915#14544] / [i915#3297])
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html

  * igt@gem_userptr_blits@readonly-pwrite-unsync:
    - shard-rkl:          [SKIP][261] ([i915#14544] / [i915#3297]) -> [SKIP][262] ([i915#3297]) +1 other test skip
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@gem_userptr_blits@readonly-pwrite-unsync.html
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@gem_userptr_blits@readonly-pwrite-unsync.html

  * igt@gem_userptr_blits@relocations:
    - shard-rkl:          [SKIP][263] ([i915#3281] / [i915#3297]) -> [SKIP][264] ([i915#14544] / [i915#3281] / [i915#3297])
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@gem_userptr_blits@relocations.html
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@gem_userptr_blits@relocations.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-rkl:          [SKIP][265] ([i915#2527]) -> [SKIP][266] ([i915#14544] / [i915#2527]) +1 other test skip
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@gen9_exec_parse@allowed-single.html
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@bb-start-param:
    - shard-rkl:          [SKIP][267] ([i915#14544] / [i915#2527]) -> [SKIP][268] ([i915#2527]) +2 other tests skip
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@gen9_exec_parse@bb-start-param.html
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@gen9_exec_parse@bb-start-param.html

  * igt@gpu_buddy@gpu_buddy:
    - shard-rkl:          [SKIP][269] ([i915#15678]) -> [SKIP][270] ([i915#14544] / [i915#15678])
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@gpu_buddy@gpu_buddy.html
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@gpu_buddy@gpu_buddy.html

  * igt@i915_module_load@resize-bar:
    - shard-rkl:          [SKIP][271] ([i915#6412]) -> [SKIP][272] ([i915#14544] / [i915#6412])
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@i915_module_load@resize-bar.html
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@i915_module_load@resize-bar.html

  * igt@i915_pm_freq_api@freq-reset-multiple:
    - shard-rkl:          [SKIP][273] ([i915#8399]) -> [SKIP][274] ([i915#14544] / [i915#8399])
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-2/igt@i915_pm_freq_api@freq-reset-multiple.html
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@i915_pm_freq_api@freq-reset-multiple.html

  * igt@i915_pm_rc6_residency@rc6-idle:
    - shard-rkl:          [SKIP][275] ([i915#14498] / [i915#14544]) -> [SKIP][276] ([i915#14498])
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@i915_pm_rc6_residency@rc6-idle.html
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-idle.html

  * igt@i915_pm_sseu@full-enable:
    - shard-rkl:          [SKIP][277] ([i915#4387]) -> [SKIP][278] ([i915#14544] / [i915#4387])
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-2/igt@i915_pm_sseu@full-enable.html
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@i915_pm_sseu@full-enable.html

  * igt@i915_suspend@forcewake:
    - shard-rkl:          [INCOMPLETE][279] ([i915#4817]) -> [ABORT][280] ([i915#15140])
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-3/igt@i915_suspend@forcewake.html
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-1/igt@i915_suspend@forcewake.html

  * igt@intel_hwmon@hwmon-read:
    - shard-rkl:          [SKIP][281] ([i915#7707]) -> [SKIP][282] ([i915#14544] / [i915#7707])
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-2/igt@intel_hwmon@hwmon-read.html
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@intel_hwmon@hwmon-read.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-rkl:          [SKIP][283] ([i915#12454] / [i915#12712] / [i915#14544]) -> [SKIP][284] ([i915#12454] / [i915#12712])
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-0:
    - shard-rkl:          [SKIP][285] ([i915#5286]) -> [SKIP][286] ([i915#14544] / [i915#5286]) +3 other tests skip
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-2/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-rkl:          [SKIP][287] ([i915#14544] / [i915#5286]) -> [SKIP][288] ([i915#5286]) +5 other tests skip
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-rkl:          [SKIP][289] ([i915#14544] / [i915#3828]) -> [SKIP][290] ([i915#3828])
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip.html
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-rkl:          [SKIP][291] ([i915#3828]) -> [SKIP][292] ([i915#14544] / [i915#3828])
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-4/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip.html
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-270:
    - shard-rkl:          [SKIP][293] ([i915#3638]) -> [SKIP][294] ([i915#14544] / [i915#3638]) +1 other test skip
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-2/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_big_fb@x-tiled-16bpp-rotate-270.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc:
    - shard-rkl:          [ABORT][295] ([i915#16852]) -> [SKIP][296] ([i915#14098] / [i915#6095])
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-5/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc.html
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-3/igt@kms_ccs@bad-rotation-90-4-tiled-dg2-rc-ccs-cc.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
    - shard-rkl:          [SKIP][297] ([i915#12313] / [i915#14544]) -> [SKIP][298] ([i915#12313])
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html

  * igt@kms_ccs@bad-rotation-90-yf-tiled-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          [SKIP][299] ([i915#6095]) -> [SKIP][300] ([i915#14544] / [i915#6095]) +4 other tests skip
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_ccs@bad-rotation-90-yf-tiled-ccs@pipe-b-hdmi-a-2.html
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_ccs@bad-rotation-90-yf-tiled-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs:
    - shard-rkl:          [SKIP][301] ([i915#14098] / [i915#14544] / [i915#6095]) -> [SKIP][302] ([i915#14098] / [i915#6095]) +5 other tests skip
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs.html
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-dg2-mc-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          [SKIP][303] ([i915#14098] / [i915#6095]) -> [SKIP][304] ([i915#14098] / [i915#14544] / [i915#6095]) +7 other tests skip
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2.html
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-rkl:          [SKIP][305] ([i915#12805]) -> [SKIP][306] ([i915#12805] / [i915#14544])
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-2/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc:
    - shard-rkl:          [SKIP][307] ([i915#14098] / [i915#6095]) -> [ABORT][308] ([i915#16852])
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc.html
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-8/igt@kms_ccs@random-ccs-data-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_cdclk@mode-transition:
    - shard-rkl:          [SKIP][309] ([i915#3742]) -> [SKIP][310] ([i915#14544] / [i915#3742])
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_cdclk@mode-transition.html
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_cdclk@mode-transition.html

  * igt@kms_chamelium_color_pipeline@plane-lut1d:
    - shard-rkl:          [SKIP][311] ([i915#14544] / [i915#16471]) -> [SKIP][312] ([i915#16471])
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_chamelium_color_pipeline@plane-lut1d.html
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_chamelium_color_pipeline@plane-lut1d.html

  * igt@kms_chamelium_color_pipeline@plane-lut1d-post-ctm3x4:
    - shard-rkl:          [SKIP][313] ([i915#16471]) -> [SKIP][314] ([i915#14544] / [i915#16471]) +1 other test skip
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_chamelium_color_pipeline@plane-lut1d-post-ctm3x4.html
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_chamelium_color_pipeline@plane-lut1d-post-ctm3x4.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - shard-rkl:          [SKIP][315] ([i915#11151] / [i915#7828]) -> [SKIP][316] ([i915#11151] / [i915#14544] / [i915#7828]) +2 other tests skip
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_chamelium_hpd@dp-hpd:
    - shard-rkl:          [SKIP][317] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][318] ([i915#11151] / [i915#7828]) +3 other tests skip
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_chamelium_hpd@dp-hpd.html
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_chamelium_hpd@dp-hpd.html

  * igt@kms_content_protection@atomic-dpms-hdcp14:
    - shard-rkl:          [SKIP][319] ([i915#15865]) -> [SKIP][320] ([i915#14544] / [i915#15865]) +1 other test skip
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_content_protection@atomic-dpms-hdcp14.html
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_content_protection@atomic-dpms-hdcp14.html

  * igt@kms_content_protection@dp-mst-lic-type-0:
    - shard-dg1:          [SKIP][321] ([i915#15330] / [i915#3299]) -> [SKIP][322] ([i915#15330] / [i915#3299] / [i915#4423])
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-dg1-17/igt@kms_content_protection@dp-mst-lic-type-0.html
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-dg1-12/igt@kms_content_protection@dp-mst-lic-type-0.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-rkl:          [SKIP][323] ([i915#14544] / [i915#15330] / [i915#3116]) -> [SKIP][324] ([i915#15330] / [i915#3116])
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_content_protection@dp-mst-type-1.html
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@mei-interface:
    - shard-rkl:          [SKIP][325] ([i915#14544] / [i915#15865]) -> [SKIP][326] ([i915#15865]) +1 other test skip
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_content_protection@mei-interface.html
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-4/igt@kms_content_protection@mei-interface.html
    - shard-dg1:          [SKIP][327] ([i915#9433]) -> [SKIP][328] ([i915#15865])
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-dg1-12/igt@kms_content_protection@mei-interface.html
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-dg1-16/igt@kms_content_protection@mei-interface.html

  * igt@kms_cursor_crc@cursor-random-32x10:
    - shard-rkl:          [SKIP][329] ([i915#14544] / [i915#3555]) -> [SKIP][330] ([i915#3555]) +4 other tests skip
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_cursor_crc@cursor-random-32x10.html
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-4/igt@kms_cursor_crc@cursor-random-32x10.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-rkl:          [SKIP][331] ([i915#3555]) -> [SKIP][332] ([i915#14544] / [i915#3555]) +3 other tests skip
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_edge_walk@256x256-top-edge:
    - shard-dg1:          [DMESG-WARN][333] ([i915#16685]) -> [ABORT][334] ([i915#16866] / [i915#16932])
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-dg1-13/igt@kms_cursor_edge_walk@256x256-top-edge.html
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-dg1-15/igt@kms_cursor_edge_walk@256x256-top-edge.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
    - shard-rkl:          [SKIP][335] ([i915#4103]) -> [SKIP][336] ([i915#14544] / [i915#4103])
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html

  * igt@kms_dp_aux_dev@basic:
    - shard-rkl:          [SKIP][337] ([i915#1257]) -> [SKIP][338] ([i915#1257] / [i915#14544])
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-2/igt@kms_dp_aux_dev@basic.html
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_dp_aux_dev@basic.html

  * igt@kms_dp_link_training@uhbr-mst:
    - shard-rkl:          [SKIP][339] ([i915#13748] / [i915#14544]) -> [SKIP][340] ([i915#13748])
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_dp_link_training@uhbr-mst.html
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-4/igt@kms_dp_link_training@uhbr-mst.html

  * igt@kms_dsc@dsc-basic-bigjoiner:
    - shard-rkl:          [SKIP][341] ([i915#14544] / [i915#16361]) -> [SKIP][342] ([i915#16361]) +1 other test skip
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_dsc@dsc-basic-bigjoiner.html
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_dsc@dsc-basic-bigjoiner.html

  * igt@kms_dsc@dsc-basic-ultrajoiner:
    - shard-rkl:          [SKIP][343] ([i915#16361]) -> [SKIP][344] ([i915#14544] / [i915#16361]) +2 other tests skip
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_dsc@dsc-basic-ultrajoiner.html
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_dsc@dsc-basic-ultrajoiner.html

  * igt@kms_feature_discovery@dsc:
    - shard-rkl:          [SKIP][345] ([i915#16600]) -> [SKIP][346] ([i915#14544] / [i915#16600])
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-2/igt@kms_feature_discovery@dsc.html
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_feature_discovery@dsc.html

  * igt@kms_feature_discovery@psr1:
    - shard-rkl:          [SKIP][347] ([i915#14544] / [i915#658]) -> [SKIP][348] ([i915#658])
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_feature_discovery@psr1.html
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-flip-vs-modeset:
    - shard-rkl:          [SKIP][349] ([i915#9934]) -> [SKIP][350] ([i915#14544] / [i915#9934]) +5 other tests skip
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_flip@2x-flip-vs-modeset.html
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_flip@2x-flip-vs-modeset.html

  * igt@kms_flip@2x-modeset-vs-vblank-race-interruptible:
    - shard-rkl:          [SKIP][351] ([i915#14544] / [i915#9934]) -> [SKIP][352] ([i915#9934]) +2 other tests skip
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_flip@2x-modeset-vs-vblank-race-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling:
    - shard-rkl:          [SKIP][353] ([i915#14544] / [i915#15643]) -> [SKIP][354] ([i915#15643]) +1 other test skip
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-rkl:          [SKIP][355] ([i915#15643]) -> [SKIP][356] ([i915#14544] / [i915#15643])
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_force_connector_basic@force-load-detect:
    - shard-mtlp:         [SKIP][357] ([i915#15672]) -> [SKIP][358]
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-mtlp-1/igt@kms_force_connector_basic@force-load-detect.html
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-mtlp-7/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt:
    - shard-rkl:          [SKIP][359] ([i915#14544]) -> [SKIP][360] +47 other tests skip
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-4/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-spr-indfb-draw-render:
    - shard-rkl:          [SKIP][361] -> [SKIP][362] ([i915#14544]) +60 other tests skip
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-2/igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-spr-indfb-draw-render.html
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_frontbuffer_tracking@fbchdr-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][363] ([i915#1825]) -> [SKIP][364] ([i915#14544] / [i915#1825]) +1 other test skip
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt.html
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc:
    - shard-dg1:          [SKIP][365] ([i915#15990] / [i915#8708]) -> [SKIP][366] ([i915#15990] / [i915#4423] / [i915#8708])
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc.html
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-dg1-12/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-spr-indfb-draw-mmap-cpu:
    - shard-rkl:          [SKIP][367] ([i915#14544] / [i915#15102]) -> [SKIP][368] ([i915#15102]) +15 other tests skip
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-spr-indfb-draw-mmap-cpu.html
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-spr-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-rte:
    - shard-rkl:          [SKIP][369] ([i915#15102]) -> [SKIP][370] ([i915#14544] / [i915#15102]) +27 other tests skip
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-rte.html
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-primscrn-pri-indfb-draw-blt:
    - shard-dg1:          [SKIP][371] -> [SKIP][372] ([i915#4423])
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-dg1-18/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-primscrn-pri-indfb-draw-blt.html
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-dg1-17/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-pwrite:
    - shard-dg1:          [SKIP][373] ([i915#15102] / [i915#4423]) -> [SKIP][374] ([i915#15102])
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-dg1-12/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-pwrite.html
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-dg1-14/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-rkl:          [SKIP][375] ([i915#14544] / [i915#1825]) -> [SKIP][376] ([i915#1825]) +2 other tests skip
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc.html
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-pri-indfb-draw-pwrite:
    - shard-dg1:          [SKIP][377] ([i915#4423]) -> [SKIP][378]
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-dg1-12/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-pri-indfb-draw-pwrite.html
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-dg1-14/igt@kms_frontbuffer_tracking@psrhdr-2p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-rkl:          [INCOMPLETE][379] ([i915#15436]) -> [SKIP][380] ([i915#16644] / [i915#3555] / [i915#8228])
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_hdr@static-toggle-suspend.html
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-rkl:          [SKIP][381] ([i915#14544] / [i915#15460]) -> [SKIP][382] ([i915#15460])
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_joiner@basic-big-joiner.html
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-rkl:          [SKIP][383] ([i915#14544] / [i915#15459]) -> [SKIP][384] ([i915#15459])
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier:
    - shard-rkl:          [SKIP][385] ([i915#15709]) -> [SKIP][386] ([i915#14544] / [i915#15709])
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-2/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier.html
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier.html

  * igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping:
    - shard-rkl:          [SKIP][387] ([i915#14544] / [i915#15709]) -> [SKIP][388] ([i915#15709]) +2 other tests skip
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping.html
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping.html

  * igt@kms_pm_dc@dc5-psr-suspend-resume:
    - shard-rkl:          [SKIP][389] ([i915#14544] / [i915#16914]) -> [SKIP][390] ([i915#16914])
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_pm_dc@dc5-psr-suspend-resume.html
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_pm_dc@dc5-psr-suspend-resume.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-tglu:         [FAIL][391] ([i915#16479]) -> [SKIP][392] ([i915#15128])
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-tglu-9/igt@kms_pm_dc@dc6-dpms.html
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-tglu-6/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-dg1:          [SKIP][393] ([i915#9340]) -> [SKIP][394] ([i915#3828])
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-dg1-13/igt@kms_pm_lpsp@kms-lpsp.html
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-dg1-15/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_prime@d3hot:
    - shard-rkl:          [SKIP][395] ([i915#6524]) -> [SKIP][396] ([i915#14544] / [i915#6524])
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_prime@d3hot.html
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_prime@d3hot.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area:
    - shard-rkl:          [SKIP][397] ([i915#11520]) -> [SKIP][398] ([i915#11520] / [i915#14544]) +3 other tests skip
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area.html
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_psr2_sf@fbc-psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area:
    - shard-rkl:          [SKIP][399] ([i915#11520] / [i915#14544]) -> [SKIP][400] ([i915#11520]) +4 other tests skip
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_psr2_sf@fbc-psr2-primary-plane-update-sf-dmg-area.html

  * igt@kms_psr@fbc-pr-cursor-mmap-gtt:
    - shard-rkl:          [SKIP][401] ([i915#1072] / [i915#9732]) -> [SKIP][402] ([i915#1072] / [i915#14544] / [i915#9732]) +10 other tests skip
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_psr@fbc-pr-cursor-mmap-gtt.html
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_psr@fbc-pr-cursor-mmap-gtt.html

  * igt@kms_psr@fbc-psr2-primary-render:
    - shard-dg1:          [SKIP][403] ([i915#1072] / [i915#9732]) -> [SKIP][404] ([i915#1072] / [i915#4423] / [i915#9732])
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-dg1-17/igt@kms_psr@fbc-psr2-primary-render.html
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-dg1-12/igt@kms_psr@fbc-psr2-primary-render.html

  * igt@kms_psr@psr-cursor-render:
    - shard-rkl:          [SKIP][405] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][406] ([i915#1072] / [i915#9732]) +10 other tests skip
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_psr@psr-cursor-render.html
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_psr@psr-cursor-render.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-rkl:          [SKIP][407] ([i915#15949]) -> [SKIP][408] ([i915#14544] / [i915#15949])
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0:
    - shard-rkl:          [SKIP][409] ([i915#5289]) -> [SKIP][410] ([i915#14544] / [i915#5289])
   [409]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html
   [410]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-0.html

  * igt@kms_tiled_display@basic-test-pattern:
    - shard-rkl:          [SKIP][411] ([i915#14544] / [i915#8623]) -> [SKIP][412] ([i915#8623])
   [411]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-6/igt@kms_tiled_display@basic-test-pattern.html
   [412]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-5/igt@kms_tiled_display@basic-test-pattern.html

  * igt@kms_tiled_display@basic-test-pattern-with-chamelium:
    - shard-rkl:          [SKIP][413] ([i915#8623]) -> [SKIP][414] ([i915#14544] / [i915#8623])
   [413]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
   [414]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html

  * igt@kms_vrr@lobf:
    - shard-rkl:          [SKIP][415] ([i915#11920]) -> [SKIP][416] ([i915#11920] / [i915#14544])
   [415]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_19069/shard-rkl-7/igt@kms_vrr@lobf.html
   [416]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/shard-rkl-6/igt@kms_vrr@lobf.html

  
  [i915#10056]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10056
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
  [i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11920]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11920
  [i915#12276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12276
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
  [i915#12454]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12454
  [i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
  [i915#12712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12712
  [i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
  [i915#13026]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13026
  [i915#13179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13179
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#13390]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13390
  [i915#13398]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13398
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
  [i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
  [i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
  [i915#13781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13781
  [i915#13790]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13790
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14259]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14259
  [i915#14419]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14419
  [i915#14498]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14498
  [i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
  [i915#14586]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14586
  [i915#14600]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14600
  [i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
  [i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
  [i915#15128]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15128
  [i915#15132]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15132
  [i915#15140]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15140
  [i915#15169]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15169
  [i915#15243]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15243
  [i915#15329]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15329
  [i915#15330]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15330
  [i915#15436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15436
  [i915#15458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15458
  [i915#15459]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15459
  [i915#15460]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15460
  [i915#15500]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15500
  [i915#15587]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15587
  [i915#15643]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15643
  [i915#15662]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15662
  [i915#15672]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15672
  [i915#15678]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15678
  [i915#15709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15709
  [i915#15733]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15733
  [i915#15792]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15792
  [i915#15804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15804
  [i915#15815]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15815
  [i915#15816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15816
  [i915#15865]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15865
  [i915#15871]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15871
  [i915#15944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15944
  [i915#15949]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15949
  [i915#15989]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15989
  [i915#15990]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15990
  [i915#16081]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16081
  [i915#16182]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16182
  [i915#16184]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16184
  [i915#16276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16276
  [i915#16361]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16361
  [i915#16420]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16420
  [i915#16471]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16471
  [i915#16479]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16479
  [i915#16593]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16593
  [i915#16599]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16599
  [i915#16600]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16600
  [i915#16644]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16644
  [i915#16680]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16680
  [i915#16685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16685
  [i915#16837]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16837
  [i915#16844]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16844
  [i915#16852]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16852
  [i915#16857]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16857
  [i915#16866]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16866
  [i915#16867]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16867
  [i915#16876]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16876
  [i915#16914]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16914
  [i915#16931]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16931
  [i915#16932]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16932
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#2190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2190
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#2681]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2681
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3299]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3299
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
  [i915#4387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4387
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6113]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6113
  [i915#6230]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6230
  [i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
  [i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
  [i915#6344]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6344
  [i915#6412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6412
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
  [i915#8623]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8623
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#8898]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8898
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
  [i915#9433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9433
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_19069 -> Patchwork_173155v6

  CI-20190529: 20190529
  CI_DRM_19069: c53467440a5196138d2d6610e269a43b6b47bf6b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_9079: 9079
  Patchwork_173155v6: c53467440a5196138d2d6610e269a43b6b47bf6b @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_173155v6/index.html

[-- Attachment #2: Type: text/html, Size: 141341 bytes --]