[PATCH] drm/i915/cmtg: Disable CMTG after PSR exit to avoid disable timeout

[PATCH] drm/i915/cmtg: Disable CMTG after PSR exit to avoid disable timeout

[Animesh Manna]

CMTG is enabled in sync-to-port mode, so its running state (CMTG_STATE)
can only clear while the port is actively timing. In hsw_crtc_disable()
the CMTG was torn down at the very beginning of the sequence, before the
encoders were disabled. At that point PSR may still be active on the eDP,
leaving the port timing generator idle. As a result, after clearing
CMTG_ENABLE the wait for CMTG_STATE to clear never completes and triggers:

  xe 0000:00:02.0: [drm] CMTG: A disable timeout
  WARNING: drivers/gpu/drm/i915/display/intel_cmtg.c:205 intel_cmtg_disable+0x331/0x3d0 [xe]

This is intermittently seen with igt@kms_hdr@bpc-switch-suspend, which
repeatedly cycles the eDP in and out of PSR across suspend/resume.

Move the CMTG disable to after intel_encoders_disable() (so PSR is
exited) but before intel_encoders_post_disable()/intel_dpll_disable(),
so the transcoder timing generator and port PLL are still active while
CMTG_STATE is polled. The ordering requirement of disabling CMTG before
the transcoder and port PLL are brought down is preserved.

Cc: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Cc: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++++----
 1 file changed, 14 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 829d7a411dcc..cc4d20fdda44 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1791,15 +1791,25 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
 		intel_atomic_get_old_crtc_state(state, crtc);
 	struct intel_crtc *pipe_crtc;
 
-	if (crtc->cmtg.enabled && intel_cmtg_is_allowed(old_crtc_state)) {
-		intel_cmtg_set_clk_select(old_crtc_state);
-		intel_cmtg_disable(old_crtc_state);
-	}
 	/*
 	 * FIXME collapse everything to one hook.
 	 * Need care with mst->ddi interactions.
 	 */
 	intel_encoders_disable(state, crtc);
+
+	/*
+	 * Disable CMTG after the encoders are disabled (so PSR is exited) but
+	 * before the transcoder timing generator and port PLL are torn down in
+	 * intel_encoders_post_disable()/intel_dpll_disable(). CMTG is synced to
+	 * the port, so its running state (CMTG_STATE) can only clear while the
+	 * port is actively timing. Doing this while PSR is still active leaves
+	 * the port idle and makes the CMTG_STATE clear wait time out.
+	 */
+	if (crtc->cmtg.enabled && intel_cmtg_is_allowed(old_crtc_state)) {
+		intel_cmtg_set_clk_select(old_crtc_state);
+		intel_cmtg_disable(old_crtc_state);
+	}
+
 	intel_encoders_post_disable(state, crtc);
 
 	intel_dpll_disable(old_crtc_state);
-- 
2.29.0

Re: [PATCH] drm/i915/cmtg: Disable CMTG after PSR exit to avoid disable timeout

[Jani Nikula]

On Fri, 07 Aug 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> CMTG is enabled in sync-to-port mode, so its running state (CMTG_STATE)
> can only clear while the port is actively timing. In hsw_crtc_disable()
> the CMTG was torn down at the very beginning of the sequence, before the
> encoders were disabled. At that point PSR may still be active on the eDP,
> leaving the port timing generator idle. As a result, after clearing
> CMTG_ENABLE the wait for CMTG_STATE to clear never completes and triggers:
>
>   xe 0000:00:02.0: [drm] CMTG: A disable timeout
>   WARNING: drivers/gpu/drm/i915/display/intel_cmtg.c:205 intel_cmtg_disable+0x331/0x3d0 [xe]
>
> This is intermittently seen with igt@kms_hdr@bpc-switch-suspend, which
> repeatedly cycles the eDP in and out of PSR across suspend/resume.
>
> Move the CMTG disable to after intel_encoders_disable() (so PSR is
> exited) but before intel_encoders_post_disable()/intel_dpll_disable(),
> so the transcoder timing generator and port PLL are still active while
> CMTG_STATE is polled. The ordering requirement of disabling CMTG before
> the transcoder and port PLL are brought down is preserved.
>
> Cc: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
> Cc: Uma Shankar <uma.shankar@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>

Fixes: ?
Cc: stable ?

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++++----
>  1 file changed, 14 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 829d7a411dcc..cc4d20fdda44 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -1791,15 +1791,25 @@ static void hsw_crtc_disable(struct intel_atomic_state *state,
>  		intel_atomic_get_old_crtc_state(state, crtc);
>  	struct intel_crtc *pipe_crtc;
>  
> -	if (crtc->cmtg.enabled && intel_cmtg_is_allowed(old_crtc_state)) {
> -		intel_cmtg_set_clk_select(old_crtc_state);
> -		intel_cmtg_disable(old_crtc_state);
> -	}
>  	/*
>  	 * FIXME collapse everything to one hook.
>  	 * Need care with mst->ddi interactions.
>  	 */
>  	intel_encoders_disable(state, crtc);
> +
> +	/*
> +	 * Disable CMTG after the encoders are disabled (so PSR is exited) but
> +	 * before the transcoder timing generator and port PLL are torn down in
> +	 * intel_encoders_post_disable()/intel_dpll_disable(). CMTG is synced to
> +	 * the port, so its running state (CMTG_STATE) can only clear while the
> +	 * port is actively timing. Doing this while PSR is still active leaves
> +	 * the port idle and makes the CMTG_STATE clear wait time out.
> +	 */
> +	if (crtc->cmtg.enabled && intel_cmtg_is_allowed(old_crtc_state)) {
> +		intel_cmtg_set_clk_select(old_crtc_state);
> +		intel_cmtg_disable(old_crtc_state);
> +	}
> +
>  	intel_encoders_post_disable(state, crtc);
>  
>  	intel_dpll_disable(old_crtc_state);

-- 
Jani Nikula, Intel

RE: [PATCH] drm/i915/cmtg: Disable CMTG after PSR exit to avoid disable timeout

[Manna, Animesh]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@linux.intel.com>
> Sent: Friday, August 7, 2026 1:33 PM
> To: Manna, Animesh <animesh.manna@intel.com>; intel-
> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Dibin Moolakadan
> Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>; Shankar,
> Uma <uma.shankar@intel.com>
> Subject: Re: [PATCH] drm/i915/cmtg: Disable CMTG after PSR exit to avoid
> disable timeout
> 
> On Fri, 07 Aug 2026, Animesh Manna <animesh.manna@intel.com> wrote:
> > CMTG is enabled in sync-to-port mode, so its running state
> > (CMTG_STATE) can only clear while the port is actively timing. In
> > hsw_crtc_disable() the CMTG was torn down at the very beginning of the
> > sequence, before the encoders were disabled. At that point PSR may
> > still be active on the eDP, leaving the port timing generator idle. As
> > a result, after clearing CMTG_ENABLE the wait for CMTG_STATE to clear
> never completes and triggers:
> >
> >   xe 0000:00:02.0: [drm] CMTG: A disable timeout
> >   WARNING: drivers/gpu/drm/i915/display/intel_cmtg.c:205
> > intel_cmtg_disable+0x331/0x3d0 [xe]
> >
> > This is intermittently seen with igt@kms_hdr@bpc-switch-suspend, which
> > repeatedly cycles the eDP in and out of PSR across suspend/resume.
> >
> > Move the CMTG disable to after intel_encoders_disable() (so PSR is
> > exited) but before intel_encoders_post_disable()/intel_dpll_disable(),
> > so the transcoder timing generator and port PLL are still active while
> > CMTG_STATE is polled. The ordering requirement of disabling CMTG
> > before the transcoder and port PLL are brought down is preserved.
> >
> > Cc: Dibin Moolakadan Subrahmanian
> > <dibin.moolakadan.subrahmanian@intel.com>
> > Cc: Uma Shankar <uma.shankar@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> 
> Fixes: ?
> Cc: stable ?

Sure, will add in next version.

Regards,
Animesh
> 
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++++----
> >  1 file changed, 14 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 829d7a411dcc..cc4d20fdda44 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -1791,15 +1791,25 @@ static void hsw_crtc_disable(struct
> intel_atomic_state *state,
> >  		intel_atomic_get_old_crtc_state(state, crtc);
> >  	struct intel_crtc *pipe_crtc;
> >
> > -	if (crtc->cmtg.enabled && intel_cmtg_is_allowed(old_crtc_state)) {
> > -		intel_cmtg_set_clk_select(old_crtc_state);
> > -		intel_cmtg_disable(old_crtc_state);
> > -	}
> >  	/*
> >  	 * FIXME collapse everything to one hook.
> >  	 * Need care with mst->ddi interactions.
> >  	 */
> >  	intel_encoders_disable(state, crtc);
> > +
> > +	/*
> > +	 * Disable CMTG after the encoders are disabled (so PSR is exited) but
> > +	 * before the transcoder timing generator and port PLL are torn down
> in
> > +	 * intel_encoders_post_disable()/intel_dpll_disable(). CMTG is
> synced to
> > +	 * the port, so its running state (CMTG_STATE) can only clear while
> the
> > +	 * port is actively timing. Doing this while PSR is still active leaves
> > +	 * the port idle and makes the CMTG_STATE clear wait time out.
> > +	 */
> > +	if (crtc->cmtg.enabled && intel_cmtg_is_allowed(old_crtc_state)) {
> > +		intel_cmtg_set_clk_select(old_crtc_state);
> > +		intel_cmtg_disable(old_crtc_state);
> > +	}
> > +
> >  	intel_encoders_post_disable(state, crtc);
> >
> >  	intel_dpll_disable(old_crtc_state);
> 
> --
> Jani Nikula, Intel

RE: [PATCH] drm/i915/cmtg: Disable CMTG after PSR exit to avoid disable timeout

[Jani Nikula]

On Fri, 07 Aug 2026, "Manna, Animesh" <animesh.manna@intel.com> wrote:
>> -----Original Message-----
>> From: Jani Nikula <jani.nikula@linux.intel.com>
>> Sent: Friday, August 7, 2026 1:33 PM
>> To: Manna, Animesh <animesh.manna@intel.com>; intel-
>> gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
>> Cc: Manna, Animesh <animesh.manna@intel.com>; Dibin Moolakadan
>> Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>; Shankar,
>> Uma <uma.shankar@intel.com>
>> Subject: Re: [PATCH] drm/i915/cmtg: Disable CMTG after PSR exit to avoid
>> disable timeout
>> 
>> On Fri, 07 Aug 2026, Animesh Manna <animesh.manna@intel.com> wrote:
>> > CMTG is enabled in sync-to-port mode, so its running state
>> > (CMTG_STATE) can only clear while the port is actively timing. In
>> > hsw_crtc_disable() the CMTG was torn down at the very beginning of the
>> > sequence, before the encoders were disabled. At that point PSR may
>> > still be active on the eDP, leaving the port timing generator idle. As
>> > a result, after clearing CMTG_ENABLE the wait for CMTG_STATE to clear
>> never completes and triggers:
>> >
>> >   xe 0000:00:02.0: [drm] CMTG: A disable timeout
>> >   WARNING: drivers/gpu/drm/i915/display/intel_cmtg.c:205
>> > intel_cmtg_disable+0x331/0x3d0 [xe]
>> >
>> > This is intermittently seen with igt@kms_hdr@bpc-switch-suspend, which
>> > repeatedly cycles the eDP in and out of PSR across suspend/resume.
>> >
>> > Move the CMTG disable to after intel_encoders_disable() (so PSR is
>> > exited) but before intel_encoders_post_disable()/intel_dpll_disable(),
>> > so the transcoder timing generator and port PLL are still active while
>> > CMTG_STATE is polled. The ordering requirement of disabling CMTG
>> > before the transcoder and port PLL are brought down is preserved.
>> >
>> > Cc: Dibin Moolakadan Subrahmanian
>> > <dibin.moolakadan.subrahmanian@intel.com>
>> > Cc: Uma Shankar <uma.shankar@intel.com>
>> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> 
>> Fixes: ?
>> Cc: stable ?
>
> Sure, will add in next version.

If there is no next version otherwise, you don't have to and should not
send a new version just to amend these trailers. Just reply with them to
the patch.

BR,
Jani.

>
> Regards,
> Animesh
>> 
>> > ---
>> >  drivers/gpu/drm/i915/display/intel_display.c | 18 ++++++++++++++----
>> >  1 file changed, 14 insertions(+), 4 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>> > b/drivers/gpu/drm/i915/display/intel_display.c
>> > index 829d7a411dcc..cc4d20fdda44 100644
>> > --- a/drivers/gpu/drm/i915/display/intel_display.c
>> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> > @@ -1791,15 +1791,25 @@ static void hsw_crtc_disable(struct
>> intel_atomic_state *state,
>> >  		intel_atomic_get_old_crtc_state(state, crtc);
>> >  	struct intel_crtc *pipe_crtc;
>> >
>> > -	if (crtc->cmtg.enabled && intel_cmtg_is_allowed(old_crtc_state)) {
>> > -		intel_cmtg_set_clk_select(old_crtc_state);
>> > -		intel_cmtg_disable(old_crtc_state);
>> > -	}
>> >  	/*
>> >  	 * FIXME collapse everything to one hook.
>> >  	 * Need care with mst->ddi interactions.
>> >  	 */
>> >  	intel_encoders_disable(state, crtc);
>> > +
>> > +	/*
>> > +	 * Disable CMTG after the encoders are disabled (so PSR is exited) but
>> > +	 * before the transcoder timing generator and port PLL are torn down
>> in
>> > +	 * intel_encoders_post_disable()/intel_dpll_disable(). CMTG is
>> synced to
>> > +	 * the port, so its running state (CMTG_STATE) can only clear while
>> the
>> > +	 * port is actively timing. Doing this while PSR is still active leaves
>> > +	 * the port idle and makes the CMTG_STATE clear wait time out.
>> > +	 */
>> > +	if (crtc->cmtg.enabled && intel_cmtg_is_allowed(old_crtc_state)) {
>> > +		intel_cmtg_set_clk_select(old_crtc_state);
>> > +		intel_cmtg_disable(old_crtc_state);
>> > +	}
>> > +
>> >  	intel_encoders_post_disable(state, crtc);
>> >
>> >  	intel_dpll_disable(old_crtc_state);
>> 
>> --
>> Jani Nikula, Intel

-- 
Jani Nikula, Intel

✗ i915.CI.BAT: failure for drm/i915/cmtg: Disable CMTG after PSR exit to avoid disable timeout

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3191 bytes --]

== Series Details ==

Series: drm/i915/cmtg: Disable CMTG after PSR exit to avoid disable timeout
URL   : https://patchwork.freedesktop.org/series/171766/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_18962 -> Patchwork_171766v1
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_171766v1 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_171766v1, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171766v1/index.html

Participating hosts (40 -> 36)
------------------------------

  Missing    (4): bat-dg2-13 bat-dg2-9 fi-snb-2520m bat-adls-6 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_171766v1:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live@requests:
    - bat-atsm-1:         [PASS][1] -> [INCOMPLETE][2] +1 other test incomplete
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18962/bat-atsm-1/igt@i915_selftest@live@requests.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171766v1/bat-atsm-1/igt@i915_selftest@live@requests.html

  
Known issues
------------

  Here are the changes found in Patchwork_171766v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@fbdev@info:
    - fi-hsw-4770:        [PASS][3] -> [SKIP][4] ([i915#1849] / [i915#2582])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18962/fi-hsw-4770/igt@fbdev@info.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171766v1/fi-hsw-4770/igt@fbdev@info.html

  * igt@fbdev@nullptr:
    - fi-hsw-4770:        [PASS][5] -> [SKIP][6] ([i915#2582]) +3 other tests skip
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18962/fi-hsw-4770/igt@fbdev@nullptr.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171766v1/fi-hsw-4770/igt@fbdev@nullptr.html

  * igt@gem_softpin@safe-alignment:
    - fi-hsw-4770:        [PASS][7] -> [FAIL][8] ([i915#15527])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18962/fi-hsw-4770/igt@gem_softpin@safe-alignment.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171766v1/fi-hsw-4770/igt@gem_softpin@safe-alignment.html

  
  [i915#15527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15527
  [i915#1849]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1849
  [i915#2582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2582


Build changes
-------------

  * Linux: CI_DRM_18962 -> Patchwork_171766v1

  CI-20190529: 20190529
  CI_DRM_18962: 01d30c194951b8794c33f0d7f559bc4a1c9b7630 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_9043: 9043
  Patchwork_171766v1: 01d30c194951b8794c33f0d7f559bc4a1c9b7630 @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_171766v1/index.html

[-- Attachment #2: Type: text/html, Size: 3957 bytes --]