From: Swati Sharma <swati2.sharma@intel.com>
To: Matt Roper <matthew.d.roper@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/dsc: Source supports DSC from DISPLAY_VER >= 11
Date: Wed, 2 Nov 2022 14:32:53 +0530 [thread overview]
Message-ID: <27ad74e3-d436-6f74-e3bb-599f960de195@intel.com> (raw)
In-Reply-To: <Y2GNrfJJ/ryBY0+9@mdroper-desk1.amr.corp.intel.com>
Hi Matt,
Yes. Though h/w supports DSC from gen10, DSC is enabled from gen11+ from
driver.
We can see "has_dsc" flag enabled in gen11+.
#define GEN11_FEATURES \
>-------.__runtime.has_dsc = 1, \
Also, in the driver intel_dsc_source_support(), it is
if (DISPLAY_VER(i915) >= 11 && cpu_transcoder != TRANSCODER_A)
return true;
So, we should align DISPLAY_VER check according to DSC enablement
from driver.
On 02-Nov-22 2:50 AM, Matt Roper wrote:
> On Tue, Nov 01, 2022 at 01:29:27PM +0530, Swati Sharma wrote:
>> i915 driver supports DSC from DISPLAY_VER >= 11. Fix it.
>
> Bspec 19713 indicates that GLK (i.e., our only display version 10
> platform) does support DSC. Are you saying that there's other GLK
> enablement missing in the driver right now that prevents DSC from
> working?
>
>
> Matt
>
>>
>> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 7400d6b4c587..02e64f0284d8 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -1012,7 +1012,7 @@ intel_dp_mode_valid(struct drm_connector *_connector,
>> * Output bpp is stored in 6.4 format so right shift by 4 to get the
>> * integer value since we support only integer values of bpp.
>> */
>> - if (DISPLAY_VER(dev_priv) >= 10 &&
>> + if (DISPLAY_VER(dev_priv) >= 11 &&
>> drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) {
>> /*
>> * TBD pass the connector BPC,
>> @@ -2906,7 +2906,7 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp)
>> intel_dp_set_max_sink_lane_count(intel_dp);
>>
>> /* Read the eDP DSC DPCD registers */
>> - if (DISPLAY_VER(dev_priv) >= 10)
>> + if (DISPLAY_VER(dev_priv) >= 11)
>> intel_dp_get_dsc_sink_cap(intel_dp);
>>
>> /*
>> --
>> 2.25.1
>>
>
--
~Swati Sharma
next prev parent reply other threads:[~2022-11-02 9:03 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-01 7:59 [Intel-gfx] [PATCH] drm/i915/dsc: Source supports DSC from DISPLAY_VER >= 11 Swati Sharma
2022-11-01 8:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2022-11-01 10:22 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-11-01 21:20 ` [Intel-gfx] [PATCH] " Matt Roper
2022-11-02 9:02 ` Swati Sharma [this message]
2022-11-02 9:32 ` Jani Nikula
2022-11-03 6:05 ` Swati Sharma
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