From: "Hogander, Jouni" <jouni.hogander@intel.com>
To: "intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>,
"Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Cc: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>,
"Manna, Animesh" <animesh.manna@intel.com>
Subject: Re: [PATCH 07/10] drm/i915/display: Introduce dp/psr_compute_config_late()
Date: Wed, 15 Oct 2025 07:59:25 +0000 [thread overview]
Message-ID: <29e8bf35563d3e9258996cca132142c22699d1e9.camel@intel.com> (raw)
In-Reply-To: <20251015072217.1710717-8-ankit.k.nautiyal@intel.com>
On Wed, 2025-10-15 at 12:52 +0530, Ankit Nautiyal wrote:
> Introduce intel_dp_compute_config_late() to handle late-stage
> configuration checks for DP/eDP features. For now, it paves path for
> psr_compute_config_late() to handle psr parameters that need to be
> computed late.
>
> Move the handling of psr_flag for Wa_18037818876 and setting of non-
> psr
> pipes to intel_psr_compute_config_late() as these are the last things
> to be configured for PSR features.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 3 +++
> drivers/gpu/drm/i915/display/intel_dp.c | 9 +++++++++
> drivers/gpu/drm/i915/display/intel_dp.h | 3 +++
> drivers/gpu/drm/i915/display/intel_psr.c | 24 +++++++++++++++-------
> --
> drivers/gpu/drm/i915/display/intel_psr.h | 2 ++
> 5 files changed, 32 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> b/drivers/gpu/drm/i915/display/intel_ddi.c
> index c09aa759f4d4..94c593bbedf4 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4560,6 +4560,9 @@ static int intel_ddi_compute_config_late(struct
> intel_encoder *encoder,
> struct drm_connector *connector = conn_state->connector;
> u8 port_sync_transcoders = 0;
>
> + if (intel_crtc_has_dp_encoder(crtc_state))
> + intel_dp_compute_config_late(encoder, crtc_state,
> conn_state);
> +
> drm_dbg_kms(display->drm, "[ENCODER:%d:%s] [CRTC:%d:%s]\n",
> encoder->base.base.id, encoder->base.name,
> crtc_state->uapi.crtc->base.id, crtc_state-
> >uapi.crtc->name);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index a723e846321f..e481ff4c4959 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6979,3 +6979,12 @@ void intel_dp_mst_resume(struct intel_display
> *display)
> }
> }
> }
> +
> +void intel_dp_compute_config_late(struct intel_encoder *encoder,
> + struct intel_crtc_state
> *crtc_state,
> + struct drm_connector_state
> *conn_state)
> +{
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> +
> + intel_psr_compute_config_late(intel_dp, crtc_state);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h
> b/drivers/gpu/drm/i915/display/intel_dp.h
> index b379443e0211..0d9573ca44cb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -218,5 +218,8 @@ int intel_dp_compute_min_hblank(struct
> intel_crtc_state *crtc_state,
> int intel_dp_dsc_bpp_step_x16(const struct intel_connector
> *connector);
> void intel_dp_dpcd_set_probe(struct intel_dp *intel_dp, bool
> force_on_external);
> bool intel_dp_in_hdr_mode(const struct drm_connector_state
> *conn_state);
> +void intel_dp_compute_config_late(struct intel_encoder *encoder,
> + struct intel_crtc_state
> *crtc_state,
> + struct drm_connector_state
> *conn_state);
>
> #endif /* __INTEL_DP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index e97dcfa7673c..383e6dc1ed63 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1785,15 +1785,6 @@ void intel_psr_compute_config(struct intel_dp
> *intel_dp,
> return;
>
> crtc_state->has_sel_update =
> intel_sel_update_config_valid(intel_dp, crtc_state);
> -
> - /* Wa_18037818876 */
> - if (intel_psr_needs_wa_18037818876(intel_dp, crtc_state)) {
> - crtc_state->has_psr = false;
> - drm_dbg_kms(display->drm,
> - "PSR disabled to workaround PSR FSM hang
> issue\n");
> - }
> -
> - intel_psr_set_non_psr_pipes(intel_dp, crtc_state);
> }
>
> void intel_psr_get_config(struct intel_encoder *encoder,
> @@ -4355,3 +4346,18 @@ bool intel_psr_needs_alpm_aux_less(struct
> intel_dp *intel_dp,
> {
> return intel_dp_is_edp(intel_dp) && crtc_state-
> >has_panel_replay;
> }
> +
> +void intel_psr_compute_config_late(struct intel_dp *intel_dp,
> + struct intel_crtc_state
> *crtc_state)
> +{
> + struct intel_display *display = to_intel_display(intel_dp);
> +
> + /* Wa_18037818876 */
> + if (intel_psr_needs_wa_18037818876(intel_dp, crtc_state)) {
> + crtc_state->has_psr = false;
> + drm_dbg_kms(display->drm,
> + "PSR disabled to workaround PSR FSM hang
> issue\n");
> + }
> +
> + intel_psr_set_non_psr_pipes(intel_dp, crtc_state);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index 9147996d6c9e..b17ce312dc37 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -83,5 +83,7 @@ void intel_psr_debugfs_register(struct
> intel_display *display);
> bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct
> intel_crtc_state *crtc_state);
> bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
> const struct intel_crtc_state
> *crtc_state);
> +void intel_psr_compute_config_late(struct intel_dp *intel_dp,
> + struct intel_crtc_state
> *crtc_state);
>
> #endif /* __INTEL_PSR_H__ */
next prev parent reply other threads:[~2025-10-15 7:59 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-10-15 7:22 [PATCH 00/10] Preparatory patches for guardband optimization Ankit Nautiyal
2025-10-15 7:22 ` [PATCH 01/10] drm/i915/vrr: Use crtc_vsync_start/end for computing vrr.vsync_start/end Ankit Nautiyal
2025-10-15 7:22 ` [PATCH 02/10] drm/i915/display: Move intel_dpll_crtc_compute_clock early Ankit Nautiyal
2025-10-15 7:22 ` [PATCH 03/10] drm/i915/vrr: s/intel_vrr_compute_config_late/intel_vrr_compute_guardband Ankit Nautiyal
2025-10-15 7:22 ` [PATCH 04/10] drm/i915/vblank: Add helper to get correct vblank length Ankit Nautiyal
2025-10-15 7:22 ` [PATCH 05/10] drm/i915/psr: Consider SCL lines when validating vblank for wake latency Ankit Nautiyal
2025-10-15 7:22 ` [PATCH 06/10] drm/i915/psr: Introduce helper intel_psr_set_non_psr_pipes() Ankit Nautiyal
2025-10-15 7:57 ` Hogander, Jouni
2025-10-15 7:22 ` [PATCH 07/10] drm/i915/display: Introduce dp/psr_compute_config_late() Ankit Nautiyal
2025-10-15 7:59 ` Hogander, Jouni [this message]
2025-10-15 7:22 ` [PATCH 08/10] drm/i915/psr: Check if final vblank is sufficient for PSR features Ankit Nautiyal
2025-10-15 8:23 ` Hogander, Jouni
2025-10-15 8:33 ` Hogander, Jouni
2025-10-15 9:14 ` Ankit Nautiyal
2025-10-15 9:32 ` Hogander, Jouni
2025-10-15 7:22 ` [PATCH 09/10] drm/i915/display: Add vblank_start adjustment logic for always-on VRR TG Ankit Nautiyal
2025-10-15 13:54 ` Ville Syrjälä
2025-10-15 7:22 ` [PATCH 10/10] drm/i915/display: Prepare for vblank_delay for LRR Ankit Nautiyal
2025-10-15 15:00 ` Ville Syrjälä
2025-10-15 11:07 ` ✓ i915.CI.BAT: success for Preparatory patches for guardband optimization (rev7) Patchwork
2025-10-15 17:12 ` ✗ i915.CI.Full: failure " Patchwork
2025-10-16 5:24 ` ✓ i915.CI.Full: success " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2025-10-16 5:54 [PATCH 00/10] Preparatory patches for guardband optimization Ankit Nautiyal
2025-10-16 5:54 ` [PATCH 07/10] drm/i915/display: Introduce dp/psr_compute_config_late() Ankit Nautiyal
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