* [Intel-gfx] [PATCH v4 01/30] drm/i915/xelpdp: Add XE_LPDP_FEATURES
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 02/30] drm/i915/lnl: Add display definitions Lucas De Marchi
` (31 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Matt Roper, Lucas De Marchi, intel-xe
Add a FEATURES macro for XE_LPD+ as this is expected to be the baseline
for Xe2_LPD and will allow to see the delta more easily.
v2: Move everything from xe_lpdp_display to the new macro and remove
the version setting: it's not needed with GMD_ID.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
.../drm/i915/display/intel_display_device.c | 57 +++++++++++++++----
1 file changed, 46 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 4a6c4ee503b2..b572ca16647d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -710,18 +710,53 @@ static const struct intel_display_device_info xe_hpd_display = {
BIT(PORT_TC1),
};
-static const struct intel_display_device_info xe_lpdp_display = {
- XE_LPD_FEATURES,
- .has_cdclk_crawl = 1,
- .has_cdclk_squash = 1,
+#define XE_LPDP_FEATURES \
+ .abox_mask = GENMASK(1, 0), \
+ .color = { \
+ .degamma_lut_size = 129, .gamma_lut_size = 1024, \
+ .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING | \
+ DRM_COLOR_LUT_EQUAL_CHANNELS, \
+ }, \
+ .dbuf.size = 4096, \
+ .dbuf.slice_mask = BIT(DBUF_S1) | BIT(DBUF_S2) | BIT(DBUF_S3) | \
+ BIT(DBUF_S4), \
+ .has_cdclk_crawl = 1, \
+ .has_cdclk_squash = 1, \
+ .has_ddi = 1, \
+ .has_dp_mst = 1, \
+ .has_dsb = 1, \
+ .has_fpga_dbg = 1, \
+ .has_hotplug = 1, \
+ .has_ipc = 1, \
+ .has_psr = 1, \
+ .pipe_offsets = { \
+ [TRANSCODER_A] = PIPE_A_OFFSET, \
+ [TRANSCODER_B] = PIPE_B_OFFSET, \
+ [TRANSCODER_C] = PIPE_C_OFFSET, \
+ [TRANSCODER_D] = PIPE_D_OFFSET, \
+ }, \
+ .trans_offsets = { \
+ [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
+ [TRANSCODER_B] = TRANSCODER_B_OFFSET, \
+ [TRANSCODER_C] = TRANSCODER_C_OFFSET, \
+ [TRANSCODER_D] = TRANSCODER_D_OFFSET, \
+ }, \
+ TGL_CURSOR_OFFSETS, \
+ \
+ .__runtime_defaults.cpu_transcoder_mask = \
+ BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+ BIT(TRANSCODER_C) | BIT(TRANSCODER_D), \
+ .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B), \
+ .__runtime_defaults.has_dmc = 1, \
+ .__runtime_defaults.has_dsc = 1, \
+ .__runtime_defaults.has_hdcp = 1, \
+ .__runtime_defaults.pipe_mask = \
+ BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
+ .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | \
+ BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4)
- .__runtime_defaults.ip.ver = 14,
- .__runtime_defaults.fbc_mask = BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B),
- .__runtime_defaults.cpu_transcoder_mask =
- BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
- BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
- .__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) |
- BIT(PORT_TC1) | BIT(PORT_TC2) | BIT(PORT_TC3) | BIT(PORT_TC4),
+static const struct intel_display_device_info xe_lpdp_display = {
+ XE_LPDP_FEATURES,
};
/*
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 02/30] drm/i915/lnl: Add display definitions
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 01/30] drm/i915/xelpdp: Add XE_LPDP_FEATURES Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 03/30] drm/i915/xe2lpd: FBC is now supported on all pipes Lucas De Marchi
` (30 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx
Cc: Matt Roper, Lucas De Marchi, intel-xe, Balasubramani Vivekanandan
From: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Add Lunar Lake platform definitions for i915 display. The support for
LNL will be added to the xe driver, with i915 only driving the display
side. Xe2 display is derived from the Xe_LPD+ IP; additional feature
deltas will be introduced in subsequent patches, so here it's just
adding a separate xe2_lpd_display struct.
v2: Use a LPDP_FEATURES macro (Matt Roper)
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_device.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index b572ca16647d..5d6d771791df 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -759,6 +759,10 @@ static const struct intel_display_device_info xe_lpdp_display = {
XE_LPDP_FEATURES,
};
+static const struct intel_display_device_info xe2_lpd_display = {
+ XE_LPDP_FEATURES,
+};
+
/*
* Separate detection for no display cases to keep the display id array simple.
*
@@ -838,6 +842,7 @@ static const struct {
const struct intel_display_device_info *display;
} gmdid_display_map[] = {
{ 14, 0, &xe_lpdp_display },
+ { 20, 0, &xe2_lpd_display },
};
static const struct intel_display_device_info *
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 03/30] drm/i915/xe2lpd: FBC is now supported on all pipes
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 01/30] drm/i915/xelpdp: Add XE_LPDP_FEATURES Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 02/30] drm/i915/lnl: Add display definitions Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 04/30] drm/i915/display: Remove FBC capability from fused off pipes Lucas De Marchi
` (29 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Matt Roper, intel-xe
From: Matt Roper <matthew.d.roper@intel.com>
FBC is no longer limited by pipe: add the defines for pipes B and C that
will be used by platforms supporting FBC on such pipes.
Bspec: 68881, 68904
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_device.c | 4 ++++
drivers/gpu/drm/i915/display/intel_fbc.h | 2 ++
2 files changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 5d6d771791df..5f14f9e8ca88 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -761,6 +761,10 @@ static const struct intel_display_device_info xe_lpdp_display = {
static const struct intel_display_device_info xe2_lpd_display = {
XE_LPDP_FEATURES,
+
+ .__runtime_defaults.fbc_mask =
+ BIT(INTEL_FBC_A) | BIT(INTEL_FBC_B) |
+ BIT(INTEL_FBC_C) | BIT(INTEL_FBC_D),
};
/*
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.h b/drivers/gpu/drm/i915/display/intel_fbc.h
index 4adb98afe6ff..6720ec8ee8a2 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.h
+++ b/drivers/gpu/drm/i915/display/intel_fbc.h
@@ -20,6 +20,8 @@ struct intel_plane_state;
enum intel_fbc_id {
INTEL_FBC_A,
INTEL_FBC_B,
+ INTEL_FBC_C,
+ INTEL_FBC_D,
I915_MAX_FBCS,
};
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 04/30] drm/i915/display: Remove FBC capability from fused off pipes
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (2 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 03/30] drm/i915/xe2lpd: FBC is now supported on all pipes Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 05/30] drm/i915: Re-order if/else ladder in intel_detect_pch() Lucas De Marchi
` (28 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Matt Roper, intel-xe
From: Clint Taylor <clinton.a.taylor@intel.com>
If a particular pipe is disabled by fuse also remove the FBC for that
pipe.
Bspec: 69464
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_device.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index 5f14f9e8ca88..a6a18eae7ae8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -1033,16 +1033,19 @@ void intel_display_device_info_runtime_init(struct drm_i915_private *i915)
if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
display_runtime->pipe_mask &= ~BIT(PIPE_B);
display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
+ display_runtime->fbc_mask &= ~BIT(INTEL_FBC_B);
}
if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
display_runtime->pipe_mask &= ~BIT(PIPE_C);
display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
+ display_runtime->fbc_mask &= ~BIT(INTEL_FBC_C);
}
if (DISPLAY_VER(i915) >= 12 &&
(dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
display_runtime->pipe_mask &= ~BIT(PIPE_D);
display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
+ display_runtime->fbc_mask &= ~BIT(INTEL_FBC_D);
}
if (!display_runtime->pipe_mask)
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 05/30] drm/i915: Re-order if/else ladder in intel_detect_pch()
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (3 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 04/30] drm/i915/display: Remove FBC capability from fused off pipes Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 06/30] drm/i915/xe2lpd: Add fake PCH Lucas De Marchi
` (27 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Matt Roper, Lucas De Marchi, intel-xe
Follow the convention of checking the last platform first and reword the
comment to convey there are more platforms than just DG1.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/soc/intel_pch.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c
index 19a8f27c404e..dfffdfa50b97 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.c
+++ b/drivers/gpu/drm/i915/soc/intel_pch.c
@@ -218,13 +218,16 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
unsigned short id;
enum intel_pch pch_type;
- /* DG1 has south engine display on the same PCI device */
- if (IS_DG1(dev_priv)) {
- dev_priv->pch_type = PCH_DG1;
- return;
- } else if (IS_DG2(dev_priv)) {
+ /*
+ * South display engine on the same PCI device: just assign the fake
+ * PCH.
+ */
+ if (IS_DG2(dev_priv)) {
dev_priv->pch_type = PCH_DG2;
return;
+ } else if (IS_DG1(dev_priv)) {
+ dev_priv->pch_type = PCH_DG1;
+ return;
}
/*
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 06/30] drm/i915/xe2lpd: Add fake PCH
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (4 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 05/30] drm/i915: Re-order if/else ladder in intel_detect_pch() Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 07/30] drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation Lucas De Marchi
` (26 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Matt Roper, Lucas De Marchi, intel-xe
From: Gustavo Sousa <gustavo.sousa@intel.com>
Xe2_LPD doesn't have south display engine on a PCH, it's actually
on the SoC die (while north display engine is on compute die). As
such it makes no sense to go through the PCI devices looking for
an ISA bridge. The approach used by BXT/GLK can't be used here since
leaving it with PCH_NONE would mean taking the wrong code paths.
For the places we currently use a PCH check, it's enough for now to just
check the north display version. Use that to define a fake PCH to be
used across the driver. Eventually these PCH checks may need to be
re-designed as this is already the third platform using/needing a
fake PCH.
v2: Match on display IP version rather than on platform (Matt Roper)
v3: Extend and clarify commit message (Matt Roper / Ville)
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/soc/intel_pch.c | 5 ++++-
drivers/gpu/drm/i915/soc/intel_pch.h | 2 ++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/soc/intel_pch.c b/drivers/gpu/drm/i915/soc/intel_pch.c
index dfffdfa50b97..240beafb38ed 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.c
+++ b/drivers/gpu/drm/i915/soc/intel_pch.c
@@ -222,7 +222,10 @@ void intel_detect_pch(struct drm_i915_private *dev_priv)
* South display engine on the same PCI device: just assign the fake
* PCH.
*/
- if (IS_DG2(dev_priv)) {
+ if (DISPLAY_VER(dev_priv) >= 20) {
+ dev_priv->pch_type = PCH_LNL;
+ return;
+ } else if (IS_DG2(dev_priv)) {
dev_priv->pch_type = PCH_DG2;
return;
} else if (IS_DG1(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/soc/intel_pch.h b/drivers/gpu/drm/i915/soc/intel_pch.h
index 32aff5a70d04..1b03ea60a7a8 100644
--- a/drivers/gpu/drm/i915/soc/intel_pch.h
+++ b/drivers/gpu/drm/i915/soc/intel_pch.h
@@ -30,6 +30,7 @@ enum intel_pch {
/* Fake PCHs, functionality handled on the same PCI dev */
PCH_DG1 = 1024,
PCH_DG2,
+ PCH_LNL,
};
#define INTEL_PCH_DEVICE_ID_MASK 0xff80
@@ -66,6 +67,7 @@ enum intel_pch {
#define INTEL_PCH_TYPE(dev_priv) ((dev_priv)->pch_type)
#define INTEL_PCH_ID(dev_priv) ((dev_priv)->pch_id)
+#define HAS_PCH_LNL(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_LNL)
#define HAS_PCH_MTP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_MTP)
#define HAS_PCH_DG2(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
#define HAS_PCH_ADP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 07/30] drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (5 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 06/30] drm/i915/xe2lpd: Add fake PCH Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 08/30] drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST Lucas De Marchi
` (25 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Matt Roper, intel-xe
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
We now start calculating relative plane data rate for cursor plane as
well, as instructed by BSpec and also treat cursor plane same way as
other planes, when doing allocation, i.e not using fixed allocation for
cursor anymore.
Bspec: 68907
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../gpu/drm/i915/display/intel_atomic_plane.c | 6 +++---
drivers/gpu/drm/i915/display/skl_watermark.c | 16 +++++++++-------
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 60a492e186ab..d7a0bd686e49 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -214,9 +214,6 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
int width, height;
unsigned int rel_data_rate;
- if (plane->id == PLANE_CURSOR)
- return 0;
-
if (!plane_state->uapi.visible)
return 0;
@@ -244,6 +241,9 @@ intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
rel_data_rate = width * height * fb->format->cpp[color_plane];
+ if (plane->id == PLANE_CURSOR)
+ return rel_data_rate;
+
return intel_adjusted_rate(&plane_state->uapi.src,
&plane_state->uapi.dst,
rel_data_rate);
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 063929a42a42..64a122d3c9c0 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -1367,7 +1367,7 @@ skl_total_relative_data_rate(const struct intel_crtc_state *crtc_state)
u64 data_rate = 0;
for_each_plane_id_on_crtc(crtc, plane_id) {
- if (plane_id == PLANE_CURSOR)
+ if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
continue;
data_rate += crtc_state->rel_data_rate[plane_id];
@@ -1514,10 +1514,12 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
return 0;
/* Allocate fixed number of blocks for cursor. */
- cursor_size = skl_cursor_allocation(crtc_state, num_active);
- iter.size -= cursor_size;
- skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
- alloc->end - cursor_size, alloc->end);
+ if (DISPLAY_VER(i915) < 20) {
+ cursor_size = skl_cursor_allocation(crtc_state, num_active);
+ iter.size -= cursor_size;
+ skl_ddb_entry_init(&crtc_state->wm.skl.plane_ddb[PLANE_CURSOR],
+ alloc->end - cursor_size, alloc->end);
+ }
iter.data_rate = skl_total_relative_data_rate(crtc_state);
@@ -1531,7 +1533,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
const struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
- if (plane_id == PLANE_CURSOR) {
+ if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20) {
const struct skl_ddb_entry *ddb =
&crtc_state->wm.skl.plane_ddb[plane_id];
@@ -1579,7 +1581,7 @@ skl_crtc_allocate_plane_ddb(struct intel_atomic_state *state,
const struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
- if (plane_id == PLANE_CURSOR)
+ if (plane_id == PLANE_CURSOR && DISPLAY_VER(i915) < 20)
continue;
if (DISPLAY_VER(i915) < 11 &&
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 08/30] drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (6 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 07/30] drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 09/30] drm/i915/xe2lpd: Register DE_RRMR has been removed Lucas De Marchi
` (24 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Matt Roper, intel-xe
From: Matt Roper <matthew.d.roper@intel.com>
Since Xe2LPD technically has FlatCCS, it doesn't have AuxCCS registers
like PLANE_AUX_DIST. However we currently have HAS_FLAT_CCS hardcoded
to 0 since compression isn't ready; we need to make sure this doesn't
cause the display code to go back to trying to write this register.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
drivers/gpu/drm/i915/display/skl_universal_plane.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 007a0bcb3f93..2a30b8aa2994 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -1247,7 +1247,7 @@ icl_plane_update_noarm(struct intel_plane *plane,
}
/* FLAT CCS doesn't need to program AUX_DIST */
- if (!HAS_FLAT_CCS(dev_priv))
+ if (!HAS_FLAT_CCS(dev_priv) && DISPLAY_VER(dev_priv) < 20)
intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
skl_plane_aux_dist(plane_state, color_plane));
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 09/30] drm/i915/xe2lpd: Register DE_RRMR has been removed
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (7 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 08/30] drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 10/30] drm/i915/display: Consolidate saved port bits in intel_digital_port Lucas De Marchi
` (23 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Matt Roper, intel-xe
From: Clint Taylor <clinton.a.taylor@intel.com>
Do not read DE_RRMR register after display version 20. This register
contains display state information during GFX state dumps.
Bspec: 69456
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/i915_gpu_error.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c
index 4008bb09fdb5..a28681c15354 100644
--- a/drivers/gpu/drm/i915/i915_gpu_error.c
+++ b/drivers/gpu/drm/i915/i915_gpu_error.c
@@ -1757,7 +1757,7 @@ static void gt_record_display_regs(struct intel_gt_coredump *gt)
struct intel_uncore *uncore = gt->_gt->uncore;
struct drm_i915_private *i915 = uncore->i915;
- if (GRAPHICS_VER(i915) >= 6)
+ if (DISPLAY_VER(i915) >= 6 && DISPLAY_VER(i915) < 20)
gt->derrmr = intel_uncore_read(uncore, DERRMR);
if (GRAPHICS_VER(i915) >= 8)
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 10/30] drm/i915/display: Consolidate saved port bits in intel_digital_port
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (8 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 09/30] drm/i915/xe2lpd: Register DE_RRMR has been removed Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 19:50 ` [Intel-gfx] [Intel-xe] " Matt Roper
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 11/30] drm/i915/display: Rename intel_dp->DP Lucas De Marchi
` (22 subsequent siblings)
32 siblings, 1 reply; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, intel-xe
From: Clint Taylor <clinton.a.taylor@intel.com>
We use multiple variables for HDMI and DisplayPort to store the value of
DDI_BUF_CTL register (now called DDI_CTL_DE in the spec). Consolidate it
to just one in struct intel_digital_port. This is a preparation step for
future changes in D2D enable/disable sequence for xe2lpd that need to
save some additional bits.
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Gustavo Sousa <gustavo.sousa@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 36 +++++++++++-------------
drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
2 files changed, 18 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 4668de45d6fe..29c9386659ff 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -325,26 +325,25 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
enum phy phy = intel_port_to_phy(i915, encoder->port);
/* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
- intel_dp->DP = dig_port->saved_port_bits |
+ dig_port->saved_port_bits |=
DDI_PORT_WIDTH(crtc_state->lane_count) |
DDI_BUF_TRANS_SELECT(0);
if (DISPLAY_VER(i915) >= 14) {
if (intel_dp_is_uhbr(crtc_state))
- intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
+ dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_40BIT;
else
- intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
+ dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_10BIT;
}
if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
- intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
+ dig_port->saved_port_bits |= ddi_buf_phy_link_rate(crtc_state->port_clock);
if (!intel_tc_port_in_tbt_alt_mode(dig_port))
- intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+ dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
}
}
@@ -1450,7 +1449,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
int level = intel_ddi_level(encoder, crtc_state, 0);
enum port port = encoder->port;
u32 signal_levels;
@@ -1467,10 +1466,10 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
signal_levels);
- intel_dp->DP &= ~DDI_BUF_EMP_MASK;
- intel_dp->DP |= signal_levels;
+ dig_port->saved_port_bits &= ~DDI_BUF_EMP_MASK;
+ dig_port->saved_port_bits |= signal_levels;
- intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
+ intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
}
@@ -3145,7 +3144,6 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
struct drm_connector *connector = conn_state->connector;
enum port port = encoder->port;
enum phy phy = intel_port_to_phy(dev_priv, port);
- u32 buf_ctl;
if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
crtc_state->hdmi_high_tmds_clock_ratio,
@@ -3211,7 +3209,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
* is filled with lane count, already set in the crtc_state.
* The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
*/
- buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
+ dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
if (DISPLAY_VER(dev_priv) >= 14) {
u8 lane_count = mtl_get_port_width(crtc_state->lane_count);
u32 port_buf = 0;
@@ -3224,13 +3222,13 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
- buf_ctl |= DDI_PORT_WIDTH(lane_count);
+ dig_port->saved_port_bits |= DDI_PORT_WIDTH(lane_count);
} else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
- buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
+ dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
}
- intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
+ intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
intel_wait_ddi_buf_active(dev_priv, port);
@@ -3448,8 +3446,8 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
mtl_port_buf_ctl_program(encoder, crtc_state);
/* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */
- intel_dp->DP |= DDI_BUF_CTL_ENABLE;
- intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
+ dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
+ intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
/* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */
@@ -3499,8 +3497,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
(intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port)))
adlp_tbt_to_dp_alt_switch_wa(encoder);
- intel_dp->DP |= DDI_BUF_CTL_ENABLE;
- intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
+ dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
+ intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
intel_wait_ddi_buf_active(dev_priv, port);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 189c5737e63a..2346cd32f5a7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6025,7 +6025,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
intel_dp->pps.active_pipe = INVALID_PIPE;
/* Preserve the current hw state. */
- intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
+ dig_port->saved_port_bits = intel_de_read(dev_priv, intel_dp->output_reg);
intel_dp->attached_connector = intel_connector;
if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [Intel-xe] [PATCH v4 10/30] drm/i915/display: Consolidate saved port bits in intel_digital_port
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 10/30] drm/i915/display: Consolidate saved port bits in intel_digital_port Lucas De Marchi
@ 2023-09-15 19:50 ` Matt Roper
2023-09-18 21:06 ` Lucas De Marchi
0 siblings, 1 reply; 40+ messages in thread
From: Matt Roper @ 2023-09-15 19:50 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, intel-xe
On Fri, Sep 15, 2023 at 10:46:31AM -0700, Lucas De Marchi wrote:
> From: Clint Taylor <clinton.a.taylor@intel.com>
>
> We use multiple variables for HDMI and DisplayPort to store the value of
> DDI_BUF_CTL register (now called DDI_CTL_DE in the spec). Consolidate it
> to just one in struct intel_digital_port. This is a preparation step for
> future changes in D2D enable/disable sequence for xe2lpd that need to
> save some additional bits.
>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_ddi.c | 36 +++++++++++-------------
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> 2 files changed, 18 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 4668de45d6fe..29c9386659ff 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -325,26 +325,25 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> enum phy phy = intel_port_to_phy(i915, encoder->port);
>
> /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
> - intel_dp->DP = dig_port->saved_port_bits |
> + dig_port->saved_port_bits |=
Before this patch, saved_port_bits was a copy of DDI_BUF_PORT_REVERSAL
and DDI_A_4_LANES, either based on a value we readout from hardware at
startup, or based on VBT settings. So it was a value of some
fundamental settings that we "saved" once at startup time and could then
just re-use thereafter.
If we're going to start saving per-modeset information (such as lane
count and link rate), then that's a pretty fundamental change to the
purpose of this field, and "saved_port_bits" doesn't really feel like an
appropriate name anymore. We should probably rename it and add some
documentation on the field explaining exactly what its purpose is and
how/when it gets updated.
> DDI_PORT_WIDTH(crtc_state->lane_count) |
> DDI_BUF_TRANS_SELECT(0);
>
> if (DISPLAY_VER(i915) >= 14) {
> if (intel_dp_is_uhbr(crtc_state))
> - intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
> + dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_40BIT;
> else
> - intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
> + dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_10BIT;
> }
>
> if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
> - intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
> + dig_port->saved_port_bits |= ddi_buf_phy_link_rate(crtc_state->port_clock);
> if (!intel_tc_port_in_tbt_alt_mode(dig_port))
> - intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> + dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> }
> }
>
> @@ -1450,7 +1449,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> int level = intel_ddi_level(encoder, crtc_state, 0);
> enum port port = encoder->port;
> u32 signal_levels;
> @@ -1467,10 +1466,10 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
> drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
> signal_levels);
>
> - intel_dp->DP &= ~DDI_BUF_EMP_MASK;
> - intel_dp->DP |= signal_levels;
> + dig_port->saved_port_bits &= ~DDI_BUF_EMP_MASK;
> + dig_port->saved_port_bits |= signal_levels;
>
> - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
> }
>
> @@ -3145,7 +3144,6 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
> struct drm_connector *connector = conn_state->connector;
> enum port port = encoder->port;
> enum phy phy = intel_port_to_phy(dev_priv, port);
> - u32 buf_ctl;
>
> if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
> crtc_state->hdmi_high_tmds_clock_ratio,
> @@ -3211,7 +3209,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
> * is filled with lane count, already set in the crtc_state.
> * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
> */
> - buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
> + dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> if (DISPLAY_VER(dev_priv) >= 14) {
> u8 lane_count = mtl_get_port_width(crtc_state->lane_count);
> u32 port_buf = 0;
> @@ -3224,13 +3222,13 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
> intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
> XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
>
> - buf_ctl |= DDI_PORT_WIDTH(lane_count);
> + dig_port->saved_port_bits |= DDI_PORT_WIDTH(lane_count);
> } else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
> drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
> - buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> + dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> }
>
> - intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
> + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
>
> intel_wait_ddi_buf_active(dev_priv, port);
>
> @@ -3448,8 +3446,8 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
> mtl_port_buf_ctl_program(encoder, crtc_state);
>
> /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */
> - intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> + dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
>
> /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */
> @@ -3499,8 +3497,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
> (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port)))
> adlp_tbt_to_dp_alt_switch_wa(encoder);
>
> - intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> + dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
>
> intel_wait_ddi_buf_active(dev_priv, port);
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 189c5737e63a..2346cd32f5a7 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6025,7 +6025,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
> intel_dp->pps.active_pipe = INVALID_PIPE;
>
> /* Preserve the current hw state. */
> - intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
> + dig_port->saved_port_bits = intel_de_read(dev_priv, intel_dp->output_reg);
Isn't this going to potentially clobber the lane reversal setting we
determined from the VBT near the beginning of intel_ddi_init()?
Matt
> intel_dp->attached_connector = intel_connector;
>
> if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [Intel-xe] [PATCH v4 10/30] drm/i915/display: Consolidate saved port bits in intel_digital_port
2023-09-15 19:50 ` [Intel-gfx] [Intel-xe] " Matt Roper
@ 2023-09-18 21:06 ` Lucas De Marchi
2023-09-18 22:22 ` Taylor, Clinton A
2023-09-18 22:43 ` Matt Roper
0 siblings, 2 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-18 21:06 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, intel-xe
On Fri, Sep 15, 2023 at 12:50:41PM -0700, Matt Roper wrote:
>On Fri, Sep 15, 2023 at 10:46:31AM -0700, Lucas De Marchi wrote:
>> From: Clint Taylor <clinton.a.taylor@intel.com>
>>
>> We use multiple variables for HDMI and DisplayPort to store the value of
>> DDI_BUF_CTL register (now called DDI_CTL_DE in the spec). Consolidate it
>> to just one in struct intel_digital_port. This is a preparation step for
>> future changes in D2D enable/disable sequence for xe2lpd that need to
>> save some additional bits.
>>
>> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>> Cc: Gustavo Sousa <gustavo.sousa@intel.com>
>> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>> Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_ddi.c | 36 +++++++++++-------------
>> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
>> 2 files changed, 18 insertions(+), 20 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
>> index 4668de45d6fe..29c9386659ff 100644
>> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
>> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
>> @@ -325,26 +325,25 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
>> const struct intel_crtc_state *crtc_state)
>> {
>> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>> enum phy phy = intel_port_to_phy(i915, encoder->port);
>>
>> /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
>> - intel_dp->DP = dig_port->saved_port_bits |
>> + dig_port->saved_port_bits |=
>
>Before this patch, saved_port_bits was a copy of DDI_BUF_PORT_REVERSAL
>and DDI_A_4_LANES, either based on a value we readout from hardware at
>startup, or based on VBT settings. So it was a value of some
>fundamental settings that we "saved" once at startup time and could then
>just re-use thereafter.
>
>If we're going to start saving per-modeset information (such as lane
>count and link rate), then that's a pretty fundamental change to the
>purpose of this field, and "saved_port_bits" doesn't really feel like an
>appropriate name anymore. We should probably rename it and add some
>documentation on the field explaining exactly what its purpose is and
>how/when it gets updated.
I will let Clint chime in as the original author here, but from what
I can see this is basically a saved value of DDI_BUF_CTL(port), to be
written when appropriate. We have more than just
DDI_BUF_PORT_REVERSAL and DDI_A_4_LANES.
drivers/gpu/drm/i915/display/intel_cx0_phy.c: bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_40BIT;
drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_10BIT;
drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= ddi_buf_phy_link_rate(crtc_state->port_clock);
drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits &= ~DDI_BUF_EMP_MASK;
drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= signal_levels;
drivers/gpu/drm/i915/display/intel_ddi.c: intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
drivers/gpu/drm/i915/display/intel_ddi.c: if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
drivers/gpu/drm/i915/display/intel_ddi.c: if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_PORT_WIDTH(lane_count);
drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
drivers/gpu/drm/i915/display/intel_ddi.c: intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
drivers/gpu/drm/i915/display/intel_ddi.c: intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
drivers/gpu/drm/i915/display/intel_ddi.c: intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
drivers/gpu/drm/i915/display/intel_ddi.c: if (dig_port->saved_port_bits & DDI_A_4_LANES)
drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_A_4_LANES;
drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits =
drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits =
drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL;
drivers/gpu/drm/i915/display/intel_display_types.h: u32 saved_port_bits;
drivers/gpu/drm/i915/display/intel_dp.c: dig_port->saved_port_bits = intel_de_read(dev_priv, intel_dp->output_reg);
drivers/gpu/drm/i915/display/intel_tc.c: bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
Lucas De Marchi
>
>> DDI_PORT_WIDTH(crtc_state->lane_count) |
>> DDI_BUF_TRANS_SELECT(0);
>>
>> if (DISPLAY_VER(i915) >= 14) {
>> if (intel_dp_is_uhbr(crtc_state))
>> - intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
>> + dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_40BIT;
>> else
>> - intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
>> + dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_10BIT;
>> }
>>
>> if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
>> - intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
>> + dig_port->saved_port_bits |= ddi_buf_phy_link_rate(crtc_state->port_clock);
>> if (!intel_tc_port_in_tbt_alt_mode(dig_port))
>> - intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
>> + dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
>> }
>> }
>>
>> @@ -1450,7 +1449,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
>> const struct intel_crtc_state *crtc_state)
>> {
>> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
>> + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
>> int level = intel_ddi_level(encoder, crtc_state, 0);
>> enum port port = encoder->port;
>> u32 signal_levels;
>> @@ -1467,10 +1466,10 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
>> drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
>> signal_levels);
>>
>> - intel_dp->DP &= ~DDI_BUF_EMP_MASK;
>> - intel_dp->DP |= signal_levels;
>> + dig_port->saved_port_bits &= ~DDI_BUF_EMP_MASK;
>> + dig_port->saved_port_bits |= signal_levels;
>>
>> - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
>> + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
>> intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
>> }
>>
>> @@ -3145,7 +3144,6 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
>> struct drm_connector *connector = conn_state->connector;
>> enum port port = encoder->port;
>> enum phy phy = intel_port_to_phy(dev_priv, port);
>> - u32 buf_ctl;
>>
>> if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
>> crtc_state->hdmi_high_tmds_clock_ratio,
>> @@ -3211,7 +3209,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
>> * is filled with lane count, already set in the crtc_state.
>> * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
>> */
>> - buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
>> + dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
>> if (DISPLAY_VER(dev_priv) >= 14) {
>> u8 lane_count = mtl_get_port_width(crtc_state->lane_count);
>> u32 port_buf = 0;
>> @@ -3224,13 +3222,13 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
>> intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
>> XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
>>
>> - buf_ctl |= DDI_PORT_WIDTH(lane_count);
>> + dig_port->saved_port_bits |= DDI_PORT_WIDTH(lane_count);
>> } else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
>> drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
>> - buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
>> + dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
>> }
>>
>> - intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
>> + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
>>
>> intel_wait_ddi_buf_active(dev_priv, port);
>>
>> @@ -3448,8 +3446,8 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
>> mtl_port_buf_ctl_program(encoder, crtc_state);
>>
>> /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */
>> - intel_dp->DP |= DDI_BUF_CTL_ENABLE;
>> - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
>> + dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
>> + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
>> intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
>>
>> /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */
>> @@ -3499,8 +3497,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
>> (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port)))
>> adlp_tbt_to_dp_alt_switch_wa(encoder);
>>
>> - intel_dp->DP |= DDI_BUF_CTL_ENABLE;
>> - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
>> + dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
>> + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
>> intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
>>
>> intel_wait_ddi_buf_active(dev_priv, port);
>> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
>> index 189c5737e63a..2346cd32f5a7 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dp.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
>> @@ -6025,7 +6025,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>> intel_dp->pps.active_pipe = INVALID_PIPE;
>>
>> /* Preserve the current hw state. */
>> - intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
>> + dig_port->saved_port_bits = intel_de_read(dev_priv, intel_dp->output_reg);
>
>Isn't this going to potentially clobber the lane reversal setting we
>determined from the VBT near the beginning of intel_ddi_init()?
>
>
>Matt
>
>> intel_dp->attached_connector = intel_connector;
>>
>> if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
>> --
>> 2.40.1
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [Intel-xe] [PATCH v4 10/30] drm/i915/display: Consolidate saved port bits in intel_digital_port
2023-09-18 21:06 ` Lucas De Marchi
@ 2023-09-18 22:22 ` Taylor, Clinton A
2023-09-18 22:43 ` Matt Roper
1 sibling, 0 replies; 40+ messages in thread
From: Taylor, Clinton A @ 2023-09-18 22:22 UTC (permalink / raw)
To: Roper, Matthew D, De Marchi, Lucas
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
On Mon, 2023-09-18 at 16:06 -0500, Lucas De Marchi wrote:
> On Fri, Sep 15, 2023 at 12:50:41PM -0700, Matt Roper wrote:
> > On Fri, Sep 15, 2023 at 10:46:31AM -0700, Lucas De Marchi wrote:
> > > From: Clint Taylor <clinton.a.taylor@intel.com>
> > >
> > > We use multiple variables for HDMI and DisplayPort to store the value of
> > > DDI_BUF_CTL register (now called DDI_CTL_DE in the spec). Consolidate it
> > > to just one in struct intel_digital_port. This is a preparation step for
> > > future changes in D2D enable/disable sequence for xe2lpd that need to
> > > save some additional bits.
> > >
> > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> > > Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 36 +++++++++++-------------
> > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> > > 2 files changed, 18 insertions(+), 20 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index 4668de45d6fe..29c9386659ff 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -325,26 +325,25 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder
> > > *encoder,
> > > const struct intel_crtc_state *crtc_state)
> > > {
> > > struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > > struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > enum phy phy = intel_port_to_phy(i915, encoder->port);
> > >
> > > /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
> > > - intel_dp->DP = dig_port->saved_port_bits |
> > > + dig_port->saved_port_bits |=
> >
> > Before this patch, saved_port_bits was a copy of DDI_BUF_PORT_REVERSAL
> > and DDI_A_4_LANES, either based on a value we readout from hardware at
> > startup, or based on VBT settings. So it was a value of some
> > fundamental settings that we "saved" once at startup time and could then
> > just re-use thereafter.
> >
> > If we're going to start saving per-modeset information (such as lane
> > count and link rate), then that's a pretty fundamental change to the
> > purpose of this field, and "saved_port_bits" doesn't really feel like an
> > appropriate name anymore. We should probably rename it and add some
> > documentation on the field explaining exactly what its purpose is and
> > how/when it gets updated.
>
> I will let Clint chime in as the original author here, but from what
> I can see this is basically a saved value of DDI_BUF_CTL(port), to be
> written when appropriate. We have more than just
> DDI_BUF_PORT_REVERSAL and DDI_A_4_LANES.
>
> drivers/gpu/drm/i915/display/intel_cx0_phy.c: bool lane_reversal = dig_port-
> >saved_port_bits & DDI_BUF_PORT_REVERSAL;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port-
> >saved_port_bits |= DDI_BUF_PORT_DATA_40BIT;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port-
> >saved_port_bits |= DDI_BUF_PORT_DATA_10BIT;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> ddi_buf_phy_link_rate(crtc_state->port_clock);
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port-
> >saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits &=
> ~DDI_BUF_EMP_MASK;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> signal_levels;
> drivers/gpu/drm/i915/display/intel_ddi.c: intel_de_write(dev_priv,
> DDI_BUF_CTL(port), dig_port->saved_port_bits);
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port-
> >saved_port_bits & DDI_BUF_PORT_REVERSAL;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> drivers/gpu/drm/i915/display/intel_ddi.c: if (dig_port->saved_port_bits &
> DDI_BUF_PORT_REVERSAL)
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits &=
> ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> DDI_BUF_CTL_ENABLE;
> drivers/gpu/drm/i915/display/intel_ddi.c: if (dig_port->saved_port_bits &
> DDI_BUF_PORT_REVERSAL)
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> DDI_PORT_WIDTH(lane_count);
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> drivers/gpu/drm/i915/display/intel_ddi.c: intel_de_write(dev_priv,
> DDI_BUF_CTL(port), dig_port->saved_port_bits);
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> DDI_BUF_CTL_ENABLE;
> drivers/gpu/drm/i915/display/intel_ddi.c: intel_de_write(dev_priv,
> DDI_BUF_CTL(port), dig_port->saved_port_bits);
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> DDI_BUF_CTL_ENABLE;
> drivers/gpu/drm/i915/display/intel_ddi.c: intel_de_write(dev_priv,
> DDI_BUF_CTL(port), dig_port->saved_port_bits);
> drivers/gpu/drm/i915/display/intel_ddi.c: if (dig_port->saved_port_bits &
> DDI_A_4_LANES)
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> DDI_A_4_LANES;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits =
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits =
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> DDI_BUF_PORT_REVERSAL;
> drivers/gpu/drm/i915/display/intel_display_types.h: u32 saved_port_bits;
> drivers/gpu/drm/i915/display/intel_dp.c: dig_port->saved_port_bits =
> intel_de_read(dev_priv, intel_dp->output_reg);
> drivers/gpu/drm/i915/display/intel_tc.c: bool lane_reversal = dig_port-
> >saved_port_bits & DDI_BUF_PORT_REVERSAL;
>
> Lucas De Marchi
>
saved_port_bits is a shadow register for the ddi_buf_ctl register used throughout the
driver. This patch was just to consolidate identical data stored in intel_dp->DP and
dig_port->saved_port_bits.
I agree the name is not easily decoded as to its actual meaning. possible changes to:
saved_port_ctl_bits
saved_ddi_buf_ctl_bits
or we could simple add a comment to struct intel_digital_port to explain the meaning of
saved_port_bits.
-Clint
> > > DDI_PORT_WIDTH(crtc_state->lane_count) |
> > > DDI_BUF_TRANS_SELECT(0);
> > >
> > > if (DISPLAY_VER(i915) >= 14) {
> > > if (intel_dp_is_uhbr(crtc_state))
> > > - intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
> > > + dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_40BIT;
> > > else
> > > - intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
> > > + dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_10BIT;
> > > }
> > >
> > > if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
> > > - intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
> > > + dig_port->saved_port_bits |= ddi_buf_phy_link_rate(crtc_state-
> > > >port_clock);
> > > if (!intel_tc_port_in_tbt_alt_mode(dig_port))
> > > - intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> > > + dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> > > }
> > > }
> > >
> > > @@ -1450,7 +1449,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
> > > const struct intel_crtc_state *crtc_state)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > int level = intel_ddi_level(encoder, crtc_state, 0);
> > > enum port port = encoder->port;
> > > u32 signal_levels;
> > > @@ -1467,10 +1466,10 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
> > > drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
> > > signal_levels);
> > >
> > > - intel_dp->DP &= ~DDI_BUF_EMP_MASK;
> > > - intel_dp->DP |= signal_levels;
> > > + dig_port->saved_port_bits &= ~DDI_BUF_EMP_MASK;
> > > + dig_port->saved_port_bits |= signal_levels;
> > >
> > > - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> > > + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> > > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
> > > }
> > >
> > > @@ -3145,7 +3144,6 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state
> > > *state,
> > > struct drm_connector *connector = conn_state->connector;
> > > enum port port = encoder->port;
> > > enum phy phy = intel_port_to_phy(dev_priv, port);
> > > - u32 buf_ctl;
> > >
> > > if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
> > > crtc_state->hdmi_high_tmds_clock_ratio,
> > > @@ -3211,7 +3209,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state
> > > *state,
> > > * is filled with lane count, already set in the crtc_state.
> > > * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
> > > */
> > > - buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
> > > + dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> > > if (DISPLAY_VER(dev_priv) >= 14) {
> > > u8 lane_count = mtl_get_port_width(crtc_state->lane_count);
> > > u32 port_buf = 0;
> > > @@ -3224,13 +3222,13 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state
> > > *state,
> > > intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
> > > XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
> > >
> > > - buf_ctl |= DDI_PORT_WIDTH(lane_count);
> > > + dig_port->saved_port_bits |= DDI_PORT_WIDTH(lane_count);
> > > } else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
> > > drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
> > > - buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> > > + dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> > > }
> > >
> > > - intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
> > > + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> > >
> > > intel_wait_ddi_buf_active(dev_priv, port);
> > >
> > > @@ -3448,8 +3446,8 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp
> > > *intel_dp,
> > > mtl_port_buf_ctl_program(encoder, crtc_state);
> > >
> > > /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice
> > > */
> > > - intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> > > - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> > > + dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> > > + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> > > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
> > >
> > > /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */
> > > @@ -3499,8 +3497,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp
> > > *intel_dp,
> > > (intel_tc_port_in_dp_alt_mode(dig_port) ||
> > > intel_tc_port_in_legacy_mode(dig_port)))
> > > adlp_tbt_to_dp_alt_switch_wa(encoder);
> > >
> > > - intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> > > - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> > > + dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> > > + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> > > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
> > >
> > > intel_wait_ddi_buf_active(dev_priv, port);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 189c5737e63a..2346cd32f5a7 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -6025,7 +6025,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
> > > intel_dp->pps.active_pipe = INVALID_PIPE;
> > >
> > > /* Preserve the current hw state. */
> > > - intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
> > > + dig_port->saved_port_bits = intel_de_read(dev_priv, intel_dp->output_reg);
> >
> > Isn't this going to potentially clobber the lane reversal setting we
> > determined from the VBT near the beginning of intel_ddi_init()?
> >
> >
> > Matt
> >
> > > intel_dp->attached_connector = intel_connector;
> > >
> > > if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
> > > --
> > > 2.40.1
> > >
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [Intel-xe] [PATCH v4 10/30] drm/i915/display: Consolidate saved port bits in intel_digital_port
2023-09-18 21:06 ` Lucas De Marchi
2023-09-18 22:22 ` Taylor, Clinton A
@ 2023-09-18 22:43 ` Matt Roper
2023-09-19 20:50 ` Taylor, Clinton A
1 sibling, 1 reply; 40+ messages in thread
From: Matt Roper @ 2023-09-18 22:43 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, intel-xe
On Mon, Sep 18, 2023 at 04:06:58PM -0500, Lucas De Marchi wrote:
> On Fri, Sep 15, 2023 at 12:50:41PM -0700, Matt Roper wrote:
> > On Fri, Sep 15, 2023 at 10:46:31AM -0700, Lucas De Marchi wrote:
> > > From: Clint Taylor <clinton.a.taylor@intel.com>
> > >
> > > We use multiple variables for HDMI and DisplayPort to store the value of
> > > DDI_BUF_CTL register (now called DDI_CTL_DE in the spec). Consolidate it
> > > to just one in struct intel_digital_port. This is a preparation step for
> > > future changes in D2D enable/disable sequence for xe2lpd that need to
> > > save some additional bits.
> > >
> > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> > > Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_ddi.c | 36 +++++++++++-------------
> > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> > > 2 files changed, 18 insertions(+), 20 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > index 4668de45d6fe..29c9386659ff 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > @@ -325,26 +325,25 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder,
> > > const struct intel_crtc_state *crtc_state)
> > > {
> > > struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > > struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > enum phy phy = intel_port_to_phy(i915, encoder->port);
> > >
> > > /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain() later */
> > > - intel_dp->DP = dig_port->saved_port_bits |
> > > + dig_port->saved_port_bits |=
> >
> > Before this patch, saved_port_bits was a copy of DDI_BUF_PORT_REVERSAL
> > and DDI_A_4_LANES, either based on a value we readout from hardware at
> > startup, or based on VBT settings. So it was a value of some
> > fundamental settings that we "saved" once at startup time and could then
> > just re-use thereafter.
> >
> > If we're going to start saving per-modeset information (such as lane
> > count and link rate), then that's a pretty fundamental change to the
> > purpose of this field, and "saved_port_bits" doesn't really feel like an
> > appropriate name anymore. We should probably rename it and add some
> > documentation on the field explaining exactly what its purpose is and
> > how/when it gets updated.
>
> I will let Clint chime in as the original author here, but from what
> I can see this is basically a saved value of DDI_BUF_CTL(port), to be
> written when appropriate. We have more than just
> DDI_BUF_PORT_REVERSAL and DDI_A_4_LANES.
I think you grepped the wrong tree. The output you pasted is where
saved_port_bits is being used after this LNL series gets applied. The
usage of this field on today's drm-tip is just:
drivers/gpu/drm/i915/display/intel_cx0_phy.c:2706: bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
drivers/gpu/drm/i915/display/intel_display_types.h:1827: u32 saved_port_bits;
drivers/gpu/drm/i915/display/intel_tc.c:362: bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
drivers/gpu/drm/i915/display/intel_ddi.c:333: intel_dp->DP = dig_port->saved_port_bits |
drivers/gpu/drm/i915/display/intel_ddi.c:2259: dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
drivers/gpu/drm/i915/display/intel_ddi.c:2389: if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
drivers/gpu/drm/i915/display/intel_ddi.c:3214: buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
drivers/gpu/drm/i915/display/intel_ddi.c:3221: if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
drivers/gpu/drm/i915/display/intel_ddi.c:4505: if (dig_port->saved_port_bits & DDI_A_4_LANES)
drivers/gpu/drm/i915/display/intel_ddi.c:4543: dig_port->saved_port_bits |= DDI_A_4_LANES;
.--
drivers/gpu/drm/i915/display/intel_ddi.c:4965: dig_port->saved_port_bits =
drivers/gpu/drm/i915/display/intel_ddi.c-4966- intel_de_read(dev_priv, DDI_BUF_CTL(port))
drivers/gpu/drm/i915/display/intel_ddi.c-4967- & DDI_BUF_PORT_REVERSAL;
.--
drivers/gpu/drm/i915/display/intel_ddi.c:4969: dig_port->saved_port_bits =
drivers/gpu/drm/i915/display/intel_ddi.c-4970- intel_de_read(dev_priv, DDI_BUF_CTL(port))
drivers/gpu/drm/i915/display/intel_ddi.c-4971- & (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
.--
drivers/gpu/drm/i915/display/intel_ddi.c:4974: dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL;
I.e., using it as a cached copy of DDI_BUF_CTL is a large change from
the existing code; previously it was an unchanging stash of just those
two specific bits from startup-time.
I'm not saying that it's wrong to make that change, just that we're
using it for a completely different purpose from today's drm-tip so I
think we need to document that carefully and make it clear what the
intended new usage is.
Matt
>
> drivers/gpu/drm/i915/display/intel_cx0_phy.c: bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_40BIT;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_10BIT;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= ddi_buf_phy_link_rate(crtc_state->port_clock);
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits &= ~DDI_BUF_EMP_MASK;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= signal_levels;
> drivers/gpu/drm/i915/display/intel_ddi.c: intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> drivers/gpu/drm/i915/display/intel_ddi.c: if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> drivers/gpu/drm/i915/display/intel_ddi.c: if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_PORT_WIDTH(lane_count);
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> drivers/gpu/drm/i915/display/intel_ddi.c: intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> drivers/gpu/drm/i915/display/intel_ddi.c: intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> drivers/gpu/drm/i915/display/intel_ddi.c: intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> drivers/gpu/drm/i915/display/intel_ddi.c: if (dig_port->saved_port_bits & DDI_A_4_LANES)
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_A_4_LANES;
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits =
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits =
> drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |= DDI_BUF_PORT_REVERSAL;
> drivers/gpu/drm/i915/display/intel_display_types.h: u32 saved_port_bits;
> drivers/gpu/drm/i915/display/intel_dp.c: dig_port->saved_port_bits = intel_de_read(dev_priv, intel_dp->output_reg);
> drivers/gpu/drm/i915/display/intel_tc.c: bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
>
> Lucas De Marchi
>
> >
> > > DDI_PORT_WIDTH(crtc_state->lane_count) |
> > > DDI_BUF_TRANS_SELECT(0);
> > >
> > > if (DISPLAY_VER(i915) >= 14) {
> > > if (intel_dp_is_uhbr(crtc_state))
> > > - intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
> > > + dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_40BIT;
> > > else
> > > - intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
> > > + dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_10BIT;
> > > }
> > >
> > > if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
> > > - intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
> > > + dig_port->saved_port_bits |= ddi_buf_phy_link_rate(crtc_state->port_clock);
> > > if (!intel_tc_port_in_tbt_alt_mode(dig_port))
> > > - intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> > > + dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> > > }
> > > }
> > >
> > > @@ -1450,7 +1449,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
> > > const struct intel_crtc_state *crtc_state)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > int level = intel_ddi_level(encoder, crtc_state, 0);
> > > enum port port = encoder->port;
> > > u32 signal_levels;
> > > @@ -1467,10 +1466,10 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
> > > drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
> > > signal_levels);
> > >
> > > - intel_dp->DP &= ~DDI_BUF_EMP_MASK;
> > > - intel_dp->DP |= signal_levels;
> > > + dig_port->saved_port_bits &= ~DDI_BUF_EMP_MASK;
> > > + dig_port->saved_port_bits |= signal_levels;
> > >
> > > - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> > > + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> > > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
> > > }
> > >
> > > @@ -3145,7 +3144,6 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
> > > struct drm_connector *connector = conn_state->connector;
> > > enum port port = encoder->port;
> > > enum phy phy = intel_port_to_phy(dev_priv, port);
> > > - u32 buf_ctl;
> > >
> > > if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
> > > crtc_state->hdmi_high_tmds_clock_ratio,
> > > @@ -3211,7 +3209,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
> > > * is filled with lane count, already set in the crtc_state.
> > > * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
> > > */
> > > - buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
> > > + dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> > > if (DISPLAY_VER(dev_priv) >= 14) {
> > > u8 lane_count = mtl_get_port_width(crtc_state->lane_count);
> > > u32 port_buf = 0;
> > > @@ -3224,13 +3222,13 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
> > > intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
> > > XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
> > >
> > > - buf_ctl |= DDI_PORT_WIDTH(lane_count);
> > > + dig_port->saved_port_bits |= DDI_PORT_WIDTH(lane_count);
> > > } else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
> > > drm_WARN_ON(&dev_priv->drm, !intel_tc_port_in_legacy_mode(dig_port));
> > > - buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> > > + dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> > > }
> > >
> > > - intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
> > > + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> > >
> > > intel_wait_ddi_buf_active(dev_priv, port);
> > >
> > > @@ -3448,8 +3446,8 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
> > > mtl_port_buf_ctl_program(encoder, crtc_state);
> > >
> > > /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port slice */
> > > - intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> > > - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> > > + dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> > > + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> > > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
> > >
> > > /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */
> > > @@ -3499,8 +3497,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
> > > (intel_tc_port_in_dp_alt_mode(dig_port) || intel_tc_port_in_legacy_mode(dig_port)))
> > > adlp_tbt_to_dp_alt_switch_wa(encoder);
> > >
> > > - intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> > > - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> > > + dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> > > + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> > > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
> > >
> > > intel_wait_ddi_buf_active(dev_priv, port);
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index 189c5737e63a..2346cd32f5a7 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -6025,7 +6025,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
> > > intel_dp->pps.active_pipe = INVALID_PIPE;
> > >
> > > /* Preserve the current hw state. */
> > > - intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
> > > + dig_port->saved_port_bits = intel_de_read(dev_priv, intel_dp->output_reg);
> >
> > Isn't this going to potentially clobber the lane reversal setting we
> > determined from the VBT near the beginning of intel_ddi_init()?
> >
> >
> > Matt
> >
> > > intel_dp->attached_connector = intel_connector;
> > >
> > > if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
> > > --
> > > 2.40.1
> > >
> >
> > --
> > Matt Roper
> > Graphics Software Engineer
> > Linux GPU Platform Enablement
> > Intel Corporation
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [Intel-xe] [PATCH v4 10/30] drm/i915/display: Consolidate saved port bits in intel_digital_port
2023-09-18 22:43 ` Matt Roper
@ 2023-09-19 20:50 ` Taylor, Clinton A
0 siblings, 0 replies; 40+ messages in thread
From: Taylor, Clinton A @ 2023-09-19 20:50 UTC (permalink / raw)
To: Roper, Matthew D, De Marchi, Lucas
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
On Mon, 2023-09-18 at 15:43 -0700, Matt Roper wrote:
> On Mon, Sep 18, 2023 at 04:06:58PM -0500, Lucas De Marchi wrote:
> > On Fri, Sep 15, 2023 at 12:50:41PM -0700, Matt Roper wrote:
> > > On Fri, Sep 15, 2023 at 10:46:31AM -0700, Lucas De Marchi wrote:
> > > > From: Clint Taylor <clinton.a.taylor@intel.com>
> > > >
> > > > We use multiple variables for HDMI and DisplayPort to store the value of
> > > > DDI_BUF_CTL register (now called DDI_CTL_DE in the spec). Consolidate it
> > > > to just one in struct intel_digital_port. This is a preparation step for
> > > > future changes in D2D enable/disable sequence for xe2lpd that need to
> > > > save some additional bits.
> > > >
> > > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > > > Cc: Gustavo Sousa <gustavo.sousa@intel.com>
> > > > Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > > > Signed-off-by: Clint Taylor <clinton.a.taylor@intel.com>
> > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/display/intel_ddi.c | 36 +++++++++++-------------
> > > > drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> > > > 2 files changed, 18 insertions(+), 20 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > index 4668de45d6fe..29c9386659ff 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> > > > @@ -325,26 +325,25 @@ static void intel_ddi_init_dp_buf_reg(struct intel_encoder
> > > > *encoder,
> > > > const struct intel_crtc_state *crtc_state)
> > > > {
> > > > struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > > > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > > > struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > > enum phy phy = intel_port_to_phy(i915, encoder->port);
> > > >
> > > > /* DDI_BUF_CTL_ENABLE will be set by intel_ddi_prepare_link_retrain()
> > > > later */
> > > > - intel_dp->DP = dig_port->saved_port_bits |
> > > > + dig_port->saved_port_bits |=
> > >
> > > Before this patch, saved_port_bits was a copy of DDI_BUF_PORT_REVERSAL
> > > and DDI_A_4_LANES, either based on a value we readout from hardware at
> > > startup, or based on VBT settings. So it was a value of some
> > > fundamental settings that we "saved" once at startup time and could then
> > > just re-use thereafter.
> > >
> > > If we're going to start saving per-modeset information (such as lane
> > > count and link rate), then that's a pretty fundamental change to the
> > > purpose of this field, and "saved_port_bits" doesn't really feel like an
> > > appropriate name anymore. We should probably rename it and add some
> > > documentation on the field explaining exactly what its purpose is and
> > > how/when it gets updated.
> >
> > I will let Clint chime in as the original author here, but from what
> > I can see this is basically a saved value of DDI_BUF_CTL(port), to be
> > written when appropriate. We have more than just
> > DDI_BUF_PORT_REVERSAL and DDI_A_4_LANES.
>
> I think you grepped the wrong tree. The output you pasted is where
> saved_port_bits is being used after this LNL series gets applied. The
> usage of this field on today's drm-tip is just:
>
> drivers/gpu/drm/i915/display/intel_cx0_phy.c:2706: bool lane_reversal = dig_port-
> >saved_port_bits & DDI_BUF_PORT_REVERSAL;
> drivers/gpu/drm/i915/display/intel_display_types.h:1827: u32 saved_port_bits;
> drivers/gpu/drm/i915/display/intel_tc.c:362: bool lane_reversal = dig_port-
> >saved_port_bits & DDI_BUF_PORT_REVERSAL;
> drivers/gpu/drm/i915/display/intel_ddi.c:333: intel_dp->DP = dig_port-
> >saved_port_bits |
> drivers/gpu/drm/i915/display/intel_ddi.c:2259: dig_port-
> >saved_port_bits & DDI_BUF_PORT_REVERSAL;
> drivers/gpu/drm/i915/display/intel_ddi.c:2389: if (dig_port->saved_port_bits &
> DDI_BUF_PORT_REVERSAL)
> drivers/gpu/drm/i915/display/intel_ddi.c:3214: buf_ctl = dig_port->saved_port_bits |
> DDI_BUF_CTL_ENABLE;
> drivers/gpu/drm/i915/display/intel_ddi.c:3221: if (dig_port->saved_port_bits
> & DDI_BUF_PORT_REVERSAL)
> drivers/gpu/drm/i915/display/intel_ddi.c:4505: if (dig_port->saved_port_bits &
> DDI_A_4_LANES)
> drivers/gpu/drm/i915/display/intel_ddi.c:4543: dig_port->saved_port_bits |=
> DDI_A_4_LANES;
> .--
> drivers/gpu/drm/i915/display/intel_ddi.c:4965: dig_port->saved_port_bits =
> drivers/gpu/drm/i915/display/intel_ddi.c
> -4966- intel_de_read(dev_priv, DDI_BUF_CTL(port))
> drivers/gpu/drm/i915/display/intel_ddi.c-4967- &
> DDI_BUF_PORT_REVERSAL;
> .--
> drivers/gpu/drm/i915/display/intel_ddi.c:4969: dig_port->saved_port_bits =
> drivers/gpu/drm/i915/display/intel_ddi.c
> -4970- intel_de_read(dev_priv, DDI_BUF_CTL(port))
> drivers/gpu/drm/i915/display/intel_ddi.c-4971- &
> (DDI_BUF_PORT_REVERSAL | DDI_A_4_LANES);
> .--
> drivers/gpu/drm/i915/display/intel_ddi.c:4974: dig_port->saved_port_bits |=
> DDI_BUF_PORT_REVERSAL;
>
> I.e., using it as a cached copy of DDI_BUF_CTL is a large change from
> the existing code; previously it was an unchanging stash of just those
> two specific bits from startup-time.
>
> I'm not saying that it's wrong to make that change, just that we're
> using it for a completely different purpose from today's drm-tip so I
> think we need to document that carefully and make it clear what the
> intended new usage is.
>
DRM-TIP uses intel_dp->DP for caching DDI_BUF_CTL for display port encoders and
saved_port_bits for caching DDI_BUF_CTL on HDMI encoders. This change consolidates both
encoder types to use saved_port_bits only.
from drm-tip: intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
-Clint
>
> Matt
>
> > drivers/gpu/drm/i915/display/intel_cx0_phy.c: bool lane_reversal = dig_port-
> > >saved_port_bits & DDI_BUF_PORT_REVERSAL;
> > drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> > drivers/gpu/drm/i915/display/intel_ddi.c: dig_port-
> > >saved_port_bits |= DDI_BUF_PORT_DATA_40BIT;
> > drivers/gpu/drm/i915/display/intel_ddi.c: dig_port-
> > >saved_port_bits |= DDI_BUF_PORT_DATA_10BIT;
> > drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> > ddi_buf_phy_link_rate(crtc_state->port_clock);
> > drivers/gpu/drm/i915/display/intel_ddi.c: dig_port-
> > >saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> > drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits &=
> > ~DDI_BUF_EMP_MASK;
> > drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> > signal_levels;
> > drivers/gpu/drm/i915/display/intel_ddi.c: intel_de_write(dev_priv,
> > DDI_BUF_CTL(port), dig_port->saved_port_bits);
> > drivers/gpu/drm/i915/display/intel_ddi.c: dig_port-
> > >saved_port_bits & DDI_BUF_PORT_REVERSAL;
> > drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> > XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> > drivers/gpu/drm/i915/display/intel_ddi.c: if (dig_port->saved_port_bits &
> > DDI_BUF_PORT_REVERSAL)
> > drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits &=
> > ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
> > drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> > DDI_BUF_CTL_ENABLE;
> > drivers/gpu/drm/i915/display/intel_ddi.c: if (dig_port->saved_port_bits
> > & DDI_BUF_PORT_REVERSAL)
> > drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> > DDI_PORT_WIDTH(lane_count);
> > drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> > DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> > drivers/gpu/drm/i915/display/intel_ddi.c: intel_de_write(dev_priv,
> > DDI_BUF_CTL(port), dig_port->saved_port_bits);
> > drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> > DDI_BUF_CTL_ENABLE;
> > drivers/gpu/drm/i915/display/intel_ddi.c: intel_de_write(dev_priv,
> > DDI_BUF_CTL(port), dig_port->saved_port_bits);
> > drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> > DDI_BUF_CTL_ENABLE;
> > drivers/gpu/drm/i915/display/intel_ddi.c: intel_de_write(dev_priv,
> > DDI_BUF_CTL(port), dig_port->saved_port_bits);
> > drivers/gpu/drm/i915/display/intel_ddi.c: if (dig_port->saved_port_bits &
> > DDI_A_4_LANES)
> > drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> > DDI_A_4_LANES;
> > drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits =
> > drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits =
> > drivers/gpu/drm/i915/display/intel_ddi.c: dig_port->saved_port_bits |=
> > DDI_BUF_PORT_REVERSAL;
> > drivers/gpu/drm/i915/display/intel_display_types.h: u32 saved_port_bits;
> > drivers/gpu/drm/i915/display/intel_dp.c: dig_port->saved_port_bits =
> > intel_de_read(dev_priv, intel_dp->output_reg);
> > drivers/gpu/drm/i915/display/intel_tc.c: bool lane_reversal = dig_port-
> > >saved_port_bits & DDI_BUF_PORT_REVERSAL;
> >
> > Lucas De Marchi
> >
> > > > DDI_PORT_WIDTH(crtc_state->lane_count) |
> > > > DDI_BUF_TRANS_SELECT(0);
> > > >
> > > > if (DISPLAY_VER(i915) >= 14) {
> > > > if (intel_dp_is_uhbr(crtc_state))
> > > > - intel_dp->DP |= DDI_BUF_PORT_DATA_40BIT;
> > > > + dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_40BIT;
> > > > else
> > > > - intel_dp->DP |= DDI_BUF_PORT_DATA_10BIT;
> > > > + dig_port->saved_port_bits |= DDI_BUF_PORT_DATA_10BIT;
> > > > }
> > > >
> > > > if (IS_ALDERLAKE_P(i915) && intel_phy_is_tc(i915, phy)) {
> > > > - intel_dp->DP |= ddi_buf_phy_link_rate(crtc_state->port_clock);
> > > > + dig_port->saved_port_bits |= ddi_buf_phy_link_rate(crtc_state-
> > > > >port_clock);
> > > > if (!intel_tc_port_in_tbt_alt_mode(dig_port))
> > > > - intel_dp->DP |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> > > > + dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> > > > }
> > > > }
> > > >
> > > > @@ -1450,7 +1449,7 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
> > > > const struct intel_crtc_state *crtc_state)
> > > > {
> > > > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > > > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > > > + struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> > > > int level = intel_ddi_level(encoder, crtc_state, 0);
> > > > enum port port = encoder->port;
> > > > u32 signal_levels;
> > > > @@ -1467,10 +1466,10 @@ hsw_set_signal_levels(struct intel_encoder *encoder,
> > > > drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
> > > > signal_levels);
> > > >
> > > > - intel_dp->DP &= ~DDI_BUF_EMP_MASK;
> > > > - intel_dp->DP |= signal_levels;
> > > > + dig_port->saved_port_bits &= ~DDI_BUF_EMP_MASK;
> > > > + dig_port->saved_port_bits |= signal_levels;
> > > >
> > > > - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> > > > + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> > > > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
> > > > }
> > > >
> > > > @@ -3145,7 +3144,6 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state
> > > > *state,
> > > > struct drm_connector *connector = conn_state->connector;
> > > > enum port port = encoder->port;
> > > > enum phy phy = intel_port_to_phy(dev_priv, port);
> > > > - u32 buf_ctl;
> > > >
> > > > if (!intel_hdmi_handle_sink_scrambling(encoder, connector,
> > > > crtc_state-
> > > > >hdmi_high_tmds_clock_ratio,
> > > > @@ -3211,7 +3209,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state
> > > > *state,
> > > > * is filled with lane count, already set in the crtc_state.
> > > > * The same is required to be filled in PORT_BUF_CTL for C10/20 Phy.
> > > > */
> > > > - buf_ctl = dig_port->saved_port_bits | DDI_BUF_CTL_ENABLE;
> > > > + dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> > > > if (DISPLAY_VER(dev_priv) >= 14) {
> > > > u8 lane_count = mtl_get_port_width(crtc_state->lane_count);
> > > > u32 port_buf = 0;
> > > > @@ -3224,13 +3222,13 @@ static void intel_enable_ddi_hdmi(struct
> > > > intel_atomic_state *state,
> > > > intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
> > > > XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL,
> > > > port_buf);
> > > >
> > > > - buf_ctl |= DDI_PORT_WIDTH(lane_count);
> > > > + dig_port->saved_port_bits |= DDI_PORT_WIDTH(lane_count);
> > > > } else if (IS_ALDERLAKE_P(dev_priv) && intel_phy_is_tc(dev_priv, phy)) {
> > > > drm_WARN_ON(&dev_priv->drm,
> > > > !intel_tc_port_in_legacy_mode(dig_port));
> > > > - buf_ctl |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> > > > + dig_port->saved_port_bits |= DDI_BUF_CTL_TC_PHY_OWNERSHIP;
> > > > }
> > > >
> > > > - intel_de_write(dev_priv, DDI_BUF_CTL(port), buf_ctl);
> > > > + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> > > >
> > > > intel_wait_ddi_buf_active(dev_priv, port);
> > > >
> > > > @@ -3448,8 +3446,8 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp
> > > > *intel_dp,
> > > > mtl_port_buf_ctl_program(encoder, crtc_state);
> > > >
> > > > /* 6.i Configure and enable DDI_CTL_DE to start sending valid data to port
> > > > slice */
> > > > - intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> > > > - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> > > > + dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> > > > + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> > > > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
> > > >
> > > > /* 6.j Poll for PORT_BUF_CTL Idle Status == 0, timeout after 100 us */
> > > > @@ -3499,8 +3497,8 @@ static void intel_ddi_prepare_link_retrain(struct intel_dp
> > > > *intel_dp,
> > > > (intel_tc_port_in_dp_alt_mode(dig_port) ||
> > > > intel_tc_port_in_legacy_mode(dig_port)))
> > > > adlp_tbt_to_dp_alt_switch_wa(encoder);
> > > >
> > > > - intel_dp->DP |= DDI_BUF_CTL_ENABLE;
> > > > - intel_de_write(dev_priv, DDI_BUF_CTL(port), intel_dp->DP);
> > > > + dig_port->saved_port_bits |= DDI_BUF_CTL_ENABLE;
> > > > + intel_de_write(dev_priv, DDI_BUF_CTL(port), dig_port->saved_port_bits);
> > > > intel_de_posting_read(dev_priv, DDI_BUF_CTL(port));
> > > >
> > > > intel_wait_ddi_buf_active(dev_priv, port);
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > index 189c5737e63a..2346cd32f5a7 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > > @@ -6025,7 +6025,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
> > > > intel_dp->pps.active_pipe = INVALID_PIPE;
> > > >
> > > > /* Preserve the current hw state. */
> > > > - intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
> > > > + dig_port->saved_port_bits = intel_de_read(dev_priv, intel_dp->output_reg);
> > >
> > > Isn't this going to potentially clobber the lane reversal setting we
> > > determined from the VBT near the beginning of intel_ddi_init()?
> > >
> > >
> > > Matt
> > >
> > > > intel_dp->attached_connector = intel_connector;
> > > >
> > > > if (_intel_dp_is_port_edp(dev_priv, intel_encoder->devdata, port)) {
> > > > --
> > > > 2.40.1
> > > >
> > >
> > > --
> > > Matt Roper
> > > Graphics Software Engineer
> > > Linux GPU Platform Enablement
> > > Intel Corporation
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH v4 11/30] drm/i915/display: Rename intel_dp->DP
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (9 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 10/30] drm/i915/display: Consolidate saved port bits in intel_digital_port Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 12/30] drm/i915/xe2lpd: Move D2D enable/disable Lucas De Marchi
` (21 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, intel-xe
Now that DDI doesn't use that field anymore and it's restricted to
display/g4x_dp.c, rename it to follow the correspondent output_reg
field. This should avoid misuses of the old DP field, which would not
end up having the desired effect, and also make it clear what is
stashed in this variable.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/g4x_dp.c | 118 +++++++++---------
.../drm/i915/display/intel_display_types.h | 2 +-
2 files changed, 60 insertions(+), 60 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index e8ee0a08947e..b9e2ceb90806 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -117,27 +117,27 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
/* Preserve the BIOS-computed detected bit. This is
* supposed to be read-only.
*/
- intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
+ intel_dp->output_reg_bits = intel_de_read(dev_priv, intel_dp->output_reg) & DP_DETECTED;
/* Handle DP bits in common between all three register formats */
- intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
- intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
+ intel_dp->output_reg_bits |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
+ intel_dp->output_reg_bits |= DP_PORT_WIDTH(pipe_config->lane_count);
/* Split out the IBX/CPU vs CPT settings */
if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) {
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
- intel_dp->DP |= DP_SYNC_HS_HIGH;
+ intel_dp->output_reg_bits |= DP_SYNC_HS_HIGH;
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
- intel_dp->DP |= DP_SYNC_VS_HIGH;
- intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
+ intel_dp->output_reg_bits |= DP_SYNC_VS_HIGH;
+ intel_dp->output_reg_bits |= DP_LINK_TRAIN_OFF_CPT;
if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
- intel_dp->DP |= DP_ENHANCED_FRAMING;
+ intel_dp->output_reg_bits |= DP_ENHANCED_FRAMING;
- intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe);
+ intel_dp->output_reg_bits |= DP_PIPE_SEL_IVB(crtc->pipe);
} else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
- intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
+ intel_dp->output_reg_bits |= DP_LINK_TRAIN_OFF_CPT;
intel_de_rmw(dev_priv, TRANS_DP_CTL(crtc->pipe),
TRANS_DP_ENH_FRAMING,
@@ -145,21 +145,21 @@ static void intel_dp_prepare(struct intel_encoder *encoder,
TRANS_DP_ENH_FRAMING : 0);
} else {
if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
- intel_dp->DP |= DP_COLOR_RANGE_16_235;
+ intel_dp->output_reg_bits |= DP_COLOR_RANGE_16_235;
if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
- intel_dp->DP |= DP_SYNC_HS_HIGH;
+ intel_dp->output_reg_bits |= DP_SYNC_HS_HIGH;
if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
- intel_dp->DP |= DP_SYNC_VS_HIGH;
- intel_dp->DP |= DP_LINK_TRAIN_OFF;
+ intel_dp->output_reg_bits |= DP_SYNC_VS_HIGH;
+ intel_dp->output_reg_bits |= DP_LINK_TRAIN_OFF;
if (pipe_config->enhanced_framing)
- intel_dp->DP |= DP_ENHANCED_FRAMING;
+ intel_dp->output_reg_bits |= DP_ENHANCED_FRAMING;
if (IS_CHERRYVIEW(dev_priv))
- intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe);
+ intel_dp->output_reg_bits |= DP_PIPE_SEL_CHV(crtc->pipe);
else
- intel_dp->DP |= DP_PIPE_SEL(crtc->pipe);
+ intel_dp->output_reg_bits |= DP_PIPE_SEL(crtc->pipe);
}
}
@@ -200,14 +200,14 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp,
drm_dbg_kms(&dev_priv->drm, "enabling eDP PLL for clock %d\n",
pipe_config->port_clock);
- intel_dp->DP &= ~DP_PLL_FREQ_MASK;
+ intel_dp->output_reg_bits &= ~DP_PLL_FREQ_MASK;
if (pipe_config->port_clock == 162000)
- intel_dp->DP |= DP_PLL_FREQ_162MHZ;
+ intel_dp->output_reg_bits |= DP_PLL_FREQ_162MHZ;
else
- intel_dp->DP |= DP_PLL_FREQ_270MHZ;
+ intel_dp->output_reg_bits |= DP_PLL_FREQ_270MHZ;
- intel_de_write(dev_priv, DP_A, intel_dp->DP);
+ intel_de_write(dev_priv, DP_A, intel_dp->output_reg_bits);
intel_de_posting_read(dev_priv, DP_A);
udelay(500);
@@ -220,9 +220,9 @@ static void ilk_edp_pll_on(struct intel_dp *intel_dp,
if (IS_IRONLAKE(dev_priv))
intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
- intel_dp->DP |= DP_PLL_ENABLE;
+ intel_dp->output_reg_bits |= DP_PLL_ENABLE;
- intel_de_write(dev_priv, DP_A, intel_dp->DP);
+ intel_de_write(dev_priv, DP_A, intel_dp->output_reg_bits);
intel_de_posting_read(dev_priv, DP_A);
udelay(200);
}
@@ -239,9 +239,9 @@ static void ilk_edp_pll_off(struct intel_dp *intel_dp,
drm_dbg_kms(&dev_priv->drm, "disabling eDP PLL\n");
- intel_dp->DP &= ~DP_PLL_ENABLE;
+ intel_dp->output_reg_bits &= ~DP_PLL_ENABLE;
- intel_de_write(dev_priv, DP_A, intel_dp->DP);
+ intel_de_write(dev_priv, DP_A, intel_dp->output_reg_bits);
intel_de_posting_read(dev_priv, DP_A);
udelay(200);
}
@@ -423,17 +423,17 @@ intel_dp_link_down(struct intel_encoder *encoder,
if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) ||
(HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
- intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
- intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
+ intel_dp->output_reg_bits &= ~DP_LINK_TRAIN_MASK_CPT;
+ intel_dp->output_reg_bits |= DP_LINK_TRAIN_PAT_IDLE_CPT;
} else {
- intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
- intel_dp->DP |= DP_LINK_TRAIN_PAT_IDLE;
+ intel_dp->output_reg_bits &= ~DP_LINK_TRAIN_MASK;
+ intel_dp->output_reg_bits |= DP_LINK_TRAIN_PAT_IDLE;
}
- intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
+ intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->output_reg_bits);
intel_de_posting_read(dev_priv, intel_dp->output_reg);
- intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
- intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
+ intel_dp->output_reg_bits &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
+ intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->output_reg_bits);
intel_de_posting_read(dev_priv, intel_dp->output_reg);
/*
@@ -450,14 +450,14 @@ intel_dp_link_down(struct intel_encoder *encoder,
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
/* always enable with pattern 1 (as per spec) */
- intel_dp->DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
- intel_dp->DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
+ intel_dp->output_reg_bits &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK);
+ intel_dp->output_reg_bits |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) |
DP_LINK_TRAIN_PAT_1;
- intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
+ intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->output_reg_bits);
intel_de_posting_read(dev_priv, intel_dp->output_reg);
- intel_dp->DP &= ~DP_PORT_EN;
- intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
+ intel_dp->output_reg_bits &= ~DP_PORT_EN;
+ intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->output_reg_bits);
intel_de_posting_read(dev_priv, intel_dp->output_reg);
intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
@@ -565,24 +565,24 @@ cpt_set_link_train(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- intel_dp->DP &= ~DP_LINK_TRAIN_MASK_CPT;
+ intel_dp->output_reg_bits &= ~DP_LINK_TRAIN_MASK_CPT;
switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
case DP_TRAINING_PATTERN_DISABLE:
- intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
+ intel_dp->output_reg_bits |= DP_LINK_TRAIN_OFF_CPT;
break;
case DP_TRAINING_PATTERN_1:
- intel_dp->DP |= DP_LINK_TRAIN_PAT_1_CPT;
+ intel_dp->output_reg_bits |= DP_LINK_TRAIN_PAT_1_CPT;
break;
case DP_TRAINING_PATTERN_2:
- intel_dp->DP |= DP_LINK_TRAIN_PAT_2_CPT;
+ intel_dp->output_reg_bits |= DP_LINK_TRAIN_PAT_2_CPT;
break;
default:
MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
return;
}
- intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
+ intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->output_reg_bits);
intel_de_posting_read(dev_priv, intel_dp->output_reg);
}
@@ -593,24 +593,24 @@ g4x_set_link_train(struct intel_dp *intel_dp,
{
struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
- intel_dp->DP &= ~DP_LINK_TRAIN_MASK;
+ intel_dp->output_reg_bits &= ~DP_LINK_TRAIN_MASK;
switch (intel_dp_training_pattern_symbol(dp_train_pat)) {
case DP_TRAINING_PATTERN_DISABLE:
- intel_dp->DP |= DP_LINK_TRAIN_OFF;
+ intel_dp->output_reg_bits |= DP_LINK_TRAIN_OFF;
break;
case DP_TRAINING_PATTERN_1:
- intel_dp->DP |= DP_LINK_TRAIN_PAT_1;
+ intel_dp->output_reg_bits |= DP_LINK_TRAIN_PAT_1;
break;
case DP_TRAINING_PATTERN_2:
- intel_dp->DP |= DP_LINK_TRAIN_PAT_2;
+ intel_dp->output_reg_bits |= DP_LINK_TRAIN_PAT_2;
break;
default:
MISSING_CASE(intel_dp_training_pattern_symbol(dp_train_pat));
return;
}
- intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
+ intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->output_reg_bits);
intel_de_posting_read(dev_priv, intel_dp->output_reg);
}
@@ -630,11 +630,11 @@ static void intel_dp_enable_port(struct intel_dp *intel_dp,
* write to enable the port. Otherwise link training will
* fail when the power sequencer is freshly used for this port.
*/
- intel_dp->DP |= DP_PORT_EN;
+ intel_dp->output_reg_bits |= DP_PORT_EN;
if (crtc_state->has_audio)
- intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
+ intel_dp->output_reg_bits |= DP_AUDIO_OUTPUT_ENABLE;
- intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
+ intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->output_reg_bits);
intel_de_posting_read(dev_priv, intel_dp->output_reg);
}
@@ -1007,10 +1007,10 @@ g4x_set_signal_levels(struct intel_encoder *encoder,
drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
signal_levels);
- intel_dp->DP &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);
- intel_dp->DP |= signal_levels;
+ intel_dp->output_reg_bits &= ~(DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK);
+ intel_dp->output_reg_bits |= signal_levels;
- intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
+ intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->output_reg_bits);
intel_de_posting_read(dev_priv, intel_dp->output_reg);
}
@@ -1055,10 +1055,10 @@ snb_cpu_edp_set_signal_levels(struct intel_encoder *encoder,
drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
signal_levels);
- intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
- intel_dp->DP |= signal_levels;
+ intel_dp->output_reg_bits &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
+ intel_dp->output_reg_bits |= signal_levels;
- intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
+ intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->output_reg_bits);
intel_de_posting_read(dev_priv, intel_dp->output_reg);
}
@@ -1107,10 +1107,10 @@ ivb_cpu_edp_set_signal_levels(struct intel_encoder *encoder,
drm_dbg_kms(&dev_priv->drm, "Using signal levels %08x\n",
signal_levels);
- intel_dp->DP &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
- intel_dp->DP |= signal_levels;
+ intel_dp->output_reg_bits &= ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
+ intel_dp->output_reg_bits |= signal_levels;
- intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->DP);
+ intel_de_write(dev_priv, intel_dp->output_reg, intel_dp->output_reg_bits);
intel_de_posting_read(dev_priv, intel_dp->output_reg);
}
@@ -1237,7 +1237,7 @@ static void intel_dp_encoder_reset(struct drm_encoder *encoder)
struct drm_i915_private *dev_priv = to_i915(encoder->dev);
struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(encoder));
- intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg);
+ intel_dp->output_reg_bits = intel_de_read(dev_priv, intel_dp->output_reg);
intel_dp->reset_link_params = true;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 3c54fe2bfddd..37cd0e70e3aa 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1701,7 +1701,7 @@ struct intel_psr {
struct intel_dp {
i915_reg_t output_reg;
- u32 DP;
+ u32 output_reg_bits;
int link_rate;
u8 lane_count;
u8 sink_count;
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 12/30] drm/i915/xe2lpd: Move D2D enable/disable
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (10 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 11/30] drm/i915/display: Rename intel_dp->DP Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 13/30] drm/i915/xe2lpd: Move registers to PICA Lucas De Marchi
` (20 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Matt Roper, Lucas De Marchi, intel-xe
Bits to enable/disable and check state for D2D moved from
XELPDP_PORT_BUF_CTL1 to DDI_BUF_CTL (now named DDI_CTL_DE in the spec).
Make the functions mtl_ddi_disable_d2d() and mtl_ddi_enable_d2d generic
to work with multiple reg location and bitfield layout.
v2: Set/Clear XE2LPD_DDI_BUF_D2D_LINK_ENABLE in saved_port_bits when
enabling/disabling D2D so DDI_BUF_CTL is correctly programmed in
other places without overriding these bits (Clint)
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 46 +++++++++++++++++-------
drivers/gpu/drm/i915/i915_reg.h | 2 ++
2 files changed, 36 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 29c9386659ff..b09c00f8f346 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2355,14 +2355,25 @@ static void
mtl_ddi_enable_d2d(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
enum port port = encoder->port;
+ i915_reg_t reg;
+ u32 set_bits, wait_bits;
+
+ if (DISPLAY_VER(dev_priv) >= 20) {
+ reg = DDI_BUF_CTL(port);
+ set_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+ wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
+ dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+ } else {
+ reg = XELPDP_PORT_BUF_CTL1(port);
+ set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
+ wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
+ }
- intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port), 0,
- XELPDP_PORT_BUF_D2D_LINK_ENABLE);
-
- if (wait_for_us((intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
- XELPDP_PORT_BUF_D2D_LINK_STATE), 100)) {
- drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for PORT_BUF_CTL %c\n",
+ intel_de_rmw(dev_priv, reg, 0, set_bits);
+ if (wait_for_us(intel_de_read(dev_priv, reg) & wait_bits, 100)) {
+ drm_err(&dev_priv->drm, "Timeout waiting for D2D Link enable for DDI/PORT_BUF_CTL %c\n",
port_name(port));
}
}
@@ -2808,14 +2819,25 @@ static void
mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
{
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
enum port port = encoder->port;
+ i915_reg_t reg;
+ u32 clr_bits, wait_bits;
+
+ if (DISPLAY_VER(dev_priv) >= 20) {
+ reg = DDI_BUF_CTL(port);
+ clr_bits = XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+ wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
+ dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
+ } else {
+ reg = XELPDP_PORT_BUF_CTL1(port);
+ clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
+ wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
+ }
- intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
- XELPDP_PORT_BUF_D2D_LINK_ENABLE, 0);
-
- if (wait_for_us(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) &
- XELPDP_PORT_BUF_D2D_LINK_STATE), 100))
- drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for PORT_BUF_CTL %c\n",
+ intel_de_rmw(dev_priv, reg, clr_bits, 0);
+ if (wait_for_us(!(intel_de_read(dev_priv, reg) & wait_bits), 100))
+ drm_err(&dev_priv->drm, "Timeout waiting for D2D Link disable for DDI/PORT_BUF_CTL %c\n",
port_name(port));
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e00e4d569ba9..2f5dd5361263 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5678,6 +5678,8 @@ enum skl_power_gate {
/* Known as DDI_CTL_DE in MTL+ */
#define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B)
#define DDI_BUF_CTL_ENABLE (1 << 31)
+#define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29)
+#define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28)
#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
#define DDI_BUF_EMP_MASK (0xf << 24)
#define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20)
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 13/30] drm/i915/xe2lpd: Move registers to PICA
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (11 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 12/30] drm/i915/xe2lpd: Move D2D enable/disable Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 14/30] drm/i915/display: Fix style and conventions for DP AUX regs Lucas De Marchi
` (19 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Matt Roper, Lucas De Marchi, intel-xe
Some registers for DDI A/B moved to PICA and now follow the same format
as the ones for the PORT_TC ports. The wrapper here deals with 2 issues:
- Share the implementation between xe2lpd and previous
platforms: there are minor layout changes, it's mostly the
register location that changed
- Handle offsets after TC ports
v2:
- Explain better the trick to use just the second range (Matt Roper)
- Add missing conversions after rebase (Matt Roper)
- Use macro instead of inline function, avoiding includes in the
header (Jani)
- Prefix old macros with underscore so they don't get used by mistake,
and name the new ones using the previous names
v3: Use the same logic for the recently-introduced XELPDP_PORT_MSGBUS_TIMER
(Gustavo)
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 85 ++++++++++---------
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 63 ++++++++++++--
drivers/gpu/drm/i915/display/intel_ddi.c | 20 +++--
drivers/gpu/drm/i915/display/intel_tc.c | 16 ++--
4 files changed, 120 insertions(+), 64 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index e6d3027c821d..33dd67332a4e 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -100,7 +100,7 @@ static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_w
static void intel_clear_response_ready_flag(struct drm_i915_private *i915,
enum port port, int lane)
{
- intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
+ intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane),
0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET);
}
@@ -108,10 +108,10 @@ static void intel_cx0_bus_reset(struct drm_i915_private *i915, enum port port, i
{
enum phy phy = intel_port_to_phy(i915, port);
- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
XELPDP_PORT_M2P_TRANSACTION_RESET);
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
XELPDP_PORT_M2P_TRANSACTION_RESET,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy));
@@ -133,7 +133,7 @@ static void intel_cx0_bus_check_and_bump_timer(struct drm_i915_private *i915,
u32 val;
u32 timer_val;
- reg = XELPDP_PORT_MSGBUS_TIMER(port, lane);
+ reg = XELPDP_PORT_MSGBUS_TIMER(i915, port, lane);
val = intel_de_read(i915, reg);
if (!(val & XELPDP_PORT_MSGBUS_TIMER_TIMED_OUT)) {
@@ -163,7 +163,7 @@ static int intel_cx0_wait_for_ack(struct drm_i915_private *i915, enum port port,
enum phy phy = intel_port_to_phy(i915, port);
if (__intel_de_wait_for_register(i915,
- XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane),
+ XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane),
XELPDP_PORT_P2M_RESPONSE_READY,
XELPDP_PORT_P2M_RESPONSE_READY,
XELPDP_MSGBUS_TIMEOUT_FAST_US,
@@ -199,7 +199,7 @@ static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port,
int ack;
u32 val;
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
drm_dbg_kms(&i915->drm,
@@ -208,7 +208,7 @@ static int __intel_cx0_read_once(struct drm_i915_private *i915, enum port port,
return -ETIMEDOUT;
}
- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING |
XELPDP_PORT_M2P_COMMAND_READ |
XELPDP_PORT_M2P_ADDRESS(addr));
@@ -259,7 +259,7 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
int ack;
u32 val;
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
drm_dbg_kms(&i915->drm,
@@ -268,14 +268,14 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
return -ETIMEDOUT;
}
- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING |
(committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) |
XELPDP_PORT_M2P_DATA(data) |
XELPDP_PORT_M2P_ADDRESS(addr));
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
drm_dbg_kms(&i915->drm,
@@ -288,7 +288,7 @@ static int __intel_cx0_write_once(struct drm_i915_private *i915, enum port port,
ack = intel_cx0_wait_for_ack(i915, port, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val);
if (ack < 0)
return ack;
- } else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane)) &
+ } else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane)) &
XELPDP_PORT_P2M_ERROR_SET)) {
drm_dbg_kms(&i915->drm,
"PHY %c Error occurred during write command.\n", phy_name(phy));
@@ -2470,7 +2470,8 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
u32 val = 0;
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port), XELPDP_PORT_REVERSAL,
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port),
+ XELPDP_PORT_REVERSAL,
lane_reversal ? XELPDP_PORT_REVERSAL : 0);
if (lane_reversal)
@@ -2490,7 +2491,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
else
val |= crtc_state->cx0pll_state.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_SSC_ENABLE_PLLA |
XELPDP_SSC_ENABLE_PLLB, val);
@@ -2523,15 +2524,16 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
u8 lane_mask, u8 state)
{
enum phy phy = intel_port_to_phy(i915, port);
+ i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(i915, port);
int lane;
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+ intel_de_rmw(i915, buf_ctl2_reg,
intel_cx0_get_powerdown_state(INTEL_CX0_BOTH_LANES, XELPDP_LANE_POWERDOWN_NEW_STATE_MASK),
intel_cx0_get_powerdown_state(lane_mask, state));
/* Wait for pending transactions.*/
for_each_cx0_lane_in_mask(lane_mask, lane)
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(port, lane),
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
drm_dbg_kms(&i915->drm,
@@ -2540,12 +2542,12 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
intel_cx0_bus_reset(i915, port, lane);
}
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+ intel_de_rmw(i915, buf_ctl2_reg,
intel_cx0_get_powerdown_update(INTEL_CX0_BOTH_LANES),
intel_cx0_get_powerdown_update(lane_mask));
/* Update Timeout Value */
- if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
+ if (__intel_de_wait_for_register(i915, buf_ctl2_reg,
intel_cx0_get_powerdown_update(lane_mask), 0,
XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
@@ -2554,10 +2556,10 @@ static void intel_cx0_powerdown_change_sequence(struct drm_i915_private *i915,
static void intel_cx0_setup_powerdown(struct drm_i915_private *i915, enum port port)
{
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port),
XELPDP_POWER_STATE_READY_MASK,
XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY));
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(port),
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(i915, port),
XELPDP_POWER_STATE_ACTIVE_MASK |
XELPDP_PLL_LANE_STAGGERING_DELAY_MASK,
XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) |
@@ -2602,28 +2604,28 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
XELPDP_LANE_PHY_CURRENT_STATUS(1))
: XELPDP_LANE_PHY_CURRENT_STATUS(0);
- if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(port),
+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL1(i915, port),
XELPDP_PORT_BUF_SOC_PHY_READY,
XELPDP_PORT_BUF_SOC_PHY_READY,
XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n",
phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port),
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port),
XELPDP_LANE_PIPE_RESET(0) | XELPDP_LANE_PIPE_RESET(1),
lane_pipe_reset);
- if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(port),
+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_BUF_CTL2(i915, port),
lane_phy_current_status, lane_phy_current_status,
XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(port),
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, port),
intel_cx0_get_pclk_refclk_request(owned_lane_mask),
intel_cx0_get_pclk_refclk_request(lane_mask));
- if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(port),
+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, port),
intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
intel_cx0_get_pclk_refclk_ack(lane_mask),
XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
@@ -2634,9 +2636,10 @@ static void intel_cx0_phy_lane_reset(struct drm_i915_private *i915,
CX0_P2_STATE_RESET);
intel_cx0_setup_powerdown(i915, port);
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(port), lane_pipe_reset, 0);
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port), lane_pipe_reset, 0);
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(port), lane_phy_current_status,
+ if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(i915, port),
+ lane_phy_current_status,
XELPDP_PORT_RESET_END_TIMEOUT))
drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n",
phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
@@ -2765,12 +2768,12 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
* 8. Set PORT_CLOCK_CTL register PCLK PLL Request
* LN<Lane for maxPCLK> to "1" to enable PLL.
*/
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
intel_cx0_get_pclk_pll_request(maxpclk_lane));
/* 9. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
- if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
intel_cx0_get_pclk_pll_ack(maxpclk_lane),
XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
@@ -2790,7 +2793,7 @@ int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
{
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
u32 clock;
- u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
+ u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
@@ -2843,11 +2846,11 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
*/
val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, crtc_state->port_clock));
val |= XELPDP_FORWARD_CLOCK_UNGATE;
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_FORWARD_CLOCK_UNGATE, val);
/* 2. Read back PORT_CLOCK_CTL REGISTER */
- val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
+ val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
/*
* 3. Follow the Display Voltage Frequency Switching - Sequence
@@ -2858,10 +2861,10 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
* 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL.
*/
val |= XELPDP_TBT_CLOCK_REQUEST;
- intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(encoder->port), val);
+ intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), val);
/* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
- if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
XELPDP_TBT_CLOCK_ACK,
XELPDP_TBT_CLOCK_ACK,
100, 0, NULL))
@@ -2913,7 +2916,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
* 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK>
* to "0" to disable PLL.
*/
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) |
intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0);
@@ -2923,7 +2926,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
/*
* 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
*/
- if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
@@ -2936,9 +2939,9 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
*/
/* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
XELPDP_DDI_CLOCK_SELECT_MASK, 0);
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
XELPDP_FORWARD_CLOCK_UNGATE, 0);
intel_cx0_phy_transaction_end(encoder, wakeref);
@@ -2957,11 +2960,11 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
/*
* 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL.
*/
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
XELPDP_TBT_CLOCK_REQUEST, 0);
/* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
- if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ if (__intel_de_wait_for_register(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL))
drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
encoder->base.base.id, encoder->base.name, phy_name(phy));
@@ -2974,7 +2977,7 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
/*
* 5. Program PORT CLOCK CTRL register to disable and gate clocks
*/
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(encoder->port),
+ intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
XELPDP_DDI_CLOCK_SELECT_MASK |
XELPDP_FORWARD_CLOCK_UNGATE, 0);
@@ -3001,7 +3004,7 @@ intel_mtl_port_pll_type(struct intel_encoder *encoder,
* TODO: Determine the PLL type from the SW state, once MTL PLL
* handling is done via the standard shared DPLL framework.
*/
- u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(encoder->port));
+ u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
u32 clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
if (clock == XELPDP_DDI_CLOCK_SELECT_MAXPCLK ||
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
index b2db4cc366d6..ff7f10d91e50 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h
@@ -7,16 +7,39 @@
#define __INTEL_CX0_PHY_REGS_H__
#include "i915_reg_defs.h"
+#include "intel_display_limits.h"
+
+/*
+ * Wrapper macro to convert from port number to the index used in some of the
+ * registers. For Display version 20 and above it converts the port number to a
+ * single range, starting with the TC offsets. When used together with
+ * _PICK_EVEN_2RANGES(idx, PORT_TC1, ...), this single range will be the second
+ * range. Example:
+ *
+ * PORT_TC1 -> PORT_TC1
+ * PORT_TC2 -> PORT_TC2
+ * PORT_TC3 -> PORT_TC3
+ * PORT_TC4 -> PORT_TC4
+ * PORT_A -> PORT_TC4 + 1
+ * PORT_B -> PORT_TC4 + 2
+ * ...
+ */
+#define __xe2lpd_port_idx(port) \
+ (port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A)
#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A 0x64040
#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B 0x64140
#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1 0x16F240
#define _XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2 0x16F440
-#define XELPDP_PORT_M2P_MSGBUS_CTL(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define _XELPDP_PORT_M2P_MSGBUS_CTL(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4)
+#define XELPDP_PORT_M2P_MSGBUS_CTL(i915__, port, lane) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_M2P_MSGBUS_CTL(__xe2lpd_port_idx(port), lane) : \
+ _XELPDP_PORT_M2P_MSGBUS_CTL(port, lane))
#define XELPDP_PORT_M2P_TRANSACTION_PENDING REG_BIT(31)
#define XELPDP_PORT_M2P_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
#define XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED REG_FIELD_PREP(XELPDP_PORT_M2P_COMMAND_TYPE_MASK, 0x1)
@@ -27,11 +50,16 @@
#define XELPDP_PORT_M2P_TRANSACTION_RESET REG_BIT(15)
#define XELPDP_PORT_M2P_ADDRESS_MASK REG_GENMASK(11, 0)
#define XELPDP_PORT_M2P_ADDRESS(val) REG_FIELD_PREP(XELPDP_PORT_M2P_ADDRESS_MASK, val)
-#define XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+
+#define _XELPDP_PORT_P2M_MSGBUS_STATUS(idx, lane) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_A, \
_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_B, \
_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC1, \
_XELPDP_PORT_M2P_MSGBUS_CTL_LN0_USBC2) + (lane) * 4 + 8)
+#define XELPDP_PORT_P2M_MSGBUS_STATUS(i915__, port, lane) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_P2M_MSGBUS_STATUS(__xe2lpd_port_idx(port), lane) : \
+ _XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane))
#define XELPDP_PORT_P2M_RESPONSE_READY REG_BIT(31)
#define XELPDP_PORT_P2M_COMMAND_TYPE_MASK REG_GENMASK(30, 27)
#define XELPDP_PORT_P2M_COMMAND_READ_ACK 0x4
@@ -54,11 +82,15 @@
#define _XELPDP_PORT_BUF_CTL1_LN0_B 0x64104
#define _XELPDP_PORT_BUF_CTL1_LN0_USBC1 0x16F200
#define _XELPDP_PORT_BUF_CTL1_LN0_USBC2 0x16F400
-#define XELPDP_PORT_BUF_CTL1(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define _XELPDP_PORT_BUF_CTL1(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
_XELPDP_PORT_BUF_CTL1_LN0_A, \
_XELPDP_PORT_BUF_CTL1_LN0_B, \
_XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
_XELPDP_PORT_BUF_CTL1_LN0_USBC2))
+#define XELPDP_PORT_BUF_CTL1(i915__, port) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_BUF_CTL1(__xe2lpd_port_idx(port)) : \
+ _XELPDP_PORT_BUF_CTL1(port))
#define XELPDP_PORT_BUF_D2D_LINK_ENABLE REG_BIT(29)
#define XELPDP_PORT_BUF_D2D_LINK_STATE REG_BIT(28)
#define XELPDP_PORT_BUF_SOC_PHY_READY REG_BIT(24)
@@ -75,12 +107,15 @@
#define XELPDP_PORT_WIDTH_MASK REG_GENMASK(3, 1)
#define XELPDP_PORT_WIDTH(val) REG_FIELD_PREP(XELPDP_PORT_WIDTH_MASK, val)
-#define XELPDP_PORT_BUF_CTL2(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define _XELPDP_PORT_BUF_CTL2(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
_XELPDP_PORT_BUF_CTL1_LN0_A, \
_XELPDP_PORT_BUF_CTL1_LN0_B, \
_XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
_XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 4)
-
+#define XELPDP_PORT_BUF_CTL2(i915__, port) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_BUF_CTL2(__xe2lpd_port_idx(port)) : \
+ _XELPDP_PORT_BUF_CTL2(port))
#define XELPDP_LANE_PIPE_RESET(lane) _PICK(lane, REG_BIT(31), REG_BIT(30))
#define XELPDP_LANE_PHY_CURRENT_STATUS(lane) _PICK(lane, REG_BIT(29), REG_BIT(28))
#define XELPDP_LANE_POWERDOWN_UPDATE(lane) _PICK(lane, REG_BIT(25), REG_BIT(24))
@@ -95,11 +130,15 @@
#define XELPDP_POWER_STATE_READY_MASK REG_GENMASK(7, 4)
#define XELPDP_POWER_STATE_READY(val) REG_FIELD_PREP(XELPDP_POWER_STATE_READY_MASK, val)
-#define XELPDP_PORT_BUF_CTL3(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define _XELPDP_PORT_BUF_CTL3(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
_XELPDP_PORT_BUF_CTL1_LN0_A, \
_XELPDP_PORT_BUF_CTL1_LN0_B, \
_XELPDP_PORT_BUF_CTL1_LN0_USBC1, \
_XELPDP_PORT_BUF_CTL1_LN0_USBC2) + 8)
+#define XELPDP_PORT_BUF_CTL3(i915__, port) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_BUF_CTL3(__xe2lpd_port_idx(port)) : \
+ _XELPDP_PORT_BUF_CTL3(port))
#define XELPDP_PLL_LANE_STAGGERING_DELAY_MASK REG_GENMASK(15, 8)
#define XELPDP_PLL_LANE_STAGGERING_DELAY(val) REG_FIELD_PREP(XELPDP_PLL_LANE_STAGGERING_DELAY_MASK, val)
#define XELPDP_POWER_STATE_ACTIVE_MASK REG_GENMASK(3, 0)
@@ -114,11 +153,15 @@
#define _XELPDP_PORT_MSGBUS_TIMER_LN0_B 0x641d8
#define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC1 0x16f258
#define _XELPDP_PORT_MSGBUS_TIMER_LN0_USBC2 0x16f458
-#define XELPDP_PORT_MSGBUS_TIMER(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define _XELPDP_PORT_MSGBUS_TIMER(port, lane) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
_XELPDP_PORT_MSGBUS_TIMER_LN0_A, \
_XELPDP_PORT_MSGBUS_TIMER_LN0_B, \
_XELPDP_PORT_MSGBUS_TIMER_LN0_USBC1, \
_XELPDP_PORT_MSGBUS_TIMER_LN0_USBC2) + (lane) * 4)
+#define XELPDP_PORT_MSGBUS_TIMER(i915__, port, lane) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_MSGBUS_TIMER(__xe2lpd_port_idx(port), lane) : \
+ _XELPDP_PORT_MSGBUS_TIMER(port, lane))
#define XELPDP_PORT_MSGBUS_TIMER_TIMED_OUT REG_BIT(31)
#define XELPDP_PORT_MSGBUS_TIMER_VAL_MASK REG_GENMASK(23, 0)
#define XELPDP_PORT_MSGBUS_TIMER_VAL(val) REG_FIELD_PREP(XELPDP_PORT_MSGBUS_TIMER_VAL_MASK, val)
@@ -127,11 +170,15 @@
#define _XELPDP_PORT_CLOCK_CTL_B 0x641E0
#define _XELPDP_PORT_CLOCK_CTL_USBC1 0x16F260
#define _XELPDP_PORT_CLOCK_CTL_USBC2 0x16F460
-#define XELPDP_PORT_CLOCK_CTL(port) _MMIO(_PICK_EVEN_2RANGES(port, PORT_TC1, \
+#define _XELPDP_PORT_CLOCK_CTL(idx) _MMIO(_PICK_EVEN_2RANGES(idx, PORT_TC1, \
_XELPDP_PORT_CLOCK_CTL_A, \
_XELPDP_PORT_CLOCK_CTL_B, \
_XELPDP_PORT_CLOCK_CTL_USBC1, \
_XELPDP_PORT_CLOCK_CTL_USBC2))
+#define XELPDP_PORT_CLOCK_CTL(i915__, port) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_CLOCK_CTL(__xe2lpd_port_idx(port)) : \
+ _XELPDP_PORT_CLOCK_CTL(port))
#define XELPDP_LANE_PCLK_PLL_REQUEST(lane) REG_BIT(31 - ((lane) * 4))
#define XELPDP_LANE_PCLK_PLL_ACK(lane) REG_BIT(30 - ((lane) * 4))
#define XELPDP_LANE_PCLK_REFCLK_REQUEST(lane) REG_BIT(29 - ((lane) * 4))
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b09c00f8f346..f9bb5ad22203 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -177,7 +177,7 @@ static void mtl_wait_ddi_buf_idle(struct drm_i915_private *i915, enum port port)
int ret;
/* FIXME: find out why Bspec's 100us timeout is too short */
- ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) &
+ ret = wait_for_us((intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port)) &
XELPDP_PORT_BUF_PHY_IDLE), 10000);
if (ret)
drm_err(&i915->drm, "Timeout waiting for DDI BUF %c to get idle\n",
@@ -225,7 +225,9 @@ static void intel_wait_ddi_buf_active(struct drm_i915_private *dev_priv,
}
if (DISPLAY_VER(dev_priv) >= 14)
- ret = _wait_for(!(intel_de_read(dev_priv, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_PORT_BUF_PHY_IDLE),
+ ret = _wait_for(!(intel_de_read(dev_priv,
+ XELPDP_PORT_BUF_CTL1(dev_priv, port)) &
+ XELPDP_PORT_BUF_PHY_IDLE),
timeout_us, 10, 10);
else
ret = _wait_for(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) & DDI_BUF_IS_IDLE),
@@ -2366,7 +2368,7 @@ mtl_ddi_enable_d2d(struct intel_encoder *encoder)
wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
dig_port->saved_port_bits |= XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
} else {
- reg = XELPDP_PORT_BUF_CTL1(port);
+ reg = XELPDP_PORT_BUF_CTL1(dev_priv, port);
set_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
}
@@ -2386,7 +2388,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
enum port port = encoder->port;
u32 val;
- val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
+ val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(i915, port));
val &= ~XELPDP_PORT_WIDTH_MASK;
val |= XELPDP_PORT_WIDTH(mtl_get_port_width(crtc_state->lane_count));
@@ -2399,7 +2401,7 @@ static void mtl_port_buf_ctl_program(struct intel_encoder *encoder,
if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
val |= XELPDP_PORT_REVERSAL;
- intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
+ intel_de_write(i915, XELPDP_PORT_BUF_CTL1(i915, port), val);
}
static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
@@ -2410,7 +2412,7 @@ static void mtl_port_buf_ctl_io_selection(struct intel_encoder *encoder)
val = intel_tc_port_in_tbt_alt_mode(dig_port) ?
XELPDP_PORT_BUF_IO_SELECT_TBT : 0;
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(encoder->port),
+ intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port),
XELPDP_PORT_BUF_IO_SELECT_TBT, val);
}
@@ -2830,7 +2832,7 @@ mtl_ddi_disable_d2d_link(struct intel_encoder *encoder)
wait_bits = XE2LPD_DDI_BUF_D2D_LINK_STATE;
dig_port->saved_port_bits &= ~XE2LPD_DDI_BUF_D2D_LINK_ENABLE;
} else {
- reg = XELPDP_PORT_BUF_CTL1(port);
+ reg = XELPDP_PORT_BUF_CTL1(dev_priv, port);
clr_bits = XELPDP_PORT_BUF_D2D_LINK_ENABLE;
wait_bits = XELPDP_PORT_BUF_D2D_LINK_STATE;
}
@@ -2968,7 +2970,7 @@ static void intel_ddi_post_disable_dp(struct intel_atomic_state *state,
/* De-select Thunderbolt */
if (DISPLAY_VER(dev_priv) >= 14)
- intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(encoder->port),
+ intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, encoder->port),
XELPDP_PORT_BUF_IO_SELECT_TBT, 0);
}
@@ -3241,7 +3243,7 @@ static void intel_enable_ddi_hdmi(struct intel_atomic_state *state,
if (dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL)
port_buf |= XELPDP_PORT_REVERSAL;
- intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(port),
+ intel_de_rmw(dev_priv, XELPDP_PORT_BUF_CTL1(dev_priv, port),
XELPDP_PORT_WIDTH_MASK | XELPDP_PORT_REVERSAL, port_buf);
dig_port->saved_port_bits |= DDI_PORT_WIDTH(lane_count);
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 3c94bbcb5497..678693978892 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -958,10 +958,11 @@ xelpdp_tc_phy_tcss_power_is_enabled(struct intel_tc_port *tc)
{
struct drm_i915_private *i915 = tc_to_i915(tc);
enum port port = tc->dig_port->base.port;
+ i915_reg_t reg = XELPDP_PORT_BUF_CTL1(i915, port);
assert_tc_cold_blocked(tc);
- return intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_TCSS_POWER_STATE;
+ return intel_de_read(i915, reg) & XELPDP_TCSS_POWER_STATE;
}
static bool
@@ -984,16 +985,17 @@ static void __xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool ena
{
struct drm_i915_private *i915 = tc_to_i915(tc);
enum port port = tc->dig_port->base.port;
+ i915_reg_t reg = XELPDP_PORT_BUF_CTL1(i915, port);
u32 val;
assert_tc_cold_blocked(tc);
- val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
+ val = intel_de_read(i915, reg);
if (enable)
val |= XELPDP_TCSS_POWER_REQUEST;
else
val &= ~XELPDP_TCSS_POWER_REQUEST;
- intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
+ intel_de_write(i915, reg, val);
}
static bool xelpdp_tc_phy_enable_tcss_power(struct intel_tc_port *tc, bool enable)
@@ -1020,26 +1022,28 @@ static void xelpdp_tc_phy_take_ownership(struct intel_tc_port *tc, bool take)
{
struct drm_i915_private *i915 = tc_to_i915(tc);
enum port port = tc->dig_port->base.port;
+ i915_reg_t reg = XELPDP_PORT_BUF_CTL1(i915, port);
u32 val;
assert_tc_cold_blocked(tc);
- val = intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port));
+ val = intel_de_read(i915, reg);
if (take)
val |= XELPDP_TC_PHY_OWNERSHIP;
else
val &= ~XELPDP_TC_PHY_OWNERSHIP;
- intel_de_write(i915, XELPDP_PORT_BUF_CTL1(port), val);
+ intel_de_write(i915, reg, val);
}
static bool xelpdp_tc_phy_is_owned(struct intel_tc_port *tc)
{
struct drm_i915_private *i915 = tc_to_i915(tc);
enum port port = tc->dig_port->base.port;
+ i915_reg_t reg = XELPDP_PORT_BUF_CTL1(i915, port);
assert_tc_cold_blocked(tc);
- return intel_de_read(i915, XELPDP_PORT_BUF_CTL1(port)) & XELPDP_TC_PHY_OWNERSHIP;
+ return intel_de_read(i915, reg) & XELPDP_TC_PHY_OWNERSHIP;
}
static void xelpdp_tc_phy_get_hw_state(struct intel_tc_port *tc)
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 14/30] drm/i915/display: Fix style and conventions for DP AUX regs
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (12 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 13/30] drm/i915/xe2lpd: Move registers to PICA Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 15/30] drm/i915/display: Use _PICK_EVEN_2RANGES() in " Lucas De Marchi
` (18 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Matt Roper, Lucas De Marchi, intel-xe
Fix some whitespace issues for register definitions and keep the defines
for DP_AUX_CH_CTL and DP_AUX_CH_DATA in the right place: together with
the bit definition.
While at it add a TODO entry that those defines shouldn't be using an
implicit dev_priv.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
.../gpu/drm/i915/display/intel_dp_aux_regs.h | 72 +++++++++----------
1 file changed, 35 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
index 5185345277c7..4503d94115d7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
@@ -13,48 +13,28 @@
* packet size supported is 20 bytes in each direction, hence the 5 fixed data
* registers
*/
-#define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
-#define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
-
-#define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
-#define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
-
-#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL)
-#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
-
-#define _XELPDP_USBC1_AUX_CH_CTL 0x16F210
-#define _XELPDP_USBC2_AUX_CH_CTL 0x16F410
-#define _XELPDP_USBC3_AUX_CH_CTL 0x16F610
-#define _XELPDP_USBC4_AUX_CH_CTL 0x16F810
-
-#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
- _DPA_AUX_CH_CTL, \
- _DPB_AUX_CH_CTL, \
- 0, /* port/aux_ch C is non-existent */ \
- _XELPDP_USBC1_AUX_CH_CTL, \
- _XELPDP_USBC2_AUX_CH_CTL, \
- _XELPDP_USBC3_AUX_CH_CTL, \
- _XELPDP_USBC4_AUX_CH_CTL))
-
-#define _XELPDP_USBC1_AUX_CH_DATA1 0x16F214
-#define _XELPDP_USBC2_AUX_CH_DATA1 0x16F414
-#define _XELPDP_USBC3_AUX_CH_DATA1 0x16F614
-#define _XELPDP_USBC4_AUX_CH_DATA1 0x16F814
-
-#define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \
- _DPA_AUX_CH_DATA1, \
- _DPB_AUX_CH_DATA1, \
- 0, /* port/aux_ch C is non-existent */ \
- _XELPDP_USBC1_AUX_CH_DATA1, \
- _XELPDP_USBC2_AUX_CH_DATA1, \
- _XELPDP_USBC3_AUX_CH_DATA1, \
- _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
+/* TODO: Remove implicit dev_priv */
+#define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
+#define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
+#define _XELPDP_USBC1_AUX_CH_CTL 0x16f210
+#define _XELPDP_USBC2_AUX_CH_CTL 0x16f410
+#define _XELPDP_USBC3_AUX_CH_CTL 0x16f610
+#define _XELPDP_USBC4_AUX_CH_CTL 0x16f810
+#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, \
+ _DPB_AUX_CH_CTL)
+#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
+ _DPA_AUX_CH_CTL, \
+ _DPB_AUX_CH_CTL, \
+ 0, /* port/aux_ch C is non-existent */ \
+ _XELPDP_USBC1_AUX_CH_CTL, \
+ _XELPDP_USBC2_AUX_CH_CTL, \
+ _XELPDP_USBC3_AUX_CH_CTL, \
+ _XELPDP_USBC4_AUX_CH_CTL))
#define DP_AUX_CH_CTL_SEND_BUSY REG_BIT(31)
#define DP_AUX_CH_CTL_DONE REG_BIT(30)
#define DP_AUX_CH_CTL_INTERRUPT REG_BIT(29)
#define DP_AUX_CH_CTL_TIME_OUT_ERROR REG_BIT(28)
-
#define DP_AUX_CH_CTL_TIME_OUT_MASK REG_GENMASK(27, 26)
#define DP_AUX_CH_CTL_TIME_OUT_400us REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 0)
#define DP_AUX_CH_CTL_TIME_OUT_600us REG_FIELD_PREP(DP_AUX_CH_CTL_TIME_OUT_MASK, 1)
@@ -83,4 +63,22 @@
#define DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK REG_GENMASK(4, 0) /* skl+ */
#define DP_AUX_CH_CTL_SYNC_PULSE_SKL(c) REG_FIELD_PREP(DP_AUX_CH_CTL_SYNC_PULSE_SKL_MASK, (c) - 1)
+/* TODO: Remove implicit dev_priv */
+#define _DPA_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64014)
+#define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
+#define _XELPDP_USBC1_AUX_CH_DATA1 0x16f214
+#define _XELPDP_USBC2_AUX_CH_DATA1 0x16f414
+#define _XELPDP_USBC3_AUX_CH_DATA1 0x16f614
+#define _XELPDP_USBC4_AUX_CH_DATA1 0x16f814
+#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, \
+ _DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
+#define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \
+ _DPA_AUX_CH_DATA1, \
+ _DPB_AUX_CH_DATA1, \
+ 0, /* port/aux_ch C is non-existent */ \
+ _XELPDP_USBC1_AUX_CH_DATA1, \
+ _XELPDP_USBC2_AUX_CH_DATA1, \
+ _XELPDP_USBC3_AUX_CH_DATA1, \
+ _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
+
#endif /* __INTEL_DP_AUX_REGS_H__ */
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 15/30] drm/i915/display: Use _PICK_EVEN_2RANGES() in DP AUX regs
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (13 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 14/30] drm/i915/display: Fix style and conventions for DP AUX regs Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 16/30] drm/i915/xe2lpd: Re-order " Lucas De Marchi
` (17 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Matt Roper, Lucas De Marchi, intel-xe
XELPDP_DP_AUX_CH_CTL() and XELPDP_DP_AUX_CH_DATA() use 2 ranges. Prefer
using _PICK_EVEN_2RANGES() over PICK().
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
.../gpu/drm/i915/display/intel_dp_aux_regs.h | 30 +++++++------------
1 file changed, 10 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
index 4503d94115d7..1e9e018a2a48 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
@@ -19,18 +19,13 @@
#define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
#define _XELPDP_USBC1_AUX_CH_CTL 0x16f210
#define _XELPDP_USBC2_AUX_CH_CTL 0x16f410
-#define _XELPDP_USBC3_AUX_CH_CTL 0x16f610
-#define _XELPDP_USBC4_AUX_CH_CTL 0x16f810
#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, \
_DPB_AUX_CH_CTL)
-#define XELPDP_DP_AUX_CH_CTL(aux_ch) _MMIO(_PICK(aux_ch, \
- _DPA_AUX_CH_CTL, \
- _DPB_AUX_CH_CTL, \
- 0, /* port/aux_ch C is non-existent */ \
- _XELPDP_USBC1_AUX_CH_CTL, \
- _XELPDP_USBC2_AUX_CH_CTL, \
- _XELPDP_USBC3_AUX_CH_CTL, \
- _XELPDP_USBC4_AUX_CH_CTL))
+#define XELPDP_DP_AUX_CH_CTL(aux_ch) \
+ _MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \
+ _DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL, \
+ _XELPDP_USBC1_AUX_CH_CTL, \
+ _XELPDP_USBC2_AUX_CH_CTL))
#define DP_AUX_CH_CTL_SEND_BUSY REG_BIT(31)
#define DP_AUX_CH_CTL_DONE REG_BIT(30)
#define DP_AUX_CH_CTL_INTERRUPT REG_BIT(29)
@@ -68,17 +63,12 @@
#define _DPB_AUX_CH_DATA1 (DISPLAY_MMIO_BASE(dev_priv) + 0x64114)
#define _XELPDP_USBC1_AUX_CH_DATA1 0x16f214
#define _XELPDP_USBC2_AUX_CH_DATA1 0x16f414
-#define _XELPDP_USBC3_AUX_CH_DATA1 0x16f614
-#define _XELPDP_USBC4_AUX_CH_DATA1 0x16f814
#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, \
_DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
-#define XELPDP_DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PICK(aux_ch, \
- _DPA_AUX_CH_DATA1, \
- _DPB_AUX_CH_DATA1, \
- 0, /* port/aux_ch C is non-existent */ \
- _XELPDP_USBC1_AUX_CH_DATA1, \
- _XELPDP_USBC2_AUX_CH_DATA1, \
- _XELPDP_USBC3_AUX_CH_DATA1, \
- _XELPDP_USBC4_AUX_CH_DATA1) + (i) * 4)
+#define XELPDP_DP_AUX_CH_DATA(aux_ch, i) \
+ _MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \
+ _DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1, \
+ _XELPDP_USBC1_AUX_CH_DATA1, \
+ _XELPDP_USBC2_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
#endif /* __INTEL_DP_AUX_REGS_H__ */
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 16/30] drm/i915/xe2lpd: Re-order DP AUX regs
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (14 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 15/30] drm/i915/display: Use _PICK_EVEN_2RANGES() in " Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 17/30] drm/i915/xe2lpd: Handle port AUX interrupts Lucas De Marchi
` (16 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Matt Roper, Lucas De Marchi, intel-xe
The address of CTL and DATA registers for DP AUX were changed in Xe2_LPD:
now they are all in a single range, with CH_A and CH_B coming right after
the USBC instances. Like was done when moving registers to PICA, use
a helper macro to remap the ch passed to an index that can be used to
calculate the right offset.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
.../i915/display/intel_display_power_well.c | 6 +++---
drivers/gpu/drm/i915/display/intel_dp_aux.c | 8 ++++----
.../gpu/drm/i915/display/intel_dp_aux_regs.h | 19 +++++++++++++++++--
3 files changed, 24 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 820b7d41a0a8..ca0714eba17a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1800,7 +1800,7 @@ static void xelpdp_aux_power_well_enable(struct drm_i915_private *dev_priv,
icl_tc_port_assert_ref_held(dev_priv, power_well,
aux_ch_to_digital_port(dev_priv, aux_ch));
- intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
+ intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(dev_priv, aux_ch),
XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
XELPDP_DP_AUX_CH_CTL_POWER_REQUEST);
@@ -1818,7 +1818,7 @@ static void xelpdp_aux_power_well_disable(struct drm_i915_private *dev_priv,
{
enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
- intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch),
+ intel_de_rmw(dev_priv, XELPDP_DP_AUX_CH_CTL(dev_priv, aux_ch),
XELPDP_DP_AUX_CH_CTL_POWER_REQUEST,
0);
usleep_range(10, 30);
@@ -1829,7 +1829,7 @@ static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv,
{
enum aux_ch aux_ch = i915_power_well_instance(power_well)->xelpdp.aux_ch;
- return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(aux_ch)) &
+ return intel_de_read(dev_priv, XELPDP_DP_AUX_CH_CTL(dev_priv, aux_ch)) &
XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c
index 2d173bd495a3..b90cad7f567b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c
@@ -687,10 +687,10 @@ static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp)
case AUX_CH_USBC2:
case AUX_CH_USBC3:
case AUX_CH_USBC4:
- return XELPDP_DP_AUX_CH_CTL(aux_ch);
+ return XELPDP_DP_AUX_CH_CTL(dev_priv, aux_ch);
default:
MISSING_CASE(aux_ch);
- return XELPDP_DP_AUX_CH_CTL(AUX_CH_A);
+ return XELPDP_DP_AUX_CH_CTL(dev_priv, AUX_CH_A);
}
}
@@ -707,10 +707,10 @@ static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index)
case AUX_CH_USBC2:
case AUX_CH_USBC3:
case AUX_CH_USBC4:
- return XELPDP_DP_AUX_CH_DATA(aux_ch, index);
+ return XELPDP_DP_AUX_CH_DATA(dev_priv, aux_ch, index);
default:
MISSING_CASE(aux_ch);
- return XELPDP_DP_AUX_CH_DATA(AUX_CH_A, index);
+ return XELPDP_DP_AUX_CH_DATA(dev_priv, AUX_CH_A, index);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
index 1e9e018a2a48..9d141e86a4b6 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
@@ -14,6 +14,13 @@
* registers
*/
+/*
+ * Wrapper macro to convert from aux_ch to the index used in some of the
+ * registers, similarly to __xe2lpd_port_idx().
+ */
+#define __xe2lpd_aux_ch_idx(aux_ch) \
+ (aux_ch >= AUX_CH_USBC1 ? aux_ch : AUX_CH_USBC4 + 1 + aux_ch - AUX_CH_A)
+
/* TODO: Remove implicit dev_priv */
#define _DPA_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64010)
#define _DPB_AUX_CH_CTL (DISPLAY_MMIO_BASE(dev_priv) + 0x64110)
@@ -21,11 +28,15 @@
#define _XELPDP_USBC2_AUX_CH_CTL 0x16f410
#define DP_AUX_CH_CTL(aux_ch) _MMIO_PORT(aux_ch, _DPA_AUX_CH_CTL, \
_DPB_AUX_CH_CTL)
-#define XELPDP_DP_AUX_CH_CTL(aux_ch) \
+#define _XELPDP_DP_AUX_CH_CTL(aux_ch) \
_MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \
_DPA_AUX_CH_CTL, _DPB_AUX_CH_CTL, \
_XELPDP_USBC1_AUX_CH_CTL, \
_XELPDP_USBC2_AUX_CH_CTL))
+#define XELPDP_DP_AUX_CH_CTL(i915__, aux_ch) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_DP_AUX_CH_CTL(__xe2lpd_aux_ch_idx(aux_ch)) : \
+ _XELPDP_DP_AUX_CH_CTL(aux_ch))
#define DP_AUX_CH_CTL_SEND_BUSY REG_BIT(31)
#define DP_AUX_CH_CTL_DONE REG_BIT(30)
#define DP_AUX_CH_CTL_INTERRUPT REG_BIT(29)
@@ -65,10 +76,14 @@
#define _XELPDP_USBC2_AUX_CH_DATA1 0x16f414
#define DP_AUX_CH_DATA(aux_ch, i) _MMIO(_PORT(aux_ch, _DPA_AUX_CH_DATA1, \
_DPB_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
-#define XELPDP_DP_AUX_CH_DATA(aux_ch, i) \
+#define _XELPDP_DP_AUX_CH_DATA(aux_ch, i) \
_MMIO(_PICK_EVEN_2RANGES(aux_ch, AUX_CH_USBC1, \
_DPA_AUX_CH_DATA1, _DPB_AUX_CH_DATA1, \
_XELPDP_USBC1_AUX_CH_DATA1, \
_XELPDP_USBC2_AUX_CH_DATA1) + (i) * 4) /* 5 registers */
+#define XELPDP_DP_AUX_CH_DATA(i915__, aux_ch, i) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_DP_AUX_CH_DATA(__xe2lpd_aux_ch_idx(aux_ch), i) : \
+ _XELPDP_DP_AUX_CH_DATA(aux_ch, i))
#endif /* __INTEL_DP_AUX_REGS_H__ */
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 17/30] drm/i915/xe2lpd: Handle port AUX interrupts
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (15 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 16/30] drm/i915/xe2lpd: Re-order " Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 18/30] drm/i915/xe2lpd: Read pin assignment from IOM Lucas De Marchi
` (15 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Matt Roper, intel-xe
From: Gustavo Sousa <gustavo.sousa@intel.com>
Differently from previous version, Xe2_LPD groups all port AUX interrupt
bits into PICA interrupt registers.
While at it, drop some trailing newlines.
BSpec: 68958, 69697
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_irq.c | 4 +++-
drivers/gpu/drm/i915/display/intel_hotplug_irq.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 5 ++---
3 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index 62ce55475554..bff4a76310c0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -792,7 +792,9 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
{
u32 mask;
- if (DISPLAY_VER(dev_priv) >= 14)
+ if (DISPLAY_VER(dev_priv) >= 20)
+ return 0;
+ else if (DISPLAY_VER(dev_priv) >= 14)
return TGL_DE_PORT_AUX_DDIA |
TGL_DE_PORT_AUX_DDIB;
else if (DISPLAY_VER(dev_priv) >= 13)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index 95a7ea94f417..3398cc21bd26 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -514,6 +514,9 @@ void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
u32 trigger_aux = iir & XELPDP_AUX_TC_MASK;
u32 pin_mask = 0, long_mask = 0;
+ if (DISPLAY_VER(i915) >= 20)
+ trigger_aux |= iir & XE2LPD_AUX_DDI_MASK;
+
for (pin = HPD_PORT_TC1; pin <= HPD_PORT_TC4; pin++) {
u32 val;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2f5dd5361263..2f115d339913 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4467,13 +4467,12 @@
#define PICAINTERRUPT_IMR _MMIO(0x16FE54)
#define PICAINTERRUPT_IIR _MMIO(0x16FE58)
#define PICAINTERRUPT_IER _MMIO(0x16FE5C)
-
#define XELPDP_DP_ALT_HOTPLUG(hpd_pin) REG_BIT(16 + _HPD_PIN_TC(hpd_pin))
#define XELPDP_DP_ALT_HOTPLUG_MASK REG_GENMASK(19, 16)
-
#define XELPDP_AUX_TC(hpd_pin) REG_BIT(8 + _HPD_PIN_TC(hpd_pin))
#define XELPDP_AUX_TC_MASK REG_GENMASK(11, 8)
-
+#define XE2LPD_AUX_DDI(hpd_pin) REG_BIT(6 + _HPD_PIN_DDI(hpd_pin))
+#define XE2LPD_AUX_DDI_MASK REG_GENMASK(7, 6)
#define XELPDP_TBT_HOTPLUG(hpd_pin) REG_BIT(_HPD_PIN_TC(hpd_pin))
#define XELPDP_TBT_HOTPLUG_MASK REG_GENMASK(3, 0)
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 18/30] drm/i915/xe2lpd: Read pin assignment from IOM
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (16 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 17/30] drm/i915/xe2lpd: Handle port AUX interrupts Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 19/30] drm/i915/xe2lpd: Enable odd size and panning for planar yuv Lucas De Marchi
` (14 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Matt Roper, Luca Coelho, intel-xe
From: Luca Coelho <luciano.coelho@intel.com>
Starting from display version 20, we need to read the pin assignment
from the IOM TCSS_DDI_STATUS register instead of reading it from the
FIA.
We use the pin assignment to decide the maximum lane count. So, to
support this change, add a new lnl_tc_port_get_max_lane_count() function
that reads from the TCSS_DDI_STATUS register and decides the maximum
lane count based on that.
BSpec: 69594
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_tc.c | 28 +++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 29 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index 678693978892..e9ced251c170 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -290,6 +290,31 @@ u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
DP_PIN_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
}
+static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
+{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ enum tc_port tc_port = intel_port_to_tc(i915, dig_port->base.port);
+ intel_wakeref_t wakeref;
+ u32 val, pin_assignment;
+
+ with_intel_display_power(i915, POWER_DOMAIN_DISPLAY_CORE, wakeref)
+ val = intel_de_read(i915, TCSS_DDI_STATUS(tc_port));
+
+ pin_assignment =
+ REG_FIELD_GET(TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK, val);
+
+ switch (pin_assignment) {
+ default:
+ MISSING_CASE(pin_assignment);
+ fallthrough;
+ case DP_PIN_ASSIGNMENT_D:
+ return 2;
+ case DP_PIN_ASSIGNMENT_C:
+ case DP_PIN_ASSIGNMENT_E:
+ return 4;
+ }
+}
+
static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
{
struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
@@ -348,6 +373,9 @@ int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port)
assert_tc_cold_blocked(tc);
+ if (DISPLAY_VER(i915) >= 20)
+ return lnl_tc_port_get_max_lane_count(dig_port);
+
if (DISPLAY_VER(i915) >= 14)
return mtl_tc_port_get_max_lane_count(dig_port);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 2f115d339913..efcf1461988f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6351,6 +6351,7 @@ enum skl_power_gate {
#define TCSS_DDI_STATUS(tc) _MMIO(_PICK_EVEN(tc, \
_TCSS_DDI_STATUS_1, \
_TCSS_DDI_STATUS_2))
+#define TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK REG_GENMASK(28, 25)
#define TCSS_DDI_STATUS_READY REG_BIT(2)
#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_TBT REG_BIT(1)
#define TCSS_DDI_STATUS_HPD_LIVE_STATUS_ALT REG_BIT(0)
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 19/30] drm/i915/xe2lpd: Enable odd size and panning for planar yuv
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (17 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 18/30] drm/i915/xe2lpd: Read pin assignment from IOM Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 20/30] drm/i915/xe2lpd: Add support for HPD Lucas De Marchi
` (13 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, intel-xe, Juha-Pekka Heikkilä
From: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Enable odd size and panning for planar yuv formats.
Cc: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic_plane.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index d7a0bd686e49..b1074350616c 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -981,6 +981,14 @@ int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
hsub = 2;
vsub = 2;
+ } else if (DISPLAY_VER(i915) >= 20 &&
+ intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
+ /*
+ * This allows NV12 and P0xx formats to have odd size and/or odd
+ * source coordinates on DISPLAY_VER(i915) >= 20
+ */
+ hsub = 1;
+ vsub = 1;
} else {
hsub = fb->format->hsub;
vsub = fb->format->vsub;
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 20/30] drm/i915/xe2lpd: Add support for HPD
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (18 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 19/30] drm/i915/xe2lpd: Enable odd size and panning for planar yuv Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 21/30] drm/i915/xe2lpd: Extend Wa_15010685871 Lucas De Marchi
` (12 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Matt Roper, Lucas De Marchi, intel-xe
From: Gustavo Sousa <gustavo.sousa@intel.com>
Hotplug setup for Xe2_LPD differs from Xe_LPD+ by the fact that the
extra programming for hotplug inversion and DDI HPD filter duration is
not necessary anymore. As mtp_hpd_irq_setup() is reasonably small,
prefer to fork it into a new function for Xe2_LPD instead of adding a
platform check.
v2: Add extra bspec reference and fix missing else (Matt Roper)
BSpec: 68970, 69940
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
.../gpu/drm/i915/display/intel_hotplug_irq.c | 21 +++++++++++++++++--
1 file changed, 19 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index 3398cc21bd26..f07047e9cb30 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -163,7 +163,9 @@ static void intel_hpd_init_pins(struct drm_i915_private *dev_priv)
(!HAS_PCH_SPLIT(dev_priv) || HAS_PCH_NOP(dev_priv)))
return;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_LNL)
+ hpd->pch_hpd = hpd_mtp;
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
hpd->pch_hpd = hpd_sde_dg1;
else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
hpd->pch_hpd = hpd_mtp;
@@ -1063,6 +1065,19 @@ static void mtp_hpd_irq_setup(struct drm_i915_private *i915)
mtp_tc_hpd_detection_setup(i915);
}
+static void xe2lpd_sde_hpd_irq_setup(struct drm_i915_private *i915)
+{
+ u32 hotplug_irqs, enabled_irqs;
+
+ enabled_irqs = intel_hpd_enabled_irqs(i915, i915->display.hotplug.pch_hpd);
+ hotplug_irqs = intel_hpd_hotplug_irqs(i915, i915->display.hotplug.pch_hpd);
+
+ ibx_display_interrupt_update(i915, hotplug_irqs, enabled_irqs);
+
+ mtp_ddi_hpd_detection_setup(i915);
+ mtp_tc_hpd_detection_setup(i915);
+}
+
static bool is_xelpdp_pica_hpd_pin(enum hpd_pin hpd_pin)
{
return hpd_pin >= HPD_PORT_TC1 && hpd_pin <= HPD_PORT_TC4;
@@ -1122,7 +1137,9 @@ static void xelpdp_hpd_irq_setup(struct drm_i915_private *i915)
xelpdp_pica_hpd_detection_setup(i915);
- if (INTEL_PCH_TYPE(i915) >= PCH_MTP)
+ if (INTEL_PCH_TYPE(i915) >= PCH_LNL)
+ xe2lpd_sde_hpd_irq_setup(i915);
+ else if (INTEL_PCH_TYPE(i915) >= PCH_MTP)
mtp_hpd_irq_setup(i915);
}
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 21/30] drm/i915/xe2lpd: Extend Wa_15010685871
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (19 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 20/30] drm/i915/xe2lpd: Add support for HPD Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 22/30] drm/i915/lnl: Add gmbus/ddc support Lucas De Marchi
` (11 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Matt Roper, Lucas De Marchi, intel-xe
Xe2_LPD also needs workaround 15010685871. While adding the new display
version, also re-order the condition to follow the convention of new
version first.
v2: Remove redundant HAS_CDCLK_SQUASH(). As the platform or IP version
needing the workaround are handpicked, there is no need to also
check if tha platform has squashing support (Matt Roper)
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ad5251ba6fe1..656ff50def39 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1841,9 +1841,10 @@ static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i91
static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
{
- return ((IS_DG2(dev_priv) || DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0)) &&
- dev_priv->display.cdclk.hw.vco > 0 &&
- HAS_CDCLK_SQUASH(dev_priv));
+ return (DISPLAY_VER_FULL(dev_priv) == IP_VER(20, 0) ||
+ DISPLAY_VER_FULL(dev_priv) == IP_VER(14, 0) ||
+ IS_DG2(dev_priv)) &&
+ dev_priv->display.cdclk.hw.vco > 0;
}
static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 22/30] drm/i915/lnl: Add gmbus/ddc support
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (20 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 21/30] drm/i915/xe2lpd: Extend Wa_15010685871 Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 23/30] drm/i915/lnl: Add CDCLK table Lucas De Marchi
` (10 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Matt Roper, Lucas De Marchi, intel-xe
LNL's south display uses the same table as MTP. Check for LNL's fake PCH
to make it consistent with the other checks.
The VBT table doesn't contain the VBT -> spec mapping for LNL. Like in
other cases, uses the same as the previous platform.
Bspec: 68971, 20124
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 3 ++-
drivers/gpu/drm/i915/display/intel_gmbus.c | 5 ++++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index f735b035436c..099ef48d8172 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2194,7 +2194,8 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin)
const u8 *ddc_pin_map;
int i, n_entries;
- if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {
+ if (INTEL_PCH_TYPE(i915) >= PCH_LNL || HAS_PCH_MTP(i915) ||
+ IS_ALDERLAKE_P(i915)) {
ddc_pin_map = adlp_ddc_pin_map;
n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
} else if (IS_ALDERLAKE_S(i915)) {
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index e95ddb580ef6..801fabbccf7e 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -155,7 +155,10 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
const struct gmbus_pin *pins;
size_t size;
- if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
+ if (INTEL_PCH_TYPE(i915) >= PCH_LNL) {
+ pins = gmbus_pins_mtp;
+ size = ARRAY_SIZE(gmbus_pins_mtp);
+ } else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
pins = gmbus_pins_dg2;
size = ARRAY_SIZE(gmbus_pins_dg2);
} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 23/30] drm/i915/lnl: Add CDCLK table
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (21 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 22/30] drm/i915/lnl: Add gmbus/ddc support Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 24/30] drm/i915/xe2lpd: Add display power well Lucas De Marchi
` (9 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Matt Roper, Lucas De Marchi, intel-xe
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Add a new CDCLK table for Lunar Lake.
v2:
- Remove mdclk from the table as it's not needed (Matt Roper)
- Update waveform values to the latest from spec (Matt Roper)
- Rename functions and calculation to match by pixel rate (Lucas)
v3: Keep only the table: as far as intel_pixel_rate_to_cdclk()
is concerned, the minimum cdclk should still be half the pixel
rate on Xe2 (bspec 68858:
"Pipe maximum pixel rate = 2 * CDCLK frequency * Pipe Ratio")
(Matt Roper)
Bspec: 68861, 68858
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 30 +++++++++++++++++++++-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 656ff50def39..4cde78db83a1 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1382,6 +1382,31 @@ static const struct intel_cdclk_vals mtl_cdclk_table[] = {
{}
};
+static const struct intel_cdclk_vals lnl_cdclk_table[] = {
+ { .refclk = 38400, .cdclk = 153600, .divider = 2, .ratio = 16, .waveform = 0xaaaa },
+ { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
+ { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
+ { .refclk = 38400, .cdclk = 211200, .divider = 2, .ratio = 16, .waveform = 0xdbb6 },
+ { .refclk = 38400, .cdclk = 230400, .divider = 2, .ratio = 16, .waveform = 0xeeee },
+ { .refclk = 38400, .cdclk = 249600, .divider = 2, .ratio = 16, .waveform = 0xf7de },
+ { .refclk = 38400, .cdclk = 268800, .divider = 2, .ratio = 16, .waveform = 0xfefe },
+ { .refclk = 38400, .cdclk = 288000, .divider = 2, .ratio = 16, .waveform = 0xfffe },
+ { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 330000, .divider = 2, .ratio = 25, .waveform = 0xdbb6 },
+ { .refclk = 38400, .cdclk = 360000, .divider = 2, .ratio = 25, .waveform = 0xeeee },
+ { .refclk = 38400, .cdclk = 390000, .divider = 2, .ratio = 25, .waveform = 0xf7de },
+ { .refclk = 38400, .cdclk = 420000, .divider = 2, .ratio = 25, .waveform = 0xfefe },
+ { .refclk = 38400, .cdclk = 450000, .divider = 2, .ratio = 25, .waveform = 0xfffe },
+ { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 487200, .divider = 2, .ratio = 29, .waveform = 0xfefe },
+ { .refclk = 38400, .cdclk = 522000, .divider = 2, .ratio = 29, .waveform = 0xfffe },
+ { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0xffff },
+ { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
+ { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
+ { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
+ {}
+};
+
static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
{
const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
@@ -3591,7 +3616,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs = {
*/
void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
{
- if (DISPLAY_VER(dev_priv) >= 14) {
+ if (DISPLAY_VER(dev_priv) >= 20) {
+ dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
+ dev_priv->display.cdclk.table = lnl_cdclk_table;
+ } else if (DISPLAY_VER(dev_priv) >= 14) {
dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
dev_priv->display.cdclk.table = mtl_cdclk_table;
} else if (IS_DG2(dev_priv)) {
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 24/30] drm/i915/xe2lpd: Add display power well
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (22 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 23/30] drm/i915/lnl: Add CDCLK table Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 18:00 ` [Intel-gfx] [Intel-xe] " Matt Roper
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 25/30] drm/i915/xe2lpd: Add DC state support Lucas De Marchi
` (8 subsequent siblings)
32 siblings, 1 reply; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, intel-xe
From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Add Display Power Well for Xe2_LPD. It's mostly the same as Xe_LPD+,
so reuse the code. PGPICA1 contains type-C capable port slices
which requires the well to power powered up, so add new power well
definition for it.
The DC_OFF fake power well will be added in a follow up commit.
v2: Do not rmw as bit 31 is the only R/W bit in the regiser (Matt Roper)
BSpec: 68886
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
.../i915/display/intel_display_power_map.c | 36 +++++++++++++++-
.../i915/display/intel_display_power_well.c | 41 +++++++++++++++++++
.../i915/display/intel_display_power_well.h | 1 +
.../gpu/drm/i915/display/intel_dp_aux_regs.h | 5 +++
4 files changed, 82 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 0f1b93d139ca..31c11586ede5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1536,6 +1536,38 @@ static const struct i915_power_well_desc_list xelpdp_power_wells[] = {
I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
};
+I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc,
+ POWER_DOMAIN_PORT_DDI_LANES_TC1,
+ POWER_DOMAIN_PORT_DDI_LANES_TC2,
+ POWER_DOMAIN_PORT_DDI_LANES_TC3,
+ POWER_DOMAIN_PORT_DDI_LANES_TC4,
+ POWER_DOMAIN_AUX_USBC1,
+ POWER_DOMAIN_AUX_USBC2,
+ POWER_DOMAIN_AUX_USBC3,
+ POWER_DOMAIN_AUX_USBC4,
+ POWER_DOMAIN_AUX_TBT1,
+ POWER_DOMAIN_AUX_TBT2,
+ POWER_DOMAIN_AUX_TBT3,
+ POWER_DOMAIN_AUX_TBT4,
+ POWER_DOMAIN_INIT);
+
+static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
+ {
+ .instances = &I915_PW_INSTANCES(I915_PW("PICA_TC",
+ &xe2lpd_pwdoms_pica_tc,
+ .id = DISP_PW_ID_NONE),
+ ),
+ .ops = &xe2lpd_pica_power_well_ops,
+ },
+};
+
+static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
+ I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
+};
+
static void init_power_well_domains(const struct i915_power_well_instance *inst,
struct i915_power_well *power_well)
{
@@ -1643,7 +1675,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
return 0;
}
- if (DISPLAY_VER(i915) >= 14)
+ if (DISPLAY_VER(i915) >= 20)
+ return set_power_wells(power_domains, xe2lpd_power_wells);
+ else if (DISPLAY_VER(i915) >= 14)
return set_power_wells(power_domains, xelpdp_power_wells);
else if (IS_DG2(i915))
return set_power_wells(power_domains, xehpd_power_wells);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index ca0714eba17a..07d650050099 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1833,6 +1833,40 @@ static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv,
XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
}
+static void xe2lpd_pica_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ intel_de_write(dev_priv, XE2LPD_PICA_PW_CTL,
+ XE2LPD_PICA_CTL_POWER_REQUEST);
+
+ if (intel_de_wait_for_set(dev_priv, XE2LPD_PICA_PW_CTL,
+ XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
+ drm_dbg_kms(&dev_priv->drm, "pica power well enable timeout\n");
+
+ drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when enabled");
+ }
+}
+
+static void xe2lpd_pica_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ intel_de_write(dev_priv, XE2LPD_PICA_PW_CTL, 0);
+
+ if (intel_de_wait_for_clear(dev_priv, XE2LPD_PICA_PW_CTL,
+ XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
+ drm_dbg_kms(&dev_priv->drm, "pica power well disable timeout\n");
+
+ drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when disabled");
+ }
+}
+
+static bool xe2lpd_pica_power_well_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ return intel_de_read(dev_priv, XE2LPD_PICA_PW_CTL) &
+ XE2LPD_PICA_CTL_POWER_STATUS;
+}
+
const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
.sync_hw = i9xx_power_well_sync_hw_noop,
.enable = i9xx_always_on_power_well_noop,
@@ -1952,3 +1986,10 @@ const struct i915_power_well_ops xelpdp_aux_power_well_ops = {
.disable = xelpdp_aux_power_well_disable,
.is_enabled = xelpdp_aux_power_well_enabled,
};
+
+const struct i915_power_well_ops xe2lpd_pica_power_well_ops = {
+ .sync_hw = i9xx_power_well_sync_hw_noop,
+ .enable = xe2lpd_pica_power_well_enable,
+ .disable = xe2lpd_pica_power_well_disable,
+ .is_enabled = xe2lpd_pica_power_well_enabled,
+};
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index a8736588314d..9357a9a73c06 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -176,5 +176,6 @@ extern const struct i915_power_well_ops icl_aux_power_well_ops;
extern const struct i915_power_well_ops icl_ddi_power_well_ops;
extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
extern const struct i915_power_well_ops xelpdp_aux_power_well_ops;
+extern const struct i915_power_well_ops xe2lpd_pica_power_well_ops;
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
index 9d141e86a4b6..e8f426d5ce20 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
@@ -86,4 +86,9 @@
_XELPDP_DP_AUX_CH_DATA(__xe2lpd_aux_ch_idx(aux_ch), i) : \
_XELPDP_DP_AUX_CH_DATA(aux_ch, i))
+/* PICA Power Well Control */
+#define XE2LPD_PICA_PW_CTL _MMIO(0x16fe04)
+#define XE2LPD_PICA_CTL_POWER_REQUEST REG_BIT(31)
+#define XE2LPD_PICA_CTL_POWER_STATUS REG_BIT(30)
+
#endif /* __INTEL_DP_AUX_REGS_H__ */
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* Re: [Intel-gfx] [Intel-xe] [PATCH v4 24/30] drm/i915/xe2lpd: Add display power well
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 24/30] drm/i915/xe2lpd: Add display power well Lucas De Marchi
@ 2023-09-15 18:00 ` Matt Roper
0 siblings, 0 replies; 40+ messages in thread
From: Matt Roper @ 2023-09-15 18:00 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, intel-xe
On Fri, Sep 15, 2023 at 10:46:45AM -0700, Lucas De Marchi wrote:
> From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
>
> Add Display Power Well for Xe2_LPD. It's mostly the same as Xe_LPD+,
> so reuse the code. PGPICA1 contains type-C capable port slices
> which requires the well to power powered up, so add new power well
> definition for it.
>
> The DC_OFF fake power well will be added in a follow up commit.
>
> v2: Do not rmw as bit 31 is the only R/W bit in the regiser (Matt Roper)
>
> BSpec: 68886
> Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> .../i915/display/intel_display_power_map.c | 36 +++++++++++++++-
> .../i915/display/intel_display_power_well.c | 41 +++++++++++++++++++
> .../i915/display/intel_display_power_well.h | 1 +
> .../gpu/drm/i915/display/intel_dp_aux_regs.h | 5 +++
> 4 files changed, 82 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> index 0f1b93d139ca..31c11586ede5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> @@ -1536,6 +1536,38 @@ static const struct i915_power_well_desc_list xelpdp_power_wells[] = {
> I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
> };
>
> +I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_pica_tc,
> + POWER_DOMAIN_PORT_DDI_LANES_TC1,
> + POWER_DOMAIN_PORT_DDI_LANES_TC2,
> + POWER_DOMAIN_PORT_DDI_LANES_TC3,
> + POWER_DOMAIN_PORT_DDI_LANES_TC4,
> + POWER_DOMAIN_AUX_USBC1,
> + POWER_DOMAIN_AUX_USBC2,
> + POWER_DOMAIN_AUX_USBC3,
> + POWER_DOMAIN_AUX_USBC4,
> + POWER_DOMAIN_AUX_TBT1,
> + POWER_DOMAIN_AUX_TBT2,
> + POWER_DOMAIN_AUX_TBT3,
> + POWER_DOMAIN_AUX_TBT4,
> + POWER_DOMAIN_INIT);
> +
> +static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
> + {
> + .instances = &I915_PW_INSTANCES(I915_PW("PICA_TC",
> + &xe2lpd_pwdoms_pica_tc,
> + .id = DISP_PW_ID_NONE),
> + ),
> + .ops = &xe2lpd_pica_power_well_ops,
> + },
> +};
> +
> +static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
> + I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
> + I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
> + I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
> + I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
> +};
> +
> static void init_power_well_domains(const struct i915_power_well_instance *inst,
> struct i915_power_well *power_well)
> {
> @@ -1643,7 +1675,9 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
> return 0;
> }
>
> - if (DISPLAY_VER(i915) >= 14)
> + if (DISPLAY_VER(i915) >= 20)
> + return set_power_wells(power_domains, xe2lpd_power_wells);
> + else if (DISPLAY_VER(i915) >= 14)
> return set_power_wells(power_domains, xelpdp_power_wells);
> else if (IS_DG2(i915))
> return set_power_wells(power_domains, xehpd_power_wells);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index ca0714eba17a..07d650050099 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -1833,6 +1833,40 @@ static bool xelpdp_aux_power_well_enabled(struct drm_i915_private *dev_priv,
> XELPDP_DP_AUX_CH_CTL_POWER_STATUS;
> }
>
> +static void xe2lpd_pica_power_well_enable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + intel_de_write(dev_priv, XE2LPD_PICA_PW_CTL,
> + XE2LPD_PICA_CTL_POWER_REQUEST);
> +
> + if (intel_de_wait_for_set(dev_priv, XE2LPD_PICA_PW_CTL,
> + XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> + drm_dbg_kms(&dev_priv->drm, "pica power well enable timeout\n");
> +
> + drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when enabled");
> + }
> +}
> +
> +static void xe2lpd_pica_power_well_disable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + intel_de_write(dev_priv, XE2LPD_PICA_PW_CTL, 0);
> +
> + if (intel_de_wait_for_clear(dev_priv, XE2LPD_PICA_PW_CTL,
> + XE2LPD_PICA_CTL_POWER_STATUS, 1)) {
> + drm_dbg_kms(&dev_priv->drm, "pica power well disable timeout\n");
> +
> + drm_WARN(&dev_priv->drm, 1, "Power well PICA timeout when disabled");
> + }
> +}
> +
> +static bool xe2lpd_pica_power_well_enabled(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + return intel_de_read(dev_priv, XE2LPD_PICA_PW_CTL) &
> + XE2LPD_PICA_CTL_POWER_STATUS;
> +}
> +
> const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> .sync_hw = i9xx_power_well_sync_hw_noop,
> .enable = i9xx_always_on_power_well_noop,
> @@ -1952,3 +1986,10 @@ const struct i915_power_well_ops xelpdp_aux_power_well_ops = {
> .disable = xelpdp_aux_power_well_disable,
> .is_enabled = xelpdp_aux_power_well_enabled,
> };
> +
> +const struct i915_power_well_ops xe2lpd_pica_power_well_ops = {
> + .sync_hw = i9xx_power_well_sync_hw_noop,
> + .enable = xe2lpd_pica_power_well_enable,
> + .disable = xe2lpd_pica_power_well_disable,
> + .is_enabled = xe2lpd_pica_power_well_enabled,
> +};
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> index a8736588314d..9357a9a73c06 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> @@ -176,5 +176,6 @@ extern const struct i915_power_well_ops icl_aux_power_well_ops;
> extern const struct i915_power_well_ops icl_ddi_power_well_ops;
> extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
> extern const struct i915_power_well_ops xelpdp_aux_power_well_ops;
> +extern const struct i915_power_well_ops xe2lpd_pica_power_well_ops;
>
> #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> index 9d141e86a4b6..e8f426d5ce20 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp_aux_regs.h
> @@ -86,4 +86,9 @@
> _XELPDP_DP_AUX_CH_DATA(__xe2lpd_aux_ch_idx(aux_ch), i) : \
> _XELPDP_DP_AUX_CH_DATA(aux_ch, i))
>
> +/* PICA Power Well Control */
> +#define XE2LPD_PICA_PW_CTL _MMIO(0x16fe04)
> +#define XE2LPD_PICA_CTL_POWER_REQUEST REG_BIT(31)
> +#define XE2LPD_PICA_CTL_POWER_STATUS REG_BIT(30)
> +
> #endif /* __INTEL_DP_AUX_REGS_H__ */
> --
> 2.40.1
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 40+ messages in thread
* [Intel-gfx] [PATCH v4 25/30] drm/i915/xe2lpd: Add DC state support
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (23 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 24/30] drm/i915/xe2lpd: Add display power well Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 26/30] drm/i915/lnl: Start using CDCLK through PLL Lucas De Marchi
` (7 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Matt Roper, intel-xe
From: Matt Roper <matthew.d.roper@intel.com>
Xe2_LPD supports DC5, DC6, and DC9 (DC3CO no longer exists). The
overall programming and requirements to enter DC states are similar to
those of Xe_LPD+ although AUX transactions do not require DC5/DC6 exit
as they did previously.
Bspec: 68851, 68857, 68886, 69115
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
---
.../gpu/drm/i915/display/intel_display_power.c | 4 +++-
.../drm/i915/display/intel_display_power_map.c | 18 ++++++++++++++++++
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 68cf5e6b0b46..a0d90a613ab3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -943,7 +943,9 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
if (!HAS_DISPLAY(dev_priv))
return 0;
- if (IS_DG2(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 20)
+ max_dc = 2;
+ else if (IS_DG2(dev_priv))
max_dc = 1;
else if (IS_DG1(dev_priv))
max_dc = 3;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 31c11586ede5..10948b3964ee 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1561,9 +1561,27 @@ static const struct i915_power_well_desc xe2lpd_power_wells_pica[] = {
},
};
+I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_dc_off,
+ POWER_DOMAIN_DC_OFF,
+ XELPD_PW_C_POWER_DOMAINS,
+ XELPD_PW_D_POWER_DOMAINS,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_INIT);
+
+static const struct i915_power_well_desc xe2lpd_power_wells_dcoff[] = {
+ {
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DC_off", &xe2lpd_pwdoms_dc_off,
+ .id = SKL_DISP_DC_OFF),
+ ),
+ .ops = &gen9_dc_off_power_well_ops,
+ },
+};
+
static const struct i915_power_well_desc_list xe2lpd_power_wells[] = {
I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(xe2lpd_power_wells_dcoff),
I915_PW_DESCRIPTORS(xelpdp_power_wells_main),
I915_PW_DESCRIPTORS(xe2lpd_power_wells_pica),
};
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 26/30] drm/i915/lnl: Start using CDCLK through PLL
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (24 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 25/30] drm/i915/xe2lpd: Add DC state support Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 27/30] FIXME: drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf Lucas De Marchi
` (6 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Matt Roper, Lucas De Marchi, intel-xe
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Introduce correspondent definitions for choosing between CD2X CDCLK
and PLL CDCLK as a source. All the entries in cdclk table for xe2lpd are
defined with PLL CDCLK as source, so simply set it. Also
skl_cdclk_decimal() shouldn't be set in CDCLK_CTL anymore, so skip it
for display version 20 and above.
v2:
- Remove unneeded comment and use REG_BIT() (Matt Roper)
- Rename CDCLK_SOURCE_SEL_CDCLK_PLL() to MDCLK_SOURCE_SEL_CDCLK_PLL
to match spec (Lucas)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 9 +++++++--
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4cde78db83a1..b55a3f75f392 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1906,8 +1906,7 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
dg2_cdclk_squash_program(dev_priv, waveform);
val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
- bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
- skl_cdclk_decimal(cdclk);
+ bxt_cdclk_cd2x_pipe(dev_priv, pipe);
/*
* Disable SSA Precharge when CD clock frequency < 500 MHz,
@@ -1916,6 +1915,12 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
cdclk >= 500000)
val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
+
+ if (DISPLAY_VER(dev_priv) >= 20)
+ val |= MDCLK_SOURCE_SEL_CDCLK_PLL;
+ else
+ val |= skl_cdclk_decimal(cdclk);
+
intel_de_write(dev_priv, CDCLK_CTL, val);
if (pipe != INVALID_PIPE)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index efcf1461988f..c59eb411cf06 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5884,6 +5884,7 @@ enum skl_power_gate {
#define CDCLK_FREQ_540 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 1)
#define CDCLK_FREQ_337_308 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 2)
#define CDCLK_FREQ_675_617 REG_FIELD_PREP(CDCLK_FREQ_SEL_MASK, 3)
+#define MDCLK_SOURCE_SEL_CDCLK_PLL REG_BIT(25)
#define BXT_CDCLK_CD2X_DIV_SEL_MASK REG_GENMASK(23, 22)
#define BXT_CDCLK_CD2X_DIV_SEL_1 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 0)
#define BXT_CDCLK_CD2X_DIV_SEL_1_5 REG_FIELD_PREP(BXT_CDCLK_CD2X_DIV_SEL_MASK, 1)
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 27/30] FIXME: drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (25 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 26/30] drm/i915/lnl: Start using CDCLK through PLL Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 28/30] drm/i915/lnl: Add programming for CDCLK change Lucas De Marchi
` (5 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, intel-xe
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
When we change MDCLK/CDCLK the BSpec now instructs us to write a ratio
between MDCLK/CDCLK to MBUS CTL and DBUF CTL registers during that
change.
Previsouly DBuf state and CDCLK were not anyhow coupled together. Now
at compute stage when we know which CDCLK/MDCLK we are going to use, we
need to update the DBuf state with that ratio, being properly encoded,
so that it gets written to those registers, once DBuf state is being
update. The criteria for updating DBuf state is also a CDCLK/MDCLK ratio
change now.
v2:
- Remove condition check for display version 20 since it's compatible
with previous versions (Matt Roper)
- Squash the serialization of global state when mdclk_cdclk_ratio
changes
Bspec: 68864, 69482, 69445
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 28 +++++++++++++++++++
drivers/gpu/drm/i915/display/skl_watermark.c | 28 ++++++++++++++++---
drivers/gpu/drm/i915/display/skl_watermark.h | 1 +
.../gpu/drm/i915/display/skl_watermark_regs.h | 2 ++
4 files changed, 55 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index b55a3f75f392..e3db6c7934f3 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -39,6 +39,7 @@
#include "intel_pcode.h"
#include "intel_psr.h"
#include "intel_vdsc.h"
+#include "skl_watermark.h"
#include "vlv_sideband.h"
/**
@@ -1800,6 +1801,16 @@ static bool cdclk_pll_is_unknown(unsigned int vco)
return vco == ~0;
}
+/* Return the MBUS_CTL's encoding of the mdclk/cdclk ratio */
+static int get_mdclk_cdclk_ratio(struct drm_i915_private *i915,
+ const struct intel_cdclk_config *cdclk_config)
+{
+ if (DISPLAY_VER(i915) >= 20)
+ return DIV_ROUND_UP(cdclk_config->vco, cdclk_config->cdclk) - 1;
+
+ return 1;
+}
+
static int cdclk_squash_divider(u16 waveform)
{
return hweight16(waveform ?: 0xffff);
@@ -2712,6 +2723,8 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
struct intel_crtc_state *crtc_state;
int min_cdclk, i;
enum pipe pipe;
+ struct intel_dbuf_state *new_dbuf_state;
+ struct intel_dbuf_state *old_dbuf_state;
for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
int ret;
@@ -2745,6 +2758,21 @@ static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
}
}
+ new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
+ old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
+ if (new_dbuf_state && old_dbuf_state) {
+ new_dbuf_state->mdclk_cdclk_ratio =
+ get_mdclk_cdclk_ratio(dev_priv, &cdclk_state->actual);
+
+ if (new_dbuf_state->mdclk_cdclk_ratio != old_dbuf_state->mdclk_cdclk_ratio) {
+ int ret;
+
+ ret = intel_atomic_serialize_global_state(&new_dbuf_state->base);
+ if (ret)
+ return ret;
+ }
+ }
+
min_cdclk = max(cdclk_state->force_min_cdclk,
cdclk_state->bw_min_cdclk);
for_each_pipe(dev_priv, pipe)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 64a122d3c9c0..1fefb02876c8 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3472,6 +3472,16 @@ int intel_dbuf_init(struct drm_i915_private *i915)
return 0;
}
+static int get_mbus_mdclk_cdclk_ratio(struct drm_i915_private *i915,
+ int mdclk_cdclk_ratio,
+ int mbus_joined)
+{
+ if (mbus_joined)
+ return (mdclk_cdclk_ratio << 1) + 1;
+
+ return mdclk_cdclk_ratio;
+}
+
/*
* Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
* update the request state of all DBUS slices.
@@ -3483,10 +3493,16 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
enum dbuf_slice slice;
const struct intel_dbuf_state *dbuf_state =
intel_atomic_get_new_dbuf_state(state);
+ int tracker_state_service;
if (!HAS_MBUS_JOINING(i915))
return;
+ tracker_state_service =
+ get_mbus_mdclk_cdclk_ratio(i915,
+ dbuf_state->mdclk_cdclk_ratio,
+ dbuf_state->joined_mbus);
+
/*
* TODO: Implement vblank synchronized MBUS joining changes.
* Must be properly coordinated with dbuf reprogramming.
@@ -3494,13 +3510,15 @@ static void update_mbus_pre_enable(struct intel_atomic_state *state)
if (dbuf_state->joined_mbus) {
mbus_ctl = MBUS_HASHING_MODE_1x4 | MBUS_JOIN |
MBUS_JOIN_PIPE_SELECT_NONE;
- dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(3);
} else {
mbus_ctl = MBUS_HASHING_MODE_2x2 |
MBUS_JOIN_PIPE_SELECT_NONE;
- dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(1);
}
+ dbuf_min_tracker_val = DBUF_MIN_TRACKER_STATE_SERVICE(tracker_state_service);
+
+ mbus_ctl |= MBUS_TRANS_THROTTLE_MIN_SELECT(dbuf_state->mdclk_cdclk_ratio);
+
intel_de_rmw(i915, MBUS_CTL,
MBUS_HASHING_MODE_MASK | MBUS_JOIN |
MBUS_JOIN_PIPE_SELECT_MASK, mbus_ctl);
@@ -3521,7 +3539,8 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
if (!new_dbuf_state ||
(new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
- new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
+ new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
+ new_dbuf_state->mdclk_cdclk_ratio == old_dbuf_state->mdclk_cdclk_ratio))
return;
WARN_ON(!new_dbuf_state->base.changed);
@@ -3542,7 +3561,8 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
if (!new_dbuf_state ||
(new_dbuf_state->enabled_slices == old_dbuf_state->enabled_slices &&
- new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus))
+ new_dbuf_state->joined_mbus == old_dbuf_state->joined_mbus &&
+ new_dbuf_state->mdclk_cdclk_ratio == old_dbuf_state->mdclk_cdclk_ratio))
return;
WARN_ON(!new_dbuf_state->base.changed);
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index f91a3d4ddc07..54db5c7d517e 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -56,6 +56,7 @@ struct intel_dbuf_state {
u8 slices[I915_MAX_PIPES];
u8 enabled_slices;
u8 active_pipes;
+ u8 mdclk_cdclk_ratio;
bool joined_mbus;
};
diff --git a/drivers/gpu/drm/i915/display/skl_watermark_regs.h b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
index 628c5920ad49..4c820f1d351d 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark_regs.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark_regs.h
@@ -38,6 +38,8 @@
#define MBUS_HASHING_MODE_2x2 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 0)
#define MBUS_HASHING_MODE_1x4 REG_FIELD_PREP(MBUS_HASHING_MODE_MASK, 1)
#define MBUS_JOIN_PIPE_SELECT_MASK REG_GENMASK(28, 26)
+#define MBUS_TRANS_THROTTLE_MIN_MASK REG_GENMASK(15, 13)
+#define MBUS_TRANS_THROTTLE_MIN_SELECT(ratio) REG_FIELD_PREP(MBUS_TRANS_THROTTLE_MIN_MASK, ratio)
#define MBUS_JOIN_PIPE_SELECT(pipe) REG_FIELD_PREP(MBUS_JOIN_PIPE_SELECT_MASK, pipe)
#define MBUS_JOIN_PIPE_SELECT_NONE MBUS_JOIN_PIPE_SELECT(7)
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 28/30] drm/i915/lnl: Add programming for CDCLK change
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (26 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 27/30] FIXME: drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 29/30] drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane Lucas De Marchi
` (4 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Matt Roper, Lucas De Marchi, intel-xe
From: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Add programming sequence for changes on CDCLK for Lunar Lake
platforms. It's mostly the same as MTL, but with some
additional programming for the squash and crawling steps when
a change in mdclk/cdclk ratio is observed.
v2: Remove wrong changes for bxt_cdclk_cd2x_pipe() (Matt Roper)
v3: Reword commit message and flatten if/else ladder (Matt Roper)
BSpec: 68864
Signed-off-by: Ravi Kumar Vodapalli <ravi.kumar.vodapalli@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
---
drivers/gpu/drm/i915/display/intel_cdclk.c | 46 +++++++++++++++++++++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index e3db6c7934f3..1da1995fb3a7 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -40,6 +40,7 @@
#include "intel_psr.h"
#include "intel_vdsc.h"
#include "skl_watermark.h"
+#include "skl_watermark_regs.h"
#include "vlv_sideband.h"
/**
@@ -1811,6 +1812,47 @@ static int get_mdclk_cdclk_ratio(struct drm_i915_private *i915,
return 1;
}
+static void lnl_prog_mbus_dbuf_ctrl(struct drm_i915_private *i915,
+ const struct intel_cdclk_config *cdclk_config)
+{
+ int min_throttle_val;
+ int min_tracker_state;
+ enum dbuf_slice slice;
+ int mdclk_cdclk_div_ratio;
+ int mbus_join = intel_de_read(i915, MBUS_CTL) & MBUS_JOIN;
+
+ mdclk_cdclk_div_ratio = get_mdclk_cdclk_ratio(i915, cdclk_config);
+
+ min_throttle_val = MBUS_TRANS_THROTTLE_MIN_SELECT(mdclk_cdclk_div_ratio);
+
+ intel_de_rmw(i915, MBUS_CTL, MBUS_TRANS_THROTTLE_MIN_MASK, min_throttle_val);
+
+ if (mbus_join)
+ mdclk_cdclk_div_ratio = (mdclk_cdclk_div_ratio << 1) + 1;
+
+ min_tracker_state = DBUF_MIN_TRACKER_STATE_SERVICE(mdclk_cdclk_div_ratio);
+
+ for_each_dbuf_slice(i915, slice)
+ intel_de_rmw(i915, DBUF_CTL_S(slice),
+ DBUF_MIN_TRACKER_STATE_SERVICE_MASK,
+ min_tracker_state);
+}
+
+static void lnl_cdclk_squash_program(struct drm_i915_private *i915,
+ const struct intel_cdclk_config *cdclk_config,
+ u16 waveform)
+{
+ if (cdclk_config->cdclk < i915->display.cdclk.hw.cdclk)
+ /* Program mbus_ctrl and dbuf_ctrl registers as Pre hook */
+ lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config);
+
+ dg2_cdclk_squash_program(i915, waveform);
+
+ if (cdclk_config->cdclk > i915->display.cdclk.hw.cdclk)
+ /* Program mbus_ctrl and dbuf_ctrl registers as Post hook */
+ lnl_prog_mbus_dbuf_ctrl(i915, cdclk_config);
+}
+
static int cdclk_squash_divider(u16 waveform)
{
return hweight16(waveform ?: 0xffff);
@@ -1913,7 +1955,9 @@ static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
else
clock = cdclk;
- if (HAS_CDCLK_SQUASH(dev_priv))
+ if (DISPLAY_VER(dev_priv) >= 20)
+ lnl_cdclk_squash_program(dev_priv, cdclk_config, waveform);
+ else if (HAS_CDCLK_SQUASH(dev_priv))
dg2_cdclk_squash_program(dev_priv, waveform);
val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 29/30] drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (27 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 28/30] drm/i915/lnl: Add programming for CDCLK change Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 30/30] drm/i915/xe2lpd: Update mbus on post plane updates Lucas De Marchi
` (3 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, intel-xe
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Previously we always updated DBuf MBUS CTL and DBUF CTL regs after
CDCLK has been changed(CDCLK_CTL), however for Xe2-LPD we can't do like
that anymore. According to BSpec, we have to first update DBuf regs and
then write CDCLK regs, when CDCLK is decreased, which we do in post
plane.
So now we do CDCLK post plane update only after DBuf regs are
written (CDCLK/MDCLK separation requires MDCLK/CDCLK ratio to be written
to DBuf regs).
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 6bbc9069754c..84c09958cca7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -7040,7 +7040,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
dev_priv->display.funcs.display->commit_modeset_enables(state);
- if (state->modeset)
+ if (state->modeset && DISPLAY_VER(dev_priv) < 20)
intel_set_cdclk_post_plane_update(state);
intel_wait_for_vblank_workers(state);
@@ -7087,6 +7087,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_dbuf_post_plane_update(state);
intel_psr_post_plane_update(state);
+ if (state->modeset && DISPLAY_VER(dev_priv) >= 20)
+ intel_set_cdclk_post_plane_update(state);
+
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
intel_post_plane_update(state, crtc);
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] [PATCH v4 30/30] drm/i915/xe2lpd: Update mbus on post plane updates
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (28 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 29/30] drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane Lucas De Marchi
@ 2023-09-15 17:46 ` Lucas De Marchi
2023-09-16 2:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable Lunar Lake display (rev5) Patchwork
` (2 subsequent siblings)
32 siblings, 0 replies; 40+ messages in thread
From: Lucas De Marchi @ 2023-09-15 17:46 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, intel-xe
From: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
According to BSpec we need to write the MBUS CTL and DBUF CTL both for
increasing CDCLK case (pre plane) and for decreasing CDCLK case (post
plane). Make sure those updates are in place for Xe2-LPD.
Since the mbus update is not only on pre-enable anymore, also rename the
function accordingly.
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
---
drivers/gpu/drm/i915/display/skl_watermark.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 1fefb02876c8..955a8fb7ba19 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3486,7 +3486,7 @@ static int get_mbus_mdclk_cdclk_ratio(struct drm_i915_private *i915,
* Configure MBUS_CTL and all DBUF_CTL_S of each slice to join_mbus state before
* update the request state of all DBUS slices.
*/
-static void update_mbus_pre_enable(struct intel_atomic_state *state)
+static void update_mbus(struct intel_atomic_state *state)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
u32 mbus_ctl, dbuf_min_tracker_val;
@@ -3545,7 +3545,7 @@ void intel_dbuf_pre_plane_update(struct intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
- update_mbus_pre_enable(state);
+ update_mbus(state);
gen9_dbuf_slices_update(i915,
old_dbuf_state->enabled_slices |
new_dbuf_state->enabled_slices);
@@ -3567,6 +3567,9 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
WARN_ON(!new_dbuf_state->base.changed);
+ if (DISPLAY_VER(i915) >= 20)
+ update_mbus(state);
+
gen9_dbuf_slices_update(i915,
new_dbuf_state->enabled_slices);
}
--
2.40.1
^ permalink raw reply related [flat|nested] 40+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable Lunar Lake display (rev5)
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (29 preceding siblings ...)
2023-09-15 17:46 ` [Intel-gfx] [PATCH v4 30/30] drm/i915/xe2lpd: Update mbus on post plane updates Lucas De Marchi
@ 2023-09-16 2:02 ` Patchwork
2023-09-16 2:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-09-16 2:12 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
32 siblings, 0 replies; 40+ messages in thread
From: Patchwork @ 2023-09-16 2:02 UTC (permalink / raw)
To: Vodapalli, Ravi Kumar; +Cc: intel-gfx
== Series Details ==
Series: Enable Lunar Lake display (rev5)
URL : https://patchwork.freedesktop.org/series/122799/
State : warning
== Summary ==
Error: dim checkpatch failed
0891930bfe21 drm/i915/xelpdp: Add XE_LPDP_FEATURES
d93689afdf8e drm/i915/lnl: Add display definitions
6d075298baed drm/i915/xe2lpd: FBC is now supported on all pipes
fdee581d06f6 drm/i915/display: Remove FBC capability from fused off pipes
1f82a263a25e drm/i915: Re-order if/else ladder in intel_detect_pch()
20e9e98d46a2 drm/i915/xe2lpd: Add fake PCH
1352ae2e0a16 drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation
7f1a28491e59 drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST
eec97f48248a drm/i915/xe2lpd: Register DE_RRMR has been removed
3831119242c0 drm/i915/display: Consolidate saved port bits in intel_digital_port
55a3d0feb769 drm/i915/display: Rename intel_dp->DP
7a476f615a06 drm/i915/xe2lpd: Move D2D enable/disable
df8a8816e56b drm/i915/xe2lpd: Move registers to PICA
-:376: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects?
#376: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:27:
+#define __xe2lpd_port_idx(port) \
+ (port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A)
-:376: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'port' may be better as '(port)' to avoid precedence issues
#376: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:27:
+#define __xe2lpd_port_idx(port) \
+ (port >= PORT_TC1 ? port : PORT_TC4 + 1 + port - PORT_A)
-:389: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects?
#389: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:39:
+#define XELPDP_PORT_M2P_MSGBUS_CTL(i915__, port, lane) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_M2P_MSGBUS_CTL(__xe2lpd_port_idx(port), lane) : \
+ _XELPDP_PORT_M2P_MSGBUS_CTL(port, lane))
-:389: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'lane' - possible side-effects?
#389: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:39:
+#define XELPDP_PORT_M2P_MSGBUS_CTL(i915__, port, lane) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_M2P_MSGBUS_CTL(__xe2lpd_port_idx(port), lane) : \
+ _XELPDP_PORT_M2P_MSGBUS_CTL(port, lane))
-:407: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects?
#407: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:59:
+#define XELPDP_PORT_P2M_MSGBUS_STATUS(i915__, port, lane) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_P2M_MSGBUS_STATUS(__xe2lpd_port_idx(port), lane) : \
+ _XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane))
-:407: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'lane' - possible side-effects?
#407: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:59:
+#define XELPDP_PORT_P2M_MSGBUS_STATUS(i915__, port, lane) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_P2M_MSGBUS_STATUS(__xe2lpd_port_idx(port), lane) : \
+ _XELPDP_PORT_P2M_MSGBUS_STATUS(port, lane))
-:424: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects?
#424: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:90:
+#define XELPDP_PORT_BUF_CTL1(i915__, port) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_BUF_CTL1(__xe2lpd_port_idx(port)) : \
+ _XELPDP_PORT_BUF_CTL1(port))
-:442: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects?
#442: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:115:
+#define XELPDP_PORT_BUF_CTL2(i915__, port) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_BUF_CTL2(__xe2lpd_port_idx(port)) : \
+ _XELPDP_PORT_BUF_CTL2(port))
-:459: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects?
#459: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:138:
+#define XELPDP_PORT_BUF_CTL3(i915__, port) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_BUF_CTL3(__xe2lpd_port_idx(port)) : \
+ _XELPDP_PORT_BUF_CTL3(port))
-:476: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects?
#476: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:161:
+#define XELPDP_PORT_MSGBUS_TIMER(i915__, port, lane) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_MSGBUS_TIMER(__xe2lpd_port_idx(port), lane) : \
+ _XELPDP_PORT_MSGBUS_TIMER(port, lane))
-:476: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'lane' - possible side-effects?
#476: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:161:
+#define XELPDP_PORT_MSGBUS_TIMER(i915__, port, lane) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_MSGBUS_TIMER(__xe2lpd_port_idx(port), lane) : \
+ _XELPDP_PORT_MSGBUS_TIMER(port, lane))
-:493: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'port' - possible side-effects?
#493: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h:178:
+#define XELPDP_PORT_CLOCK_CTL(i915__, port) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_PORT_CLOCK_CTL(__xe2lpd_port_idx(port)) : \
+ _XELPDP_PORT_CLOCK_CTL(port))
total: 0 errors, 0 warnings, 12 checks, 567 lines checked
8427bcfd869f drm/i915/display: Fix style and conventions for DP AUX regs
6a2765513861 drm/i915/display: Use _PICK_EVEN_2RANGES() in DP AUX regs
eec8fd50770c drm/i915/xe2lpd: Re-order DP AUX regs
-:88: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'aux_ch' - possible side-effects?
#88: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_regs.h:21:
+#define __xe2lpd_aux_ch_idx(aux_ch) \
+ (aux_ch >= AUX_CH_USBC1 ? aux_ch : AUX_CH_USBC4 + 1 + aux_ch - AUX_CH_A)
-:88: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'aux_ch' may be better as '(aux_ch)' to avoid precedence issues
#88: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_regs.h:21:
+#define __xe2lpd_aux_ch_idx(aux_ch) \
+ (aux_ch >= AUX_CH_USBC1 ? aux_ch : AUX_CH_USBC4 + 1 + aux_ch - AUX_CH_A)
-:104: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'aux_ch' - possible side-effects?
#104: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_regs.h:36:
+#define XELPDP_DP_AUX_CH_CTL(i915__, aux_ch) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_DP_AUX_CH_CTL(__xe2lpd_aux_ch_idx(aux_ch)) : \
+ _XELPDP_DP_AUX_CH_CTL(aux_ch))
-:121: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'aux_ch' - possible side-effects?
#121: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_regs.h:84:
+#define XELPDP_DP_AUX_CH_DATA(i915__, aux_ch, i) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_DP_AUX_CH_DATA(__xe2lpd_aux_ch_idx(aux_ch), i) : \
+ _XELPDP_DP_AUX_CH_DATA(aux_ch, i))
-:121: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'i' - possible side-effects?
#121: FILE: drivers/gpu/drm/i915/display/intel_dp_aux_regs.h:84:
+#define XELPDP_DP_AUX_CH_DATA(i915__, aux_ch, i) \
+ (DISPLAY_VER(i915__) >= 20 ? \
+ _XELPDP_DP_AUX_CH_DATA(__xe2lpd_aux_ch_idx(aux_ch), i) : \
+ _XELPDP_DP_AUX_CH_DATA(aux_ch, i))
total: 0 errors, 0 warnings, 5 checks, 92 lines checked
0ee28455fb3f drm/i915/xe2lpd: Handle port AUX interrupts
de623d8a98d3 drm/i915/xe2lpd: Read pin assignment from IOM
51bdaa105e1c drm/i915/xe2lpd: Enable odd size and panning for planar yuv
26ee6dadc71f drm/i915/xe2lpd: Add support for HPD
72adf8cdd458 drm/i915/xe2lpd: Extend Wa_15010685871
ee44ad47e087 drm/i915/lnl: Add gmbus/ddc support
41758537262c drm/i915/lnl: Add CDCLK table
c84dc1ea268c drm/i915/xe2lpd: Add display power well
-:13: WARNING:TYPO_SPELLING: 'regiser' may be misspelled - perhaps 'register'?
#13:
v2: Do not rmw as bit 31 is the only R/W bit in the regiser (Matt Roper)
^^^^^^^
total: 0 errors, 1 warnings, 0 checks, 113 lines checked
c153e28fb6e6 drm/i915/xe2lpd: Add DC state support
-:41: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#41: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1565:
+I915_DECL_PW_DOMAINS(xe2lpd_pwdoms_dc_off,
+ POWER_DOMAIN_DC_OFF,
-:49: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#49: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1573:
+ .instances = &I915_PW_INSTANCES(
total: 0 errors, 0 warnings, 2 checks, 37 lines checked
c9db14bccb31 drm/i915/lnl: Start using CDCLK through PLL
f8632a3622fb FIXME: drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf
ed5321ba9ec1 drm/i915/lnl: Add programming for CDCLK change
b433a890aa15 drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane
5379effd3df5 drm/i915/xe2lpd: Update mbus on post plane updates
^ permalink raw reply [flat|nested] 40+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable Lunar Lake display (rev5)
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (30 preceding siblings ...)
2023-09-16 2:02 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable Lunar Lake display (rev5) Patchwork
@ 2023-09-16 2:02 ` Patchwork
2023-09-16 2:12 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
32 siblings, 0 replies; 40+ messages in thread
From: Patchwork @ 2023-09-16 2:02 UTC (permalink / raw)
To: Vodapalli, Ravi Kumar; +Cc: intel-gfx
== Series Details ==
Series: Enable Lunar Lake display (rev5)
URL : https://patchwork.freedesktop.org/series/122799/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 40+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for Enable Lunar Lake display (rev5)
2023-09-15 17:46 [Intel-gfx] [PATCH v4 00/30] Enable Lunar Lake display Lucas De Marchi
` (31 preceding siblings ...)
2023-09-16 2:02 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-09-16 2:12 ` Patchwork
32 siblings, 0 replies; 40+ messages in thread
From: Patchwork @ 2023-09-16 2:12 UTC (permalink / raw)
To: Vodapalli, Ravi Kumar; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4113 bytes --]
== Series Details ==
Series: Enable Lunar Lake display (rev5)
URL : https://patchwork.freedesktop.org/series/122799/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13643 -> Patchwork_122799v5
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_122799v5 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_122799v5, please notify your bug team (lgci.bug.filing@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122799v5/index.html
Participating hosts (40 -> 17)
------------------------------
ERROR: It appears as if the changes made in Patchwork_122799v5 prevented too many machines from booting.
Missing (23): fi-rkl-11600 bat-adls-5 fi-snb-2520m bat-rpls-1 fi-blb-e6850 fi-skl-6600u fi-bsw-n3050 bat-dg2-9 fi-ilk-650 bat-adln-1 fi-elk-e7500 bat-jsl-3 bat-rplp-1 fi-bsw-nick fi-kbl-7567u bat-kbl-2 fi-cfl-8700k bat-mtlp-8 bat-jsl-1 fi-cfl-guc fi-cfl-8109u fi-kbl-8809g bat-dg2-13
Known issues
------------
Here are the changes found in Patchwork_122799v5 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [FAIL][1] ([IGT#3] / [i915#6121]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13643/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122799v5/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
[IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
[i915#6121]: https://gitlab.freedesktop.org/drm/intel/issues/6121
Build changes
-------------
* Linux: CI_DRM_13643 -> Patchwork_122799v5
CI-20190529: 20190529
CI_DRM_13643: dc4cd6e4e53d46211952fe7c0e408fce3e212993 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7490: 7490
Patchwork_122799v5: dc4cd6e4e53d46211952fe7c0e408fce3e212993 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
a1512e4ab38f drm/i915/xe2lpd: Update mbus on post plane updates
95ba176137a8 drm/i915/xe2lpd: Write DBuf after CDCLK change in post plane
54a8c4429dc1 drm/i915/lnl: Add programming for CDCLK change
1cfd746b85c0 FIXME: drm/i915/lnl: Introduce MDCLK_CDCLK ratio to DBuf
e6bd643715fe drm/i915/lnl: Start using CDCLK through PLL
a88713fc7026 drm/i915/xe2lpd: Add DC state support
a3a743041183 drm/i915/xe2lpd: Add display power well
1f29022f5ef5 drm/i915/lnl: Add CDCLK table
e2fea73b6edb drm/i915/lnl: Add gmbus/ddc support
1a899a446698 drm/i915/xe2lpd: Extend Wa_15010685871
4021c2133859 drm/i915/xe2lpd: Add support for HPD
d9ffb2884399 drm/i915/xe2lpd: Enable odd size and panning for planar yuv
fdd0866ff54f drm/i915/xe2lpd: Read pin assignment from IOM
5360a0f73e66 drm/i915/xe2lpd: Handle port AUX interrupts
8e5fd7b94294 drm/i915/xe2lpd: Re-order DP AUX regs
7ac85cc7520c drm/i915/display: Use _PICK_EVEN_2RANGES() in DP AUX regs
5d11d03ecd91 drm/i915/display: Fix style and conventions for DP AUX regs
fbae14705d90 drm/i915/xe2lpd: Move registers to PICA
d6d6cf7c943e drm/i915/xe2lpd: Move D2D enable/disable
c2bc5e1b4ef3 drm/i915/display: Rename intel_dp->DP
708d470949be drm/i915/display: Consolidate saved port bits in intel_digital_port
43af5bbfa30f drm/i915/xe2lpd: Register DE_RRMR has been removed
a5ec9d7afd0c drm/i915/xe2lpd: Don't try to program PLANE_AUX_DIST
dfff011c0855 drm/i915/xe2lpd: Treat cursor plane as regular plane for DDB allocation
e9cede014192 drm/i915/xe2lpd: Add fake PCH
118eb67567aa drm/i915: Re-order if/else ladder in intel_detect_pch()
c76243995f84 drm/i915/display: Remove FBC capability from fused off pipes
1d52bd792e86 drm/i915/xe2lpd: FBC is now supported on all pipes
e6eaf321ef77 drm/i915/lnl: Add display definitions
3b72b290abf4 drm/i915/xelpdp: Add XE_LPDP_FEATURES
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122799v5/index.html
[-- Attachment #2: Type: text/html, Size: 4910 bytes --]
^ permalink raw reply [flat|nested] 40+ messages in thread