* [Intel-gfx] [PATCH 1/3] drm/i915/gt: Move wal_get_fw_for_rmw()
@ 2023-06-22 18:27 Lucas De Marchi
2023-06-22 18:27 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: Fix context workarounds with non-masked regs Lucas De Marchi
` (4 more replies)
0 siblings, 5 replies; 12+ messages in thread
From: Lucas De Marchi @ 2023-06-22 18:27 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Kenneth Graunke, Matt Roper, stable, dri-devel
Move helper function to get all the forcewakes required by the wa list
to the top, so it can be re-used by other functions.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 32 ++++++++++-----------
1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 4d2dece96011..0578fc2c9e60 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -123,6 +123,22 @@ static void wa_init_finish(struct i915_wa_list *wal)
wal->wa_count, wal->name, wal->engine_name);
}
+static enum forcewake_domains
+wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal)
+{
+ enum forcewake_domains fw = 0;
+ struct i915_wa *wa;
+ unsigned int i;
+
+ for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
+ fw |= intel_uncore_forcewake_for_reg(uncore,
+ wa->reg,
+ FW_REG_READ |
+ FW_REG_WRITE);
+
+ return fw;
+}
+
static void _wa_add(struct i915_wa_list *wal, const struct i915_wa *wa)
{
unsigned int addr = i915_mmio_reg_offset(wa->reg);
@@ -1850,22 +1866,6 @@ void intel_gt_init_workarounds(struct intel_gt *gt)
wa_init_finish(wal);
}
-static enum forcewake_domains
-wal_get_fw_for_rmw(struct intel_uncore *uncore, const struct i915_wa_list *wal)
-{
- enum forcewake_domains fw = 0;
- struct i915_wa *wa;
- unsigned int i;
-
- for (i = 0, wa = wal->list; i < wal->count; i++, wa++)
- fw |= intel_uncore_forcewake_for_reg(uncore,
- wa->reg,
- FW_REG_READ |
- FW_REG_WRITE);
-
- return fw;
-}
-
static bool
wa_verify(struct intel_gt *gt, const struct i915_wa *wa, u32 cur,
const char *name, const char *from)
--
2.40.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 2/3] drm/i915/gt: Fix context workarounds with non-masked regs
2023-06-22 18:27 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Move wal_get_fw_for_rmw() Lucas De Marchi
@ 2023-06-22 18:27 ` Lucas De Marchi
2023-06-22 23:37 ` Kenneth Graunke
2023-06-22 18:27 ` [Intel-gfx] [PATCH 3/3] drm/i915/gt: Drop read from GEN8_L3CNTLREG in ICL workaround Lucas De Marchi
` (3 subsequent siblings)
4 siblings, 1 reply; 12+ messages in thread
From: Lucas De Marchi @ 2023-06-22 18:27 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Kenneth Graunke, Matt Roper, stable, dri-devel
Most of the context workarounds tweak masked registers, but not all. For
masked registers, when writing the value it's sufficient to just write
the wa->set_bits since that will take care of both the clr and set bits
as well as not overwriting other bits.
However there are some workarounds, the registers are non-masked. Up
until now the driver was simply emitting a MI_LOAD_REGISTER_IMM with the
set_bits to program the register via the GPU in the WA bb. This has the
side effect of overwriting the content of the register outside of bits
that should be set and also doesn't handle the bits that should be
cleared.
Kenneth reported that on DG2, mesa was seeing a weird behavior due to
the kernel programming of L3SQCREG5 in dg2_ctx_gt_tuning_init(). With
the GPU idle, that register could be read via intel_reg as 0x00e001ff,
but during a 3D workload it would change to 0x0000007f. So the
programming of that tuning was affecting more than the bits in
L3_PWM_TIMER_INIT_VAL_MASK. Matt Roper noticed the lack of rmw for the
context workarounds due to the use of MI_LOAD_REGISTER_IMM.
So, for registers that are not masked, read its value via mmio, modify
and then set it in the buffer to be written by the GPU. This should take
care in a simple way of programming just the bits required by the
tuning/workaround. If in future there are registers that involved that
can't be read by the CPU, a more complex approach may be required like
a) issuing additional instructions to read and modify; or b) scan the
golden context and patch it in place before saving it; or something
else. But for now this should suffice.
Scanning the context workarounds for all platforms, these are the
impacted ones with the respective registers
mtl: DRAW_WATERMARK
mtl/dg2: XEHP_L3SQCREG5, XEHP_FF_MODE2
gen12: GEN12_FF_MODE2
ICL has some non-masked registers in the context workarounds:
GEN8_L3CNTLREG, IVB_FBC_RT_BASE and VB_FBC_RT_BASE_UPPER, but there
shouldn't be an impact. The first is already being manually read and the
other 2 are intentionally overwriting the entire register.
Cc: Kenneth Graunke <kenneth@whitecape.org>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: stable@vger.kernel.org # v5.7+
Link: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23783#note_1968971
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 27 ++++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 0578fc2c9e60..a013f245a790 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1003,6 +1003,9 @@ void intel_engine_init_ctx_wa(struct intel_engine_cs *engine)
int intel_engine_emit_ctx_wa(struct i915_request *rq)
{
struct i915_wa_list *wal = &rq->engine->ctx_wa_list;
+ struct intel_uncore *uncore = rq->engine->uncore;
+ enum forcewake_domains fw;
+ unsigned long flags;
struct i915_wa *wa;
unsigned int i;
u32 *cs;
@@ -1019,13 +1022,35 @@ int intel_engine_emit_ctx_wa(struct i915_request *rq)
if (IS_ERR(cs))
return PTR_ERR(cs);
+ fw = wal_get_fw_for_rmw(uncore, wal);
+
+ intel_gt_mcr_lock(wal->gt, &flags);
+ spin_lock(&uncore->lock);
+ intel_uncore_forcewake_get__locked(uncore, fw);
+
*cs++ = MI_LOAD_REGISTER_IMM(wal->count);
for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
+ u32 val;
+
+ if (wa->masked_reg || wa->set == U32_MAX) {
+ val = wa->set;
+ } else {
+ val = wa->is_mcr ?
+ intel_gt_mcr_read_any_fw(wal->gt, wa->mcr_reg) :
+ intel_uncore_read_fw(uncore, wa->reg);
+ val &= ~wa->clr;
+ val |= wa->set;
+ }
+
*cs++ = i915_mmio_reg_offset(wa->reg);
- *cs++ = wa->set;
+ *cs++ = val;
}
*cs++ = MI_NOOP;
+ intel_uncore_forcewake_put__locked(uncore, fw);
+ spin_unlock(&uncore->lock);
+ intel_gt_mcr_unlock(wal->gt, flags);
+
intel_ring_advance(rq, cs);
ret = rq->engine->emit_flush(rq, EMIT_BARRIER);
--
2.40.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 3/3] drm/i915/gt: Drop read from GEN8_L3CNTLREG in ICL workaround
2023-06-22 18:27 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Move wal_get_fw_for_rmw() Lucas De Marchi
2023-06-22 18:27 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: Fix context workarounds with non-masked regs Lucas De Marchi
@ 2023-06-22 18:27 ` Lucas De Marchi
2023-06-22 19:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gt: Move wal_get_fw_for_rmw() Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 12+ messages in thread
From: Lucas De Marchi @ 2023-06-22 18:27 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Kenneth Graunke, Matt Roper, stable, dri-devel
Now that non-masked registers are already read before programming the
context reads, the additional read became redudant, so remove it.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a013f245a790..7d90fb376e8e 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -637,10 +637,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
/* Wa_1406697149 (WaDisableBankHangMode:icl) */
- wa_write(wal,
- GEN8_L3CNTLREG,
- intel_uncore_read(engine->uncore, GEN8_L3CNTLREG) |
- GEN8_ERRDETBCTRL);
+ wa_write(wal, GEN8_L3CNTLREG, GEN8_ERRDETBCTRL);
/* WaForceEnableNonCoherent:icl
* This is not the same workaround as in early Gen9 platforms, where
--
2.40.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gt: Move wal_get_fw_for_rmw()
2023-06-22 18:27 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Move wal_get_fw_for_rmw() Lucas De Marchi
2023-06-22 18:27 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: Fix context workarounds with non-masked regs Lucas De Marchi
2023-06-22 18:27 ` [Intel-gfx] [PATCH 3/3] drm/i915/gt: Drop read from GEN8_L3CNTLREG in ICL workaround Lucas De Marchi
@ 2023-06-22 19:12 ` Patchwork
2023-06-22 23:37 ` [Intel-gfx] [PATCH 1/3] " Kenneth Graunke
2023-06-23 9:11 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] " Patchwork
4 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2023-06-22 19:12 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 5661 bytes --]
== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Move wal_get_fw_for_rmw()
URL : https://patchwork.freedesktop.org/series/119766/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13309 -> Patchwork_119766v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/index.html
Participating hosts (43 -> 42)
------------------------------
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_119766v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_backlight@basic-brightness@edp-1:
- bat-rplp-1: NOTRUN -> [ABORT][1] ([i915#7077])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/bat-rplp-1/igt@i915_pm_backlight@basic-brightness@edp-1.html
* igt@i915_selftest@live@execlists:
- fi-bsw-nick: [PASS][2] -> [ABORT][3] ([i915#7911] / [i915#7913])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/fi-bsw-nick/igt@i915_selftest@live@execlists.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/fi-bsw-nick/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@migrate:
- bat-mtlp-6: [PASS][4] -> [DMESG-FAIL][5] ([i915#7699])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/bat-mtlp-6/igt@i915_selftest@live@migrate.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/bat-mtlp-6/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@requests:
- bat-rpls-1: [PASS][6] -> [ABORT][7] ([i915#4983] / [i915#7911] / [i915#7920])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/bat-rpls-1/igt@i915_selftest@live@requests.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/bat-rpls-1/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@workarounds:
- bat-rpls-2: [PASS][8] -> [DMESG-FAIL][9] ([i915#7102] / [i915#7913])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/bat-rpls-2/igt@i915_selftest@live@workarounds.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/bat-rpls-2/igt@i915_selftest@live@workarounds.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-dg2-11: NOTRUN -> [SKIP][10] ([i915#7828])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/bat-dg2-11/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
#### Possible fixes ####
* igt@i915_selftest@live@gt_mocs:
- bat-mtlp-6: [DMESG-FAIL][11] ([i915#7059]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html
* igt@i915_selftest@live@requests:
- bat-dg2-11: [ABORT][13] ([i915#7913]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/bat-dg2-11/igt@i915_selftest@live@requests.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/bat-dg2-11/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@workarounds:
- bat-mtlp-6: [DMESG-FAIL][15] ([i915#6763]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/bat-mtlp-6/igt@i915_selftest@live@workarounds.html
#### Warnings ####
* igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: [ABORT][17] ([i915#4579] / [i915#8260]) -> [SKIP][18] ([i915#3555] / [i915#4579])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/bat-rplp-1/igt@kms_setmode@basic-clone-single-crtc.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/bat-rplp-1/igt@kms_setmode@basic-clone-single-crtc.html
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#6763]: https://gitlab.freedesktop.org/drm/intel/issues/6763
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7077]: https://gitlab.freedesktop.org/drm/intel/issues/7077
[i915#7102]: https://gitlab.freedesktop.org/drm/intel/issues/7102
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7911]: https://gitlab.freedesktop.org/drm/intel/issues/7911
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7920]: https://gitlab.freedesktop.org/drm/intel/issues/7920
[i915#8260]: https://gitlab.freedesktop.org/drm/intel/issues/8260
Build changes
-------------
* Linux: CI_DRM_13309 -> Patchwork_119766v1
CI-20190529: 20190529
CI_DRM_13309: af67b02abf56a5018cd885c94d7611241052e98f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7346: 29302a0d57bcf10cb553f5d7ff5bb99166a19bba @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_119766v1: af67b02abf56a5018cd885c94d7611241052e98f @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
2aa1195e7eaf drm/i915/gt: Drop read from GEN8_L3CNTLREG in ICL workaround
4fec2482aa5f drm/i915/gt: Fix context workarounds with non-masked regs
8bf665038d5c drm/i915/gt: Move wal_get_fw_for_rmw()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/index.html
[-- Attachment #2: Type: text/html, Size: 6772 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Fix context workarounds with non-masked regs
2023-06-22 18:27 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: Fix context workarounds with non-masked regs Lucas De Marchi
@ 2023-06-22 23:37 ` Kenneth Graunke
2023-06-23 15:49 ` Lucas De Marchi
0 siblings, 1 reply; 12+ messages in thread
From: Kenneth Graunke @ 2023-06-22 23:37 UTC (permalink / raw)
To: intel-gfx, Lucas De Marchi; +Cc: Lucas De Marchi, Matt Roper, stable, dri-devel
[-- Attachment #1: Type: text/plain, Size: 2811 bytes --]
On Thursday, June 22, 2023 11:27:30 AM PDT Lucas De Marchi wrote:
> Most of the context workarounds tweak masked registers, but not all. For
> masked registers, when writing the value it's sufficient to just write
> the wa->set_bits since that will take care of both the clr and set bits
> as well as not overwriting other bits.
>
> However there are some workarounds, the registers are non-masked. Up
> until now the driver was simply emitting a MI_LOAD_REGISTER_IMM with the
> set_bits to program the register via the GPU in the WA bb. This has the
> side effect of overwriting the content of the register outside of bits
> that should be set and also doesn't handle the bits that should be
> cleared.
>
> Kenneth reported that on DG2, mesa was seeing a weird behavior due to
> the kernel programming of L3SQCREG5 in dg2_ctx_gt_tuning_init(). With
> the GPU idle, that register could be read via intel_reg as 0x00e001ff,
> but during a 3D workload it would change to 0x0000007f. So the
> programming of that tuning was affecting more than the bits in
> L3_PWM_TIMER_INIT_VAL_MASK. Matt Roper noticed the lack of rmw for the
> context workarounds due to the use of MI_LOAD_REGISTER_IMM.
>
> So, for registers that are not masked, read its value via mmio, modify
> and then set it in the buffer to be written by the GPU. This should take
> care in a simple way of programming just the bits required by the
> tuning/workaround. If in future there are registers that involved that
> can't be read by the CPU, a more complex approach may be required like
> a) issuing additional instructions to read and modify; or b) scan the
> golden context and patch it in place before saving it; or something
> else. But for now this should suffice.
>
> Scanning the context workarounds for all platforms, these are the
> impacted ones with the respective registers
>
> mtl: DRAW_WATERMARK
> mtl/dg2: XEHP_L3SQCREG5, XEHP_FF_MODE2
> gen12: GEN12_FF_MODE2
Speaking of GEN12_FF_MODE2...there's a big scary comment above that
workaround write which says that register "will return the wrong value
when read." I think with this patch, we'll start doing a RMW cycle for
the register, which could mix in some of this "wrong value". The
comment mentions that the intention is to write the whole register,
as the default value is 0 for all fields.
Maybe what we want to do is change gen12_ctx_gt_tuning_init to do
wa_write(wal, GEN12_FF_MODE2, FF_MODE2_TDS_TIMER_128);
so it has a clear mask of ~0 instead of FF_MODE2_TDS_TIMER_MASK, and
then in this patch update your condition below from
+ if (wa->masked_reg || wa->set == U32_MAX) {
to
+ if (wa->masked_reg || wa->set == U32_MAX || wa->clear == U32_MAX) {
because if we're clearing all bits then we don't care about doing a
read-modify-write either.
--Ken
[-- Attachment #2: This is a digitally signed message part. --]
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH 1/3] drm/i915/gt: Move wal_get_fw_for_rmw()
2023-06-22 18:27 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Move wal_get_fw_for_rmw() Lucas De Marchi
` (2 preceding siblings ...)
2023-06-22 19:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gt: Move wal_get_fw_for_rmw() Patchwork
@ 2023-06-22 23:37 ` Kenneth Graunke
2023-06-23 9:11 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] " Patchwork
4 siblings, 0 replies; 12+ messages in thread
From: Kenneth Graunke @ 2023-06-22 23:37 UTC (permalink / raw)
To: intel-gfx, Lucas De Marchi; +Cc: Lucas De Marchi, Matt Roper, stable, dri-devel
[-- Attachment #1: Type: text/plain, Size: 466 bytes --]
On Thursday, June 22, 2023 11:27:29 AM PDT Lucas De Marchi wrote:
> Move helper function to get all the forcewakes required by the wa list
> to the top, so it can be re-used by other functions.
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 32 ++++++++++-----------
> 1 file changed, 16 insertions(+), 16 deletions(-)
Patches 1 and 3 are:
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
[-- Attachment #2: This is a digitally signed message part. --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] drm/i915/gt: Move wal_get_fw_for_rmw()
2023-06-22 18:27 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Move wal_get_fw_for_rmw() Lucas De Marchi
` (3 preceding siblings ...)
2023-06-22 23:37 ` [Intel-gfx] [PATCH 1/3] " Kenneth Graunke
@ 2023-06-23 9:11 ` Patchwork
4 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2023-06-23 9:11 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
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== Series Details ==
Series: series starting with [1/3] drm/i915/gt: Move wal_get_fw_for_rmw()
URL : https://patchwork.freedesktop.org/series/119766/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13309_full -> Patchwork_119766v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_119766v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_119766v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (9 -> 8)
------------------------------
Missing (1): shard-rkl0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_119766v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_vblank@pipe-b-accuracy-idle:
- shard-glk: [PASS][1] -> [FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-glk3/igt@kms_vblank@pipe-b-accuracy-idle.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-glk5/igt@kms_vblank@pipe-b-accuracy-idle.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@kms_content_protection@atomic@pipe-a-dp-4:
- {shard-dg2}: NOTRUN -> [TIMEOUT][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-dg2-11/igt@kms_content_protection@atomic@pipe-a-dp-4.html
* igt@kms_frontbuffer_tracking@fbc-1p-rte:
- {shard-dg2}: [PASS][4] -> [FAIL][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-dg2-6/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-dg2-8/igt@kms_frontbuffer_tracking@fbc-1p-rte.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-dp-4:
- {shard-dg2}: NOTRUN -> [SKIP][6]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-dg2-11/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-c-dp-4.html
New tests
---------
New tests have been introduced between CI_DRM_13309_full and Patchwork_119766v1_full:
### New IGT tests (3) ###
* igt@kms_pipe_crc_basic@nonblocking-crc-frame-sequence@pipe-c-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-b-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-c-dp-2:
- Statuses : 1 pass(s)
- Exec time: [0.0] s
Known issues
------------
Here are the changes found in Patchwork_119766v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@crc32:
- shard-rkl: NOTRUN -> [SKIP][7] ([i915#6230])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@api_intel_bb@crc32.html
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- shard-rkl: NOTRUN -> [FAIL][8] ([i915#7742])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
* igt@feature_discovery@psr2:
- shard-rkl: NOTRUN -> [SKIP][9] ([i915#658])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@feature_discovery@psr2.html
* igt@gem_barrier_race@remote-request@rcs0:
- shard-apl: [PASS][10] -> [ABORT][11] ([i915#7461] / [i915#8211] / [i915#8234])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-apl6/igt@gem_barrier_race@remote-request@rcs0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-apl4/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_ccs@block-copy-compressed:
- shard-rkl: NOTRUN -> [SKIP][12] ([i915#3555] / [i915#4579] / [i915#5325])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-7/igt@gem_ccs@block-copy-compressed.html
* igt@gem_create@create-ext-set-pat:
- shard-glk: NOTRUN -> [FAIL][13] ([i915#8621])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-glk8/igt@gem_create@create-ext-set-pat.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-rkl: [PASS][14] -> [FAIL][15] ([i915#6268])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-rkl-4/igt@gem_ctx_exec@basic-nohangcheck.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-7/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_eio@hibernate:
- shard-rkl: NOTRUN -> [ABORT][16] ([i915#7975] / [i915#8213])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@gem_eio@hibernate.html
* igt@gem_exec_balancer@parallel-keep-submit-fence:
- shard-rkl: NOTRUN -> [SKIP][17] ([i915#4525])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-7/igt@gem_exec_balancer@parallel-keep-submit-fence.html
* igt@gem_exec_fair@basic-deadline:
- shard-rkl: [PASS][18] -> [FAIL][19] ([i915#2846])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-rkl-1/igt@gem_exec_fair@basic-deadline.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-4/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-glk: NOTRUN -> [FAIL][20] ([i915#2842]) +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-glk1/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@gem_exec_fair@basic-none@bcs0:
- shard-rkl: [PASS][21] -> [FAIL][22] ([i915#2842]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-rkl-6/igt@gem_exec_fair@basic-none@bcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-1/igt@gem_exec_fair@basic-none@bcs0.html
* igt@gem_exec_params@rsvd2-dirt:
- shard-rkl: NOTRUN -> [SKIP][23] ([fdo#109283])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@gem_exec_params@rsvd2-dirt.html
* igt@gem_exec_reloc@basic-wc-cpu:
- shard-rkl: NOTRUN -> [SKIP][24] ([i915#3281])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@gem_exec_reloc@basic-wc-cpu.html
* igt@gem_lmem_swapping@random-engines:
- shard-glk: NOTRUN -> [SKIP][25] ([fdo#109271] / [i915#4613]) +2 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-glk8/igt@gem_lmem_swapping@random-engines.html
* igt@gem_pxp@protected-encrypted-src-copy-not-readible:
- shard-rkl: NOTRUN -> [SKIP][26] ([i915#4270])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@gem_pxp@protected-encrypted-src-copy-not-readible.html
* igt@gen7_exec_parse@bitmasks:
- shard-rkl: NOTRUN -> [SKIP][27] ([fdo#109289])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@gen7_exec_parse@bitmasks.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [PASS][28] -> [ABORT][29] ([i915#5566])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-apl2/igt@gen9_exec_parse@allowed-all.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-apl1/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_dc@dc6-dpms:
- shard-rkl: NOTRUN -> [SKIP][30] ([i915#3361])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- shard-rkl: NOTRUN -> [SKIP][31] ([i915#1937] / [i915#4579])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-vga:
- shard-snb: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#4579]) +4 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-snb4/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-vga.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- shard-rkl: [PASS][33] -> [SKIP][34] ([i915#1397]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-rkl-7/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-2/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
* igt@i915_pm_rps@reset:
- shard-snb: [PASS][35] -> [DMESG-FAIL][36] ([i915#8319])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-snb2/igt@i915_pm_rps@reset.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-snb6/igt@i915_pm_rps@reset.html
* igt@kms_atomic_transition@modeset-transition:
- shard-apl: NOTRUN -> [SKIP][37] ([fdo#109271]) +5 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-apl4/igt@kms_atomic_transition@modeset-transition.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0:
- shard-rkl: NOTRUN -> [SKIP][38] ([i915#5286]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0.html
* igt@kms_big_fb@linear-16bpp-rotate-180:
- shard-apl: [PASS][39] -> [SKIP][40] ([fdo#109271]) +9 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-apl6/igt@kms_big_fb@linear-16bpp-rotate-180.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-apl4/igt@kms_big_fb@linear-16bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-rkl: NOTRUN -> [SKIP][41] ([fdo#111614] / [i915#3638])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-rkl: NOTRUN -> [SKIP][42] ([fdo#110723]) +1 similar issue
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-rkl: NOTRUN -> [SKIP][43] ([i915#3886] / [i915#5354] / [i915#6095]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-ccs-on-another-bo-yf_tiled_ccs:
- shard-rkl: NOTRUN -> [SKIP][44] ([i915#3734] / [i915#5354] / [i915#6095])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-7/igt@kms_ccs@pipe-b-ccs-on-another-bo-yf_tiled_ccs.html
* igt@kms_ccs@pipe-b-crc-primary-basic-4_tiled_dg2_rc_ccs:
- shard-rkl: NOTRUN -> [SKIP][45] ([i915#5354] / [i915#6095]) +3 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@kms_ccs@pipe-b-crc-primary-basic-4_tiled_dg2_rc_ccs.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#3886]) +4 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-glk9/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_rc_ccs:
- shard-rkl: NOTRUN -> [SKIP][47] ([i915#5354]) +8 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_gen12_rc_ccs.html
* igt@kms_chamelium_audio@hdmi-audio-edid:
- shard-rkl: NOTRUN -> [SKIP][48] ([i915#7828]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@kms_chamelium_audio@hdmi-audio-edid.html
* igt@kms_chamelium_color@ctm-green-to-red:
- shard-rkl: NOTRUN -> [SKIP][49] ([fdo#111827])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-7/igt@kms_chamelium_color@ctm-green-to-red.html
* igt@kms_color@ctm-red-to-blue@pipe-c:
- shard-apl: [PASS][50] -> [SKIP][51] ([fdo#109271] / [i915#4579])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-apl6/igt@kms_color@ctm-red-to-blue@pipe-c.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-apl4/igt@kms_color@ctm-red-to-blue@pipe-c.html
* igt@kms_content_protection@atomic-dpms:
- shard-rkl: NOTRUN -> [SKIP][52] ([i915#4579] / [i915#7118])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@kms_content_protection@atomic-dpms.html
* igt@kms_cursor_legacy@cursora-vs-flipb-legacy:
- shard-rkl: NOTRUN -> [SKIP][53] ([fdo#111825]) +4 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@kms_cursor_legacy@cursora-vs-flipb-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-apl: [PASS][54] -> [FAIL][55] ([i915#2346])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_dp_aux_dev:
- shard-rkl: NOTRUN -> [SKIP][56] ([i915#1257])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-7/igt@kms_dp_aux_dev.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][57] -> [FAIL][58] ([i915#79])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-glk5/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-glk1/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-hdmi-a1-hdmi-a2.html
* igt@kms_flip@flip-vs-suspend@c-dp1:
- shard-apl: [PASS][59] -> [ABORT][60] ([i915#180])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-apl4/igt@kms_flip@flip-vs-suspend@c-dp1.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-apl3/igt@kms_flip@flip-vs-suspend@c-dp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode:
- shard-rkl: NOTRUN -> [SKIP][61] ([i915#2672] / [i915#4579]) +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-7/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-upscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-glk: NOTRUN -> [SKIP][62] ([fdo#109271] / [i915#4579]) +11 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-glk9/igt@kms_flip_scaled_crc@flip-32bpp-ytileccs-to-64bpp-ytile-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt:
- shard-rkl: NOTRUN -> [SKIP][63] ([i915#3023]) +5 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
- shard-rkl: NOTRUN -> [SKIP][64] ([fdo#111825] / [i915#1825]) +10 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-rkl: NOTRUN -> [SKIP][65] ([i915#3555] / [i915#4579]) +2 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-2/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes:
- shard-apl: [PASS][66] -> [DMESG-WARN][67] ([i915#180])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html
* igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1:
- shard-glk: NOTRUN -> [FAIL][68] ([i915#7862]) +1 similar issue
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-glk9/igt@kms_plane_alpha_blend@alpha-basic@pipe-c-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][69] ([i915#5176]) +5 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][70] ([i915#4579] / [i915#5176]) +5 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-7/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-a-vga-1:
- shard-snb: NOTRUN -> [SKIP][71] ([fdo#109271]) +11 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-snb4/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-pixel-formats@pipe-a-vga-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][72] ([i915#4579] / [i915#5235]) +2 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-2/igt@kms_plane_scaling@planes-downscale-factor-0-25-upscale-20x20@pipe-b-hdmi-a-2.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][73] ([i915#5235]) +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-25@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-1:
- shard-glk: NOTRUN -> [SKIP][74] ([fdo#109271]) +135 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-glk9/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5:
- shard-apl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#4579]) +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-apl4/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-5.html
* igt@kms_psr2_sf@plane-move-sf-dmg-area:
- shard-rkl: NOTRUN -> [SKIP][76] ([fdo#111068] / [i915#658])
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@kms_psr2_sf@plane-move-sf-dmg-area.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-rkl: NOTRUN -> [SKIP][77] ([i915#1072]) +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_setmode@basic@pipe-a-hdmi-a-1:
- shard-snb: NOTRUN -> [FAIL][78] ([i915#5465]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-snb1/igt@kms_setmode@basic@pipe-a-hdmi-a-1.html
* igt@kms_setmode@invalid-clone-exclusive-crtc:
- shard-rkl: NOTRUN -> [SKIP][79] ([i915#3555] / [i915#4098] / [i915#4579])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-7/igt@kms_setmode@invalid-clone-exclusive-crtc.html
* igt@kms_vblank@pipe-c-wait-idle:
- shard-rkl: NOTRUN -> [SKIP][80] ([i915#4070] / [i915#6768]) +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@kms_vblank@pipe-c-wait-idle.html
* igt@kms_vblank@pipe-d-ts-continuation-modeset:
- shard-rkl: NOTRUN -> [SKIP][81] ([i915#4070] / [i915#533] / [i915#6768]) +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-7/igt@kms_vblank@pipe-d-ts-continuation-modeset.html
* igt@perf@per-context-mode-unprivileged:
- shard-rkl: NOTRUN -> [SKIP][82] ([i915#2435])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@perf@per-context-mode-unprivileged.html
* igt@prime_vgem@fence-write-hang:
- shard-rkl: NOTRUN -> [SKIP][83] ([fdo#109295] / [i915#3708])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-7/igt@prime_vgem@fence-write-hang.html
* igt@v3d/v3d_wait_bo@map-bo-1ns:
- shard-rkl: NOTRUN -> [SKIP][84] ([fdo#109315]) +2 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@v3d/v3d_wait_bo@map-bo-1ns.html
* igt@vc4/vc4_tiling@set-bad-flags:
- shard-rkl: NOTRUN -> [SKIP][85] ([i915#7711])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-6/igt@vc4/vc4_tiling@set-bad-flags.html
#### Possible fixes ####
* igt@gem_barrier_race@remote-request@rcs0:
- shard-rkl: [ABORT][86] ([i915#7461] / [i915#8211]) -> [PASS][87]
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-rkl-7/igt@gem_barrier_race@remote-request@rcs0.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-7/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_eio@kms:
- {shard-dg2}: [INCOMPLETE][88] ([i915#7892]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-dg2-7/igt@gem_eio@kms.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-dg2-3/igt@gem_eio@kms.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [FAIL][90] ([i915#2842]) -> [PASS][91] +1 similar issue
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-apl3/igt@gem_exec_fair@basic-none-solo@rcs0.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-apl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_softpin@noreloc-s3:
- {shard-dg2}: [INCOMPLETE][92] ([i915#7886]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-dg2-7/igt@gem_softpin@noreloc-s3.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-dg2-3/igt@gem_softpin@noreloc-s3.html
* igt@i915_pm_rc6_residency@rc6-idle@rcs0:
- {shard-dg1}: [FAIL][94] ([i915#3591]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
* igt@i915_pm_rpm@modeset-lpsp-stress:
- shard-rkl: [SKIP][96] ([i915#1397]) -> [PASS][97] +1 similar issue
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-rkl-4/igt@i915_pm_rpm@modeset-lpsp-stress.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-7/igt@i915_pm_rpm@modeset-lpsp-stress.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- {shard-dg1}: [SKIP][98] ([i915#1397]) -> [PASS][99]
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-dg1-19/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-dg1-13/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- {shard-dg2}: [SKIP][100] ([i915#1397]) -> [PASS][101] +1 similar issue
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-dg2-12/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-dg2-3/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_big_fb@yf-tiled-32bpp-rotate-0:
- shard-glk: [INCOMPLETE][102] -> [PASS][103]
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-glk2/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-glk7/igt@kms_big_fb@yf-tiled-32bpp-rotate-0.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [FAIL][104] ([i915#2346]) -> [PASS][105]
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
- shard-glk: [TIMEOUT][106] -> [PASS][107]
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
* igt@kms_cursor_legacy@single-move@pipe-b:
- {shard-dg2}: [INCOMPLETE][108] ([i915#8011]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-dg2-10/igt@kms_cursor_legacy@single-move@pipe-b.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-dg2-6/igt@kms_cursor_legacy@single-move@pipe-b.html
* igt@perf_pmu@busy-double-start@vecs0:
- {shard-dg1}: [FAIL][110] ([i915#4349]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-dg1-15/igt@perf_pmu@busy-double-start@vecs0.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-dg1-15/igt@perf_pmu@busy-double-start@vecs0.html
#### Warnings ####
* igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- shard-apl: [SKIP][112] ([fdo#109271] / [i915#3886]) -> [SKIP][113] ([fdo#109271])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-apl6/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-apl4/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-rkl: [SKIP][114] ([i915#3955]) -> [SKIP][115] ([fdo#110189] / [i915#3955])
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-rkl-7/igt@kms_fbcon_fbt@psr-suspend.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-2/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][116] ([i915#4070] / [i915#4816]) -> [SKIP][117] ([i915#4816])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-rkl-6/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-apl: [SKIP][118] ([fdo#109271] / [i915#533]) -> [SKIP][119] ([fdo#109271])
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13309/shard-apl6/igt@kms_vblank@pipe-d-wait-idle.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/shard-apl4/igt@kms_vblank@pipe-d-wait-idle.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2435]: https://gitlab.freedesktop.org/drm/intel/issues/2435
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#3023]: https://gitlab.freedesktop.org/drm/intel/issues/3023
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817
[i915#4936]: https://gitlab.freedesktop.org/drm/intel/issues/4936
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5465]: https://gitlab.freedesktop.org/drm/intel/issues/5465
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#6032]: https://gitlab.freedesktop.org/drm/intel/issues/6032
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6230]: https://gitlab.freedesktop.org/drm/intel/issues/6230
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
[i915#7173]: https://gitlab.freedesktop.org/drm/intel/issues/7173
[i915#7331]: https://gitlab.freedesktop.org/drm/intel/issues/7331
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7757]: https://gitlab.freedesktop.org/drm/intel/issues/7757
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7862]: https://gitlab.freedesktop.org/drm/intel/issues/7862
[i915#7886]: https://gitlab.freedesktop.org/drm/intel/issues/7886
[i915#7892]: https://gitlab.freedesktop.org/drm/intel/issues/7892
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8319]: https://gitlab.freedesktop.org/drm/intel/issues/8319
[i915#8621]: https://gitlab.freedesktop.org/drm/intel/issues/8621
[i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
Build changes
-------------
* Linux: CI_DRM_13309 -> Patchwork_119766v1
CI-20190529: 20190529
CI_DRM_13309: af67b02abf56a5018cd885c94d7611241052e98f @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7346: 29302a0d57bcf10cb553f5d7ff5bb99166a19bba @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_119766v1: af67b02abf56a5018cd885c94d7611241052e98f @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_119766v1/index.html
[-- Attachment #2: Type: text/html, Size: 40058 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Fix context workarounds with non-masked regs
2023-06-22 23:37 ` Kenneth Graunke
@ 2023-06-23 15:49 ` Lucas De Marchi
2023-06-23 19:48 ` Kenneth Graunke
0 siblings, 1 reply; 12+ messages in thread
From: Lucas De Marchi @ 2023-06-23 15:49 UTC (permalink / raw)
To: Kenneth Graunke; +Cc: intel-gfx, Matt Roper, stable, dri-devel
On Thu, Jun 22, 2023 at 04:37:21PM -0700, Kenneth Graunke wrote:
>On Thursday, June 22, 2023 11:27:30 AM PDT Lucas De Marchi wrote:
>> Most of the context workarounds tweak masked registers, but not all. For
>> masked registers, when writing the value it's sufficient to just write
>> the wa->set_bits since that will take care of both the clr and set bits
>> as well as not overwriting other bits.
>>
>> However there are some workarounds, the registers are non-masked. Up
>> until now the driver was simply emitting a MI_LOAD_REGISTER_IMM with the
>> set_bits to program the register via the GPU in the WA bb. This has the
>> side effect of overwriting the content of the register outside of bits
>> that should be set and also doesn't handle the bits that should be
>> cleared.
>>
>> Kenneth reported that on DG2, mesa was seeing a weird behavior due to
>> the kernel programming of L3SQCREG5 in dg2_ctx_gt_tuning_init(). With
>> the GPU idle, that register could be read via intel_reg as 0x00e001ff,
>> but during a 3D workload it would change to 0x0000007f. So the
>> programming of that tuning was affecting more than the bits in
>> L3_PWM_TIMER_INIT_VAL_MASK. Matt Roper noticed the lack of rmw for the
>> context workarounds due to the use of MI_LOAD_REGISTER_IMM.
>>
>> So, for registers that are not masked, read its value via mmio, modify
>> and then set it in the buffer to be written by the GPU. This should take
>> care in a simple way of programming just the bits required by the
>> tuning/workaround. If in future there are registers that involved that
>> can't be read by the CPU, a more complex approach may be required like
>> a) issuing additional instructions to read and modify; or b) scan the
>> golden context and patch it in place before saving it; or something
>> else. But for now this should suffice.
>>
>> Scanning the context workarounds for all platforms, these are the
>> impacted ones with the respective registers
>>
>> mtl: DRAW_WATERMARK
>> mtl/dg2: XEHP_L3SQCREG5, XEHP_FF_MODE2
>> gen12: GEN12_FF_MODE2
>
>Speaking of GEN12_FF_MODE2...there's a big scary comment above that
>workaround write which says that register "will return the wrong value
>when read." I think with this patch, we'll start doing a RMW cycle for
>the register, which could mix in some of this "wrong value". The
>comment mentions that the intention is to write the whole register,
>as the default value is 0 for all fields.
Good point. That also means we don't need to backport this patch to
stable kernel to any gen12, since overwritting the other bits is
actually the intended behavior.
>
>Maybe what we want to do is change gen12_ctx_gt_tuning_init to do
>
> wa_write(wal, GEN12_FF_MODE2, FF_MODE2_TDS_TIMER_128);
>
>so it has a clear mask of ~0 instead of FF_MODE2_TDS_TIMER_MASK, and
In order to ignore read back when verifying, we would still need to use
wa_add(), but changing the mask. We don't have a wa_write() that ends up
with { .clr = ~0, .read_mask = 0 }.
wa_add(wal,
GEN12_FF_MODE2,
~0, FF_MODE2_TDS_TIMER_128,
0, false);
>then in this patch update your condition below from
>
>+ if (wa->masked_reg || wa->set == U32_MAX) {
>
>to
>
>+ if (wa->masked_reg || wa->set == U32_MAX || wa->clear == U32_MAX) {
yeah... and maybe also warn if wa->read is 0, which means it's one
of the registers we can't/shouldn't read from the CPU.
>
>because if we're clearing all bits then we don't care about doing a
>read-modify-write either.
thanks
Lucas De Marchi
>
>--Ken
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Fix context workarounds with non-masked regs
2023-06-23 15:49 ` Lucas De Marchi
@ 2023-06-23 19:48 ` Kenneth Graunke
2023-06-23 21:05 ` Lucas De Marchi
0 siblings, 1 reply; 12+ messages in thread
From: Kenneth Graunke @ 2023-06-23 19:48 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx, Matt Roper, stable, dri-devel
[-- Attachment #1: Type: text/plain, Size: 4142 bytes --]
On Friday, June 23, 2023 8:49:05 AM PDT Lucas De Marchi wrote:
> On Thu, Jun 22, 2023 at 04:37:21PM -0700, Kenneth Graunke wrote:
> >On Thursday, June 22, 2023 11:27:30 AM PDT Lucas De Marchi wrote:
> >> Most of the context workarounds tweak masked registers, but not all. For
> >> masked registers, when writing the value it's sufficient to just write
> >> the wa->set_bits since that will take care of both the clr and set bits
> >> as well as not overwriting other bits.
> >>
> >> However there are some workarounds, the registers are non-masked. Up
> >> until now the driver was simply emitting a MI_LOAD_REGISTER_IMM with the
> >> set_bits to program the register via the GPU in the WA bb. This has the
> >> side effect of overwriting the content of the register outside of bits
> >> that should be set and also doesn't handle the bits that should be
> >> cleared.
> >>
> >> Kenneth reported that on DG2, mesa was seeing a weird behavior due to
> >> the kernel programming of L3SQCREG5 in dg2_ctx_gt_tuning_init(). With
> >> the GPU idle, that register could be read via intel_reg as 0x00e001ff,
> >> but during a 3D workload it would change to 0x0000007f. So the
> >> programming of that tuning was affecting more than the bits in
> >> L3_PWM_TIMER_INIT_VAL_MASK. Matt Roper noticed the lack of rmw for the
> >> context workarounds due to the use of MI_LOAD_REGISTER_IMM.
> >>
> >> So, for registers that are not masked, read its value via mmio, modify
> >> and then set it in the buffer to be written by the GPU. This should take
> >> care in a simple way of programming just the bits required by the
> >> tuning/workaround. If in future there are registers that involved that
> >> can't be read by the CPU, a more complex approach may be required like
> >> a) issuing additional instructions to read and modify; or b) scan the
> >> golden context and patch it in place before saving it; or something
> >> else. But for now this should suffice.
> >>
> >> Scanning the context workarounds for all platforms, these are the
> >> impacted ones with the respective registers
> >>
> >> mtl: DRAW_WATERMARK
> >> mtl/dg2: XEHP_L3SQCREG5, XEHP_FF_MODE2
> >> gen12: GEN12_FF_MODE2
> >
> >Speaking of GEN12_FF_MODE2...there's a big scary comment above that
> >workaround write which says that register "will return the wrong value
> >when read." I think with this patch, we'll start doing a RMW cycle for
> >the register, which could mix in some of this "wrong value". The
> >comment mentions that the intention is to write the whole register,
> >as the default value is 0 for all fields.
>
> Good point. That also means we don't need to backport this patch to
> stable kernel to any gen12, since overwritting the other bits is
> actually the intended behavior.
>
> >
> >Maybe what we want to do is change gen12_ctx_gt_tuning_init to do
> >
> > wa_write(wal, GEN12_FF_MODE2, FF_MODE2_TDS_TIMER_128);
> >
> >so it has a clear mask of ~0 instead of FF_MODE2_TDS_TIMER_MASK, and
>
> In order to ignore read back when verifying, we would still need to use
> wa_add(), but changing the mask. We don't have a wa_write() that ends up
> with { .clr = ~0, .read_mask = 0 }.
>
> wa_add(wal,
> GEN12_FF_MODE2,
> ~0, FF_MODE2_TDS_TIMER_128,
> 0, false);
Good point! Though, I just noticed another bug here:
gen12_ctx_workarounds_init sets FF_MODE2_GS_TIMER_224 to avoid hangs
in the HS/DS unit, after gen12_ctx_gt_tuning_init set TDS_TIMER_128
for performance. One of those is going to clobber the other; we're
likely losing the TDS tuning today. Combining those workarounds into
one place seems like an easy way to fix that.
> >then in this patch update your condition below from
> >
> >+ if (wa->masked_reg || wa->set == U32_MAX) {
> >
> >to
> >
> >+ if (wa->masked_reg || wa->set == U32_MAX || wa->clear == U32_MAX) {
>
> yeah... and maybe also warn if wa->read is 0, which means it's one
> of the registers we can't/shouldn't read from the CPU.
>
> >
> >because if we're clearing all bits then we don't care about doing a
> >read-modify-write either.
>
> thanks
> Lucas De Marchi
>
> >
> >--Ken
>
>
>
[-- Attachment #2: This is a digitally signed message part. --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Fix context workarounds with non-masked regs
2023-06-23 19:48 ` Kenneth Graunke
@ 2023-06-23 21:05 ` Lucas De Marchi
2023-06-23 21:56 ` Matt Roper
0 siblings, 1 reply; 12+ messages in thread
From: Lucas De Marchi @ 2023-06-23 21:05 UTC (permalink / raw)
To: Kenneth Graunke; +Cc: intel-gfx, Matt Roper, stable, dri-devel
On Fri, Jun 23, 2023 at 12:48:13PM -0700, Kenneth Graunke wrote:
>On Friday, June 23, 2023 8:49:05 AM PDT Lucas De Marchi wrote:
>> On Thu, Jun 22, 2023 at 04:37:21PM -0700, Kenneth Graunke wrote:
>> >On Thursday, June 22, 2023 11:27:30 AM PDT Lucas De Marchi wrote:
>> >> Most of the context workarounds tweak masked registers, but not all. For
>> >> masked registers, when writing the value it's sufficient to just write
>> >> the wa->set_bits since that will take care of both the clr and set bits
>> >> as well as not overwriting other bits.
>> >>
>> >> However there are some workarounds, the registers are non-masked. Up
>> >> until now the driver was simply emitting a MI_LOAD_REGISTER_IMM with the
>> >> set_bits to program the register via the GPU in the WA bb. This has the
>> >> side effect of overwriting the content of the register outside of bits
>> >> that should be set and also doesn't handle the bits that should be
>> >> cleared.
>> >>
>> >> Kenneth reported that on DG2, mesa was seeing a weird behavior due to
>> >> the kernel programming of L3SQCREG5 in dg2_ctx_gt_tuning_init(). With
>> >> the GPU idle, that register could be read via intel_reg as 0x00e001ff,
>> >> but during a 3D workload it would change to 0x0000007f. So the
>> >> programming of that tuning was affecting more than the bits in
>> >> L3_PWM_TIMER_INIT_VAL_MASK. Matt Roper noticed the lack of rmw for the
>> >> context workarounds due to the use of MI_LOAD_REGISTER_IMM.
>> >>
>> >> So, for registers that are not masked, read its value via mmio, modify
>> >> and then set it in the buffer to be written by the GPU. This should take
>> >> care in a simple way of programming just the bits required by the
>> >> tuning/workaround. If in future there are registers that involved that
>> >> can't be read by the CPU, a more complex approach may be required like
>> >> a) issuing additional instructions to read and modify; or b) scan the
>> >> golden context and patch it in place before saving it; or something
>> >> else. But for now this should suffice.
>> >>
>> >> Scanning the context workarounds for all platforms, these are the
>> >> impacted ones with the respective registers
>> >>
>> >> mtl: DRAW_WATERMARK
>> >> mtl/dg2: XEHP_L3SQCREG5, XEHP_FF_MODE2
>> >> gen12: GEN12_FF_MODE2
>> >
>> >Speaking of GEN12_FF_MODE2...there's a big scary comment above that
>> >workaround write which says that register "will return the wrong value
>> >when read." I think with this patch, we'll start doing a RMW cycle for
>> >the register, which could mix in some of this "wrong value". The
>> >comment mentions that the intention is to write the whole register,
>> >as the default value is 0 for all fields.
>>
>> Good point. That also means we don't need to backport this patch to
>> stable kernel to any gen12, since overwritting the other bits is
>> actually the intended behavior.
>>
>> >
>> >Maybe what we want to do is change gen12_ctx_gt_tuning_init to do
>> >
>> > wa_write(wal, GEN12_FF_MODE2, FF_MODE2_TDS_TIMER_128);
>> >
>> >so it has a clear mask of ~0 instead of FF_MODE2_TDS_TIMER_MASK, and
>>
>> In order to ignore read back when verifying, we would still need to use
>> wa_add(), but changing the mask. We don't have a wa_write() that ends up
>> with { .clr = ~0, .read_mask = 0 }.
>>
>> wa_add(wal,
>> GEN12_FF_MODE2,
>> ~0, FF_MODE2_TDS_TIMER_128,
>> 0, false);
>
>Good point! Though, I just noticed another bug here:
>
>gen12_ctx_workarounds_init sets FF_MODE2_GS_TIMER_224 to avoid hangs
>in the HS/DS unit, after gen12_ctx_gt_tuning_init set TDS_TIMER_128
>for performance. One of those is going to clobber the other; we're
>likely losing the TDS tuning today. Combining those workarounds into
we are not losing it today. As long as the wa list is the same, we do detect collisions when
adding workarounds and they are coallesced before applying. However,
indeed if we change this to make clear be ~0, then they will collide and
we will see a warning.
Applying them together in a single operation would indeed solve it
with a side-effect of moving this back to the workarounds. Either that
or
a) we handle the read_back == 0 && clear == U32_MAX specially when
adding WAs. If that is true, then the check for collisions can
be adjusted to allow that.
b) we give up on this approach and proceed with one of
1) scan the ctx wa list. If it has any non-masked register,
we submit a job to read it from the GPU side. MCR will
make this harder as the steering from the GPU side is
different than the CPU
2) emit additional commands to read and modify the register from
the GPU side
3) find the register in the golden context and patch it in place
>one place seems like an easy way to fix that.
I'm leaning towards this option in the hope we don't have have
another GEN12_FF_MODE2 in future.
Matt, we've been pushing towards separating the tuning from the WAs, but
here we'd go the other way. Anything against doing this for now?
thanks
Lucas De Marchi
>
>> >then in this patch update your condition below from
>> >
>> >+ if (wa->masked_reg || wa->set == U32_MAX) {
>> >
>> >to
>> >
>> >+ if (wa->masked_reg || wa->set == U32_MAX || wa->clear == U32_MAX) {
>>
>> yeah... and maybe also warn if wa->read is 0, which means it's one
>> of the registers we can't/shouldn't read from the CPU.
>>
>> >
>> >because if we're clearing all bits then we don't care about doing a
>> >read-modify-write either.
>>
>> thanks
>> Lucas De Marchi
>>
>> >
>> >--Ken
>>
>>
>>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Fix context workarounds with non-masked regs
2023-06-23 21:05 ` Lucas De Marchi
@ 2023-06-23 21:56 ` Matt Roper
2023-06-24 18:12 ` Lucas De Marchi
0 siblings, 1 reply; 12+ messages in thread
From: Matt Roper @ 2023-06-23 21:56 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: stable, Kenneth Graunke, intel-gfx, dri-devel
On Fri, Jun 23, 2023 at 02:05:20PM -0700, Lucas De Marchi wrote:
> On Fri, Jun 23, 2023 at 12:48:13PM -0700, Kenneth Graunke wrote:
> > On Friday, June 23, 2023 8:49:05 AM PDT Lucas De Marchi wrote:
> > > On Thu, Jun 22, 2023 at 04:37:21PM -0700, Kenneth Graunke wrote:
> > > >On Thursday, June 22, 2023 11:27:30 AM PDT Lucas De Marchi wrote:
> > > >> Most of the context workarounds tweak masked registers, but not all. For
> > > >> masked registers, when writing the value it's sufficient to just write
> > > >> the wa->set_bits since that will take care of both the clr and set bits
> > > >> as well as not overwriting other bits.
> > > >>
> > > >> However there are some workarounds, the registers are non-masked. Up
> > > >> until now the driver was simply emitting a MI_LOAD_REGISTER_IMM with the
> > > >> set_bits to program the register via the GPU in the WA bb. This has the
> > > >> side effect of overwriting the content of the register outside of bits
> > > >> that should be set and also doesn't handle the bits that should be
> > > >> cleared.
> > > >>
> > > >> Kenneth reported that on DG2, mesa was seeing a weird behavior due to
> > > >> the kernel programming of L3SQCREG5 in dg2_ctx_gt_tuning_init(). With
> > > >> the GPU idle, that register could be read via intel_reg as 0x00e001ff,
> > > >> but during a 3D workload it would change to 0x0000007f. So the
> > > >> programming of that tuning was affecting more than the bits in
> > > >> L3_PWM_TIMER_INIT_VAL_MASK. Matt Roper noticed the lack of rmw for the
> > > >> context workarounds due to the use of MI_LOAD_REGISTER_IMM.
> > > >>
> > > >> So, for registers that are not masked, read its value via mmio, modify
> > > >> and then set it in the buffer to be written by the GPU. This should take
> > > >> care in a simple way of programming just the bits required by the
> > > >> tuning/workaround. If in future there are registers that involved that
> > > >> can't be read by the CPU, a more complex approach may be required like
> > > >> a) issuing additional instructions to read and modify; or b) scan the
> > > >> golden context and patch it in place before saving it; or something
> > > >> else. But for now this should suffice.
> > > >>
> > > >> Scanning the context workarounds for all platforms, these are the
> > > >> impacted ones with the respective registers
> > > >>
> > > >> mtl: DRAW_WATERMARK
> > > >> mtl/dg2: XEHP_L3SQCREG5, XEHP_FF_MODE2
> > > >> gen12: GEN12_FF_MODE2
> > > >
> > > >Speaking of GEN12_FF_MODE2...there's a big scary comment above that
> > > >workaround write which says that register "will return the wrong value
> > > >when read." I think with this patch, we'll start doing a RMW cycle for
> > > >the register, which could mix in some of this "wrong value". The
> > > >comment mentions that the intention is to write the whole register,
> > > >as the default value is 0 for all fields.
> > >
> > > Good point. That also means we don't need to backport this patch to
> > > stable kernel to any gen12, since overwritting the other bits is
> > > actually the intended behavior.
> > >
> > > >
> > > >Maybe what we want to do is change gen12_ctx_gt_tuning_init to do
> > > >
> > > > wa_write(wal, GEN12_FF_MODE2, FF_MODE2_TDS_TIMER_128);
> > > >
> > > >so it has a clear mask of ~0 instead of FF_MODE2_TDS_TIMER_MASK, and
> > >
> > > In order to ignore read back when verifying, we would still need to use
> > > wa_add(), but changing the mask. We don't have a wa_write() that ends up
> > > with { .clr = ~0, .read_mask = 0 }.
> > >
> > > wa_add(wal,
> > > GEN12_FF_MODE2,
> > > ~0, FF_MODE2_TDS_TIMER_128,
> > > 0, false);
> >
> > Good point! Though, I just noticed another bug here:
> >
> > gen12_ctx_workarounds_init sets FF_MODE2_GS_TIMER_224 to avoid hangs
> > in the HS/DS unit, after gen12_ctx_gt_tuning_init set TDS_TIMER_128
> > for performance. One of those is going to clobber the other; we're
> > likely losing the TDS tuning today. Combining those workarounds into
>
> we are not losing it today. As long as the wa list is the same, we do detect collisions when
> adding workarounds and they are coallesced before applying. However,
> indeed if we change this to make clear be ~0, then they will collide and
> we will see a warning.
>
> Applying them together in a single operation would indeed solve it
> with a side-effect of moving this back to the workarounds. Either that
> or
>
> a) we handle the read_back == 0 && clear == U32_MAX specially when
> adding WAs. If that is true, then the check for collisions can
> be adjusted to allow that.
>
> b) we give up on this approach and proceed with one of
>
> 1) scan the ctx wa list. If it has any non-masked register,
> we submit a job to read it from the GPU side. MCR will
> make this harder as the steering from the GPU side is
> different than the CPU
>
> 2) emit additional commands to read and modify the register from
> the GPU side
>
> 3) find the register in the golden context and patch it in place
>
>
>
>
> > one place seems like an easy way to fix that.
>
> I'm leaning towards this option in the hope we don't have have
> another GEN12_FF_MODE2 in future.
>
> Matt, we've been pushing towards separating the tuning from the WAs, but
> here we'd go the other way. Anything against doing this for now?
That's probably fine as long as we leave a comment behind in the tuning
section explaining why that specific setting is found in a different
spot.
Matt
>
> thanks
> Lucas De Marchi
>
> >
> > > >then in this patch update your condition below from
> > > >
> > > >+ if (wa->masked_reg || wa->set == U32_MAX) {
> > > >
> > > >to
> > > >
> > > >+ if (wa->masked_reg || wa->set == U32_MAX || wa->clear == U32_MAX) {
> > >
> > > yeah... and maybe also warn if wa->read is 0, which means it's one
> > > of the registers we can't/shouldn't read from the CPU.
> > >
> > > >
> > > >because if we're clearing all bits then we don't care about doing a
> > > >read-modify-write either.
> > >
> > > thanks
> > > Lucas De Marchi
> > >
> > > >
> > > >--Ken
> > >
> > >
> > >
> >
>
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH 2/3] drm/i915/gt: Fix context workarounds with non-masked regs
2023-06-23 21:56 ` Matt Roper
@ 2023-06-24 18:12 ` Lucas De Marchi
0 siblings, 0 replies; 12+ messages in thread
From: Lucas De Marchi @ 2023-06-24 18:12 UTC (permalink / raw)
To: Matt Roper; +Cc: dri-devel, Kenneth Graunke, intel-gfx, stable
On Fri, Jun 23, 2023 at 02:56:46PM -0700, Matt Roper wrote:
>On Fri, Jun 23, 2023 at 02:05:20PM -0700, Lucas De Marchi wrote:
>> On Fri, Jun 23, 2023 at 12:48:13PM -0700, Kenneth Graunke wrote:
>> > On Friday, June 23, 2023 8:49:05 AM PDT Lucas De Marchi wrote:
>> > > On Thu, Jun 22, 2023 at 04:37:21PM -0700, Kenneth Graunke wrote:
>> > > >On Thursday, June 22, 2023 11:27:30 AM PDT Lucas De Marchi wrote:
>> > > >> Most of the context workarounds tweak masked registers, but not all. For
>> > > >> masked registers, when writing the value it's sufficient to just write
>> > > >> the wa->set_bits since that will take care of both the clr and set bits
>> > > >> as well as not overwriting other bits.
>> > > >>
>> > > >> However there are some workarounds, the registers are non-masked. Up
>> > > >> until now the driver was simply emitting a MI_LOAD_REGISTER_IMM with the
>> > > >> set_bits to program the register via the GPU in the WA bb. This has the
>> > > >> side effect of overwriting the content of the register outside of bits
>> > > >> that should be set and also doesn't handle the bits that should be
>> > > >> cleared.
>> > > >>
>> > > >> Kenneth reported that on DG2, mesa was seeing a weird behavior due to
>> > > >> the kernel programming of L3SQCREG5 in dg2_ctx_gt_tuning_init(). With
>> > > >> the GPU idle, that register could be read via intel_reg as 0x00e001ff,
>> > > >> but during a 3D workload it would change to 0x0000007f. So the
>> > > >> programming of that tuning was affecting more than the bits in
>> > > >> L3_PWM_TIMER_INIT_VAL_MASK. Matt Roper noticed the lack of rmw for the
>> > > >> context workarounds due to the use of MI_LOAD_REGISTER_IMM.
>> > > >>
>> > > >> So, for registers that are not masked, read its value via mmio, modify
>> > > >> and then set it in the buffer to be written by the GPU. This should take
>> > > >> care in a simple way of programming just the bits required by the
>> > > >> tuning/workaround. If in future there are registers that involved that
>> > > >> can't be read by the CPU, a more complex approach may be required like
>> > > >> a) issuing additional instructions to read and modify; or b) scan the
>> > > >> golden context and patch it in place before saving it; or something
>> > > >> else. But for now this should suffice.
>> > > >>
>> > > >> Scanning the context workarounds for all platforms, these are the
>> > > >> impacted ones with the respective registers
>> > > >>
>> > > >> mtl: DRAW_WATERMARK
>> > > >> mtl/dg2: XEHP_L3SQCREG5, XEHP_FF_MODE2
>> > > >> gen12: GEN12_FF_MODE2
>> > > >
>> > > >Speaking of GEN12_FF_MODE2...there's a big scary comment above that
>> > > >workaround write which says that register "will return the wrong value
>> > > >when read." I think with this patch, we'll start doing a RMW cycle for
>> > > >the register, which could mix in some of this "wrong value". The
>> > > >comment mentions that the intention is to write the whole register,
>> > > >as the default value is 0 for all fields.
>> > >
>> > > Good point. That also means we don't need to backport this patch to
>> > > stable kernel to any gen12, since overwritting the other bits is
>> > > actually the intended behavior.
>> > >
>> > > >
>> > > >Maybe what we want to do is change gen12_ctx_gt_tuning_init to do
>> > > >
>> > > > wa_write(wal, GEN12_FF_MODE2, FF_MODE2_TDS_TIMER_128);
>> > > >
>> > > >so it has a clear mask of ~0 instead of FF_MODE2_TDS_TIMER_MASK, and
>> > >
>> > > In order to ignore read back when verifying, we would still need to use
>> > > wa_add(), but changing the mask. We don't have a wa_write() that ends up
>> > > with { .clr = ~0, .read_mask = 0 }.
>> > >
>> > > wa_add(wal,
>> > > GEN12_FF_MODE2,
>> > > ~0, FF_MODE2_TDS_TIMER_128,
>> > > 0, false);
>> >
>> > Good point! Though, I just noticed another bug here:
>> >
>> > gen12_ctx_workarounds_init sets FF_MODE2_GS_TIMER_224 to avoid hangs
>> > in the HS/DS unit, after gen12_ctx_gt_tuning_init set TDS_TIMER_128
>> > for performance. One of those is going to clobber the other; we're
>> > likely losing the TDS tuning today. Combining those workarounds into
>>
>> we are not losing it today. As long as the wa list is the same, we do detect collisions when
>> adding workarounds and they are coallesced before applying. However,
>> indeed if we change this to make clear be ~0, then they will collide and
>> we will see a warning.
>>
>> Applying them together in a single operation would indeed solve it
>> with a side-effect of moving this back to the workarounds. Either that
>> or
>>
>> a) we handle the read_back == 0 && clear == U32_MAX specially when
>> adding WAs. If that is true, then the check for collisions can
>> be adjusted to allow that.
>>
>> b) we give up on this approach and proceed with one of
>>
>> 1) scan the ctx wa list. If it has any non-masked register,
>> we submit a job to read it from the GPU side. MCR will
>> make this harder as the steering from the GPU side is
>> different than the CPU
>>
>> 2) emit additional commands to read and modify the register from
>> the GPU side
>>
>> 3) find the register in the golden context and patch it in place
>>
>>
>>
>>
>> > one place seems like an easy way to fix that.
>>
>> I'm leaning towards this option in the hope we don't have have
>> another GEN12_FF_MODE2 in future.
>>
>> Matt, we've been pushing towards separating the tuning from the WAs, but
>> here we'd go the other way. Anything against doing this for now?
>
>That's probably fine as long as we leave a comment behind in the tuning
>section explaining why that specific setting is found in a different
>spot.
alright, just submitted a new version with a few more changes.
thanks
Lucas De Marchi
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2023-06-24 18:12 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-06-22 18:27 [Intel-gfx] [PATCH 1/3] drm/i915/gt: Move wal_get_fw_for_rmw() Lucas De Marchi
2023-06-22 18:27 ` [Intel-gfx] [PATCH 2/3] drm/i915/gt: Fix context workarounds with non-masked regs Lucas De Marchi
2023-06-22 23:37 ` Kenneth Graunke
2023-06-23 15:49 ` Lucas De Marchi
2023-06-23 19:48 ` Kenneth Graunke
2023-06-23 21:05 ` Lucas De Marchi
2023-06-23 21:56 ` Matt Roper
2023-06-24 18:12 ` Lucas De Marchi
2023-06-22 18:27 ` [Intel-gfx] [PATCH 3/3] drm/i915/gt: Drop read from GEN8_L3CNTLREG in ICL workaround Lucas De Marchi
2023-06-22 19:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/gt: Move wal_get_fw_for_rmw() Patchwork
2023-06-22 23:37 ` [Intel-gfx] [PATCH 1/3] " Kenneth Graunke
2023-06-23 9:11 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for series starting with [1/3] " Patchwork
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