[Intel-gfx] [PATCH v3 0/7] Add DSC PPS readout

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* [Intel-gfx] [PATCH v3 0/7] Add DSC PPS readout
@ 2023-07-17 10:09 Suraj Kandpal
  2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 1/7] drm/i915/vdsc: Refactor dsc register field macro Suraj Kandpal
                   ` (9 more replies)
  0 siblings, 10 replies; 13+ messages in thread
From: Suraj Kandpal @ 2023-07-17 10:09 UTC (permalink / raw)
  To: intel-gfx; +Cc: Jani Nikula

Up until now we only verified one or two of the dsc pps
params like bits_per_component and bits_per_pixel this
patch series aim to readout almost all PPS param and get
them compared.
Along with that some work on making a common function to
read and write PPS param regiters is also done.

--v2
-Remove duplicated code and create function that fetches register
and reuse that. [Jani]
-move WARN_ON one abstraction layer up. [Jani]
-Split patch so that refactor and a new functionality is not added
in the same patch. [Jani]
-Add a new refactor patch so that bit shifting can be done in a
clean way. [Jani]

--v3
-Fix the typo in patch 2 [Jani]
-Get both dsc_reg regardless of dsc_eng_no. [Jani]
-Remove usage of num_vdsc_instances. [Ankit]
-Add macro to further optimize intel_dsc_get_pps_reg

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>

Suraj Kandpal (7):
  drm/i915/vdsc: Refactor dsc register field macro
  drm/i915/vdsc: Add a check for dsc split cases
  drm/i915/vdsc: Add function to read any PPS register
  drm/i915/vdsc: Use MACRO to cleanup intel_dsc_get_pps_reg
  drm/i915/vdsc: Add function to write in PPS register
  drm/i915/vdsc: Fill the intel_dsc_get_pps_config function
  drm/i915/display: Compare the readout dsc pps params

 drivers/gpu/drm/i915/display/intel_display.c  |  31 ++
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 506 +++++++++---------
 .../gpu/drm/i915/display/intel_vdsc_regs.h    | 101 +++-
 3 files changed, 347 insertions(+), 291 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 13+ messages in thread

* [Intel-gfx] [PATCH v3 1/7] drm/i915/vdsc: Refactor dsc register field macro
  2023-07-17 10:09 [Intel-gfx] [PATCH v3 0/7] Add DSC PPS readout Suraj Kandpal
@ 2023-07-17 10:09 ` Suraj Kandpal
  2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 2/7] drm/i915/vdsc: Add a check for dsc split cases Suraj Kandpal
                   ` (8 subsequent siblings)
  9 siblings, 0 replies; 13+ messages in thread
From: Suraj Kandpal @ 2023-07-17 10:09 UTC (permalink / raw)
  To: intel-gfx

This patch refactors dsc register related macros that prepares
the values to be written in the register. The current bit shifting
looks bad and going forward will not serve our purpose to readout
dsc register field values the change was suggested by Jani Nikula.

Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 .../gpu/drm/i915/display/intel_vdsc_regs.h    | 98 +++++++++++++------
 1 file changed, 70 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index b71f00b5c761..785ede31116e 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -57,7 +57,8 @@
 #define MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _MTL_DSC1_PICTURE_PARAMETER_SET_17_PB, \
 							   _MTL_DSC1_PICTURE_PARAMETER_SET_17_PC)
-#define DSC_SL_BPG_OFFSET(offset)		((offset) << 27)
+#define DSC_SL_BPG_OFFSET_MASK			REG_GENMASK(31, 27)
+#define DSC_SL_BPG_OFFSET(offset)		REG_FIELD_PREP(DSC_SL_BPG_OFFSET_MASK, offset)
 
 #define _MTL_DSC0_PICTURE_PARAMETER_SET_18_PB	0x782B8
 #define _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB	0x783B8
@@ -69,8 +70,10 @@
 #define MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _MTL_DSC1_PICTURE_PARAMETER_SET_18_PB, \
 							   _MTL_DSC1_PICTURE_PARAMETER_SET_18_PC)
-#define DSC_NSL_BPG_OFFSET(offset)		((offset) << 16)
-#define DSC_SL_OFFSET_ADJ(offset)		((offset) << 0)
+#define DSC_NSL_BPG_OFFSET_MASK			REG_GENMASK(31, 16)
+#define DSC_SL_OFFSET_ADJ_MASK			REG_GENMASK(15, 0)
+#define DSC_NSL_BPG_OFFSET(offset)		REG_FIELD_PREP(DSC_NSL_BPG_OFFSET_MASK, offset)
+#define DSC_SL_OFFSET_ADJ(offset)		REG_FIELD_PREP(DSC_SL_OFFSET_ADJ_MASK, offset)
 
 /* Icelake Display Stream Compression Registers */
 #define DSCA_PICTURE_PARAMETER_SET_0		_MMIO(0x6B200)
@@ -123,8 +126,10 @@
 #define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 					    _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
 					    _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
-#define  DSC_PIC_WIDTH(pic_width)	((pic_width) << 16)
-#define  DSC_PIC_HEIGHT(pic_height)	((pic_height) << 0)
+#define  DSC_PIC_WIDTH_MASK		REG_GENMASK(31, 16)
+#define  DSC_PIC_HEIGHT_MASK		REG_GENMASK(15, 0)
+#define  DSC_PIC_WIDTH(pic_width)	REG_FIELD_PREP(DSC_PIC_WIDTH_MASK, pic_width)
+#define  DSC_PIC_HEIGHT(pic_height)	REG_FIELD_PREP(DSC_PIC_HEIGHT_MASK, pic_height)
 
 #define DSCA_PICTURE_PARAMETER_SET_3		_MMIO(0x6B20C)
 #define DSCC_PICTURE_PARAMETER_SET_3		_MMIO(0x6BA0C)
@@ -138,8 +143,10 @@
 #define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
-#define  DSC_SLICE_WIDTH(slice_width)   ((slice_width) << 16)
-#define  DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
+#define  DSC_SLICE_WIDTH_MASK			REG_GENMASK(31, 16)
+#define  DSC_SLICE_HEIGHT_MASK			REG_GENMASK(15, 0)
+#define  DSC_SLICE_WIDTH(slice_width)		REG_FIELD_PREP(DSC_SLICE_WIDTH_MASK, slice_width)
+#define  DSC_SLICE_HEIGHT(slice_height)		REG_FIELD_PREP(DSC_SLICE_HEIGHT_MASK, slice_height)
 
 #define DSCA_PICTURE_PARAMETER_SET_4		_MMIO(0x6B210)
 #define DSCC_PICTURE_PARAMETER_SET_4		_MMIO(0x6BA10)
@@ -153,8 +160,12 @@
 #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
-#define  DSC_INITIAL_DEC_DELAY(dec_delay)       ((dec_delay) << 16)
-#define  DSC_INITIAL_XMIT_DELAY(xmit_delay)     ((xmit_delay) << 0)
+#define  DSC_INITIAL_DEC_DELAY_MASK		REG_GENMASK(31, 16)
+#define  DSC_INITIAL_XMIT_DELAY_MASK		REG_GENMASK(9, 0)
+#define  DSC_INITIAL_DEC_DELAY(dec_delay)       REG_FIELD_PREP(DSC_INITIAL_DEC_DELAY_MASK, \
+							       dec_delay)
+#define  DSC_INITIAL_XMIT_DELAY(xmit_delay)     REG_FIELD_PREP(DSC_INITIAL_XMIT_DELAY_MASK, \
+							       xmit_delay)
 
 #define DSCA_PICTURE_PARAMETER_SET_5		_MMIO(0x6B214)
 #define DSCC_PICTURE_PARAMETER_SET_5		_MMIO(0x6BA14)
@@ -168,8 +179,10 @@
 #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
-#define  DSC_SCALE_DEC_INT(scale_dec)	((scale_dec) << 16)
-#define  DSC_SCALE_INC_INT(scale_inc)		((scale_inc) << 0)
+#define  DSC_SCALE_DEC_INT_MASK			REG_GENMASK(27, 16)
+#define  DSC_SCALE_INC_INT_MASK			REG_GENMASK(15, 0)
+#define  DSC_SCALE_DEC_INT(scale_dec)		REG_FIELD_PREP(DSC_SCALE_DEC_INT_MASK, scale_dec)
+#define  DSC_SCALE_INC_INT(scale_inc)		REG_FIELD_PREP(DSC_SCALE_INC_INT_MASK, scale_inc)
 
 #define DSCA_PICTURE_PARAMETER_SET_6		_MMIO(0x6B218)
 #define DSCC_PICTURE_PARAMETER_SET_6		_MMIO(0x6BA18)
@@ -183,10 +196,16 @@
 #define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
-#define  DSC_FLATNESS_MAX_QP(max_qp)		((max_qp) << 24)
-#define  DSC_FLATNESS_MIN_QP(min_qp)		((min_qp) << 16)
-#define  DSC_FIRST_LINE_BPG_OFFSET(offset)	((offset) << 8)
-#define  DSC_INITIAL_SCALE_VALUE(value)		((value) << 0)
+#define  DSC_FLATNESS_MAX_QP_MASK		REG_GENMASK(28, 24)
+#define  DSC_FLATNESS_MIN_QP_MASK		REG_GENMASK(20, 16)
+#define  DSC_FIRST_LINE_BPG_OFFSET_MASK		REG_GENMASK(12, 8)
+#define  DSC_INITIAL_SCALE_VALUE_MASK		REG_GENMASK(5, 0)
+#define  DSC_FLATNESS_MAX_QP(max_qp)		REG_FIELD_PREP(DSC_FLATNESS_MAX_QP_MASK, max_qp)
+#define  DSC_FLATNESS_MIN_QP(min_qp)		REG_FIELD_PREP(DSC_FLATNESS_MIN_QP_MASK, min_qp)
+#define  DSC_FIRST_LINE_BPG_OFFSET(offset)	REG_FIELD_PREP(DSC_FIRST_LINE_BPG_OFFSET_MASK, \
+							       offset)
+#define  DSC_INITIAL_SCALE_VALUE(value)		REG_FIELD_PREP(DSC_INITIAL_SCALE_VALUE_MASK, \
+							       value)
 
 #define DSCA_PICTURE_PARAMETER_SET_7		_MMIO(0x6B21C)
 #define DSCC_PICTURE_PARAMETER_SET_7		_MMIO(0x6BA1C)
@@ -200,8 +219,11 @@
 #define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							    _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
 							    _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
-#define  DSC_NFL_BPG_OFFSET(bpg_offset)		((bpg_offset) << 16)
-#define  DSC_SLICE_BPG_OFFSET(bpg_offset)	((bpg_offset) << 0)
+#define  DSC_NFL_BPG_OFFSET_MASK		REG_GENMASK(31, 16)
+#define  DSC_SLICE_BPG_OFFSET_MASK		REG_GENMASK(15, 0)
+#define  DSC_NFL_BPG_OFFSET(bpg_offset)		REG_FIELD_PREP(DSC_NFL_BPG_OFFSET_MASK, bpg_offset)
+#define  DSC_SLICE_BPG_OFFSET(bpg_offset)	REG_FIELD_PREP(DSC_SLICE_BPG_OFFSET_MASK, \
+							       bpg_offset)
 
 #define DSCA_PICTURE_PARAMETER_SET_8		_MMIO(0x6B220)
 #define DSCC_PICTURE_PARAMETER_SET_8		_MMIO(0x6BA20)
@@ -215,8 +237,12 @@
 #define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
-#define  DSC_INITIAL_OFFSET(initial_offset)		((initial_offset) << 16)
-#define  DSC_FINAL_OFFSET(final_offset)			((final_offset) << 0)
+#define  DSC_INITIAL_OFFSET_MASK		REG_GENMASK(31, 16)
+#define  DSC_FINAL_OFFSET_MASK			REG_GENMASK(15, 0)
+#define  DSC_INITIAL_OFFSET(initial_offset)	REG_FIELD_PREP(DSC_INITIAL_OFFSET_MASK, \
+							       initial_offset)
+#define  DSC_FINAL_OFFSET(final_offset)		REG_FIELD_PREP(DSC_FINAL_OFFSET_MASK, \
+							       final_offset)
 
 #define DSCA_PICTURE_PARAMETER_SET_9		_MMIO(0x6B224)
 #define DSCC_PICTURE_PARAMETER_SET_9		_MMIO(0x6BA24)
@@ -230,8 +256,12 @@
 #define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
-#define  DSC_RC_EDGE_FACTOR(rc_edge_fact)	((rc_edge_fact) << 16)
-#define  DSC_RC_MODEL_SIZE(rc_model_size)	((rc_model_size) << 0)
+#define  DSC_RC_EDGE_FACTOR_MASK		REG_GENMASK(19, 16)
+#define  DSC_RC_MODEL_SIZE_MASK			REG_GENMASK(15, 0)
+#define  DSC_RC_EDGE_FACTOR(rc_edge_fact)	REG_FIELD_PREP(DSC_RC_EDGE_FACTOR_MASK, \
+							       rc_edge_fact)
+#define  DSC_RC_MODEL_SIZE(rc_model_size)	REG_FIELD_PREP(DSC_RC_MODEL_SIZE_MASK, \
+							       rc_model_size)
 
 #define DSCA_PICTURE_PARAMETER_SET_10		_MMIO(0x6B228)
 #define DSCC_PICTURE_PARAMETER_SET_10		_MMIO(0x6BA28)
@@ -245,10 +275,16 @@
 #define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
-#define  DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low)		((rc_tgt_off_low) << 20)
-#define  DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high)	((rc_tgt_off_high) << 16)
-#define  DSC_RC_QUANT_INC_LIMIT1(lim)			((lim) << 8)
-#define  DSC_RC_QUANT_INC_LIMIT0(lim)			((lim) << 0)
+#define  DSC_RC_TGT_OFF_LOW_MASK			REG_GENMASK(23, 20)
+#define  DSC_RC_TGT_OFF_HIGH_MASK			REG_GENMASK(19, 16)
+#define  DSC_RC_QUANT_INC_LIMIT1_MASK			REG_GENMASK(12, 8)
+#define  DSC_RC_QUANT_INC_LIMIT0_MASK			REG_GENMASK(4, 0)
+#define  DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low)		REG_FIELD_PREP(DSC_RC_TGT_OFF_LOW_MASK, \
+								       rc_tgt_off_low)
+#define  DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high)	REG_FIELD_PREP(DSC_RC_TGT_OFF_HIGH_MASK, \
+								       rc_tgt_off_high)
+#define  DSC_RC_QUANT_INC_LIMIT1(lim)		REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT1_MASK, lim)
+#define  DSC_RC_QUANT_INC_LIMIT0(lim)		REG_FIELD_PREP(DSC_RC_QUANT_INC_LIMIT0_MASK, lim)
 
 #define DSCA_PICTURE_PARAMETER_SET_11		_MMIO(0x6B22C)
 #define DSCC_PICTURE_PARAMETER_SET_11		_MMIO(0x6BA2C)
@@ -327,9 +363,15 @@
 #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe)	_MMIO_PIPE((pipe) - PIPE_B, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
 							   _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
-#define  DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame)	((slice_row_per_frame) << 20)
-#define  DSC_SLICE_PER_LINE(slice_per_line)		((slice_per_line) << 16)
-#define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		((slice_chunk_size) << 0)
+#define  DSC_SLICE_ROW_PR_FRME_MASK			REG_GENMASK(31, 20)
+#define  DSC_SLICE_PER_LINE_MASK			REG_GENMASK(18, 16)
+#define  DSC_SLICE_CHUNK_SIZE_MASK			REG_GENMASK(15, 0)
+#define  DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame)	REG_FIELD_PREP(DSC_SLICE_ROW_PR_FRME_MASK, \
+								       slice_row_per_frame)
+#define  DSC_SLICE_PER_LINE(slice_per_line)		REG_FIELD_PREP(DSC_SLICE_PER_LINE_MASK, \
+								       slice_per_line)
+#define  DSC_SLICE_CHUNK_SIZE(slice_chunk_size)		REG_FIELD_PREP(DSC_SLICE_CHUNK_SIZE_MASK, \
+								       slice_chunk_size)
 
 /* Icelake Rate Control Buffer Threshold Registers */
 #define DSCA_RC_BUF_THRESH_0			_MMIO(0x6B230)
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [Intel-gfx] [PATCH v3 2/7] drm/i915/vdsc: Add a check for dsc split cases
  2023-07-17 10:09 [Intel-gfx] [PATCH v3 0/7] Add DSC PPS readout Suraj Kandpal
  2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 1/7] drm/i915/vdsc: Refactor dsc register field macro Suraj Kandpal
@ 2023-07-17 10:09 ` Suraj Kandpal
  2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 3/7] drm/i915/vdsc: Add function to read any PPS register Suraj Kandpal
                   ` (7 subsequent siblings)
  9 siblings, 0 replies; 13+ messages in thread
From: Suraj Kandpal @ 2023-07-17 10:09 UTC (permalink / raw)
  To: intel-gfx

In intel_vdsc_get_config we only read the primary dsc engine register
and not take into account if the other dsc engine is in use and if
both registers have the same value or not this patche fixes that by
adding a check.

--v3
-Remove superfluos new line [Jani]
-Fix register naming [Jani]

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 14 +++++++++++++-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 530f3c08a172..9196329d998d 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -939,7 +939,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 	enum pipe pipe = crtc->pipe;
 	enum intel_display_power_domain power_domain;
 	intel_wakeref_t wakeref;
-	u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0;
+	u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0 = 0, pps_temp1 = 1;
 
 	if (!intel_dsc_source_support(crtc_state))
 		return;
@@ -965,11 +965,23 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 	/* PPS0 & PPS1 */
 	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
 		pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
+		if (crtc_state->dsc.dsc_split) {
+			pps_temp1 = intel_de_read(dev_priv, DSCC_PICTURE_PARAMETER_SET_1);
+			drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
+		}
 	} else {
 		pps0 = intel_de_read(dev_priv,
 				     ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
 		pps1 = intel_de_read(dev_priv,
 				     ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
+		if (crtc_state->dsc.dsc_split) {
+			pps_temp0 = intel_de_read(dev_priv,
+						  ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe));
+			pps_temp1 = intel_de_read(dev_priv,
+						  ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe));
+			drm_WARN_ON(&dev_priv->drm, pps0 != pps_temp0);
+			drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
+		}
 	}
 
 	vdsc_cfg->bits_per_pixel = pps1;
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [Intel-gfx] [PATCH v3 3/7] drm/i915/vdsc: Add function to read any PPS register
  2023-07-17 10:09 [Intel-gfx] [PATCH v3 0/7] Add DSC PPS readout Suraj Kandpal
  2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 1/7] drm/i915/vdsc: Refactor dsc register field macro Suraj Kandpal
  2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 2/7] drm/i915/vdsc: Add a check for dsc split cases Suraj Kandpal
@ 2023-07-17 10:09 ` Suraj Kandpal
  2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 4/7] drm/i915/vdsc: Use MACRO to cleanup intel_dsc_get_pps_reg Suraj Kandpal
                   ` (6 subsequent siblings)
  9 siblings, 0 replies; 13+ messages in thread
From: Suraj Kandpal @ 2023-07-17 10:09 UTC (permalink / raw)
  To: intel-gfx

Add function to read any PPS register based on the
intel_dsc_pps enum provided. Add a function which will call the
new pps read function and place it in crtc state. Only PPS0 and
PPS1 are readout the rest of the registers will be read in upcoming
patches.

--v2
-Changes in read function as PPS enum is removed
-Initialize pps_val as 0 in pps_read func itself [Jani]
-Create a function that gets the required register and call that
in the common read function [Jani]
-Move the drm_WARN_ON one abstraction layer above [Jani]

--v3
-Send both reg values regardless of dsc engine no [Jani]
-Don't use num_vdsc_instances stick to dsc_split field [Ankit]

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 221 ++++++++++++++++++----
 1 file changed, 188 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 9196329d998d..6d319f351a12 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -303,6 +303,143 @@ int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
 	return num_vdsc_instances;
 }
 
+static void intel_dsc_get_pps_reg(struct intel_crtc_state *crtc_state, int pps,
+				  i915_reg_t *dsc_reg0, i915_reg_t *dsc_reg1)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+	enum pipe pipe = crtc->pipe;
+	bool pipe_dsc;
+
+	pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
+
+	switch (pps) {
+	case 0:
+		if (pipe_dsc) {
+			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe);
+			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe);
+		} else {
+			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_0;
+			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_0;
+		}
+		break;
+	case 1:
+		if (pipe_dsc) {
+			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe);
+			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe);
+		} else {
+			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_1;
+			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_1;
+		}
+		break;
+	case 2:
+		if (pipe_dsc) {
+			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe);
+			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe);
+		} else {
+			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_2;
+			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_2;
+		}
+		break;
+	case 3:
+		if (pipe_dsc) {
+			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe);
+			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe);
+		} else {
+			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_3;
+			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_3;
+		}
+		break;
+	case 4:
+		if (pipe_dsc) {
+			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe);
+			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe);
+		} else {
+			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_4;
+			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_4;
+		}
+		break;
+	case 5:
+		if (pipe_dsc) {
+			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe);
+			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe);
+		} else {
+			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_5;
+			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_5;
+		}
+		break;
+	case 6:
+		if (pipe_dsc) {
+			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe);
+			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe);
+		} else {
+			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_6;
+			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_6;
+		}
+		break;
+	case 7:
+		if (pipe_dsc) {
+			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe);
+			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe);
+		} else {
+			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_7;
+			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_7;
+		}
+		break;
+	case 8:
+		if (pipe_dsc) {
+			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe);
+			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe);
+		} else {
+			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_8;
+			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_8;
+		}
+		break;
+	case 9:
+		if (pipe_dsc) {
+			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe);
+			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe);
+		} else {
+			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_9;
+			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_9;
+		}
+		break;
+	case 10:
+		if (pipe_dsc) {
+			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe);
+			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe);
+		} else {
+			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_10;
+			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_10;
+		}
+		break;
+	case 16:
+		if (pipe_dsc) {
+			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe);
+			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe);
+		} else {
+			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_16;
+			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_16;
+		}
+		break;
+	/*
+	 * Since PPS_17 and PPS_18 were introduced from MTL dsc check
+	 * need not be done
+	 */
+	case 17:
+		*dsc_reg0 = MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe);
+		*dsc_reg1 = MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe);
+		break;
+	case 18:
+		*dsc_reg0 = MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe);
+		*dsc_reg1 = MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe);
+		break;
+	default:
+		MISSING_CASE(pps);
+		break;
+	}
+}
+
 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -930,16 +1067,63 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state)
 	}
 }
 
+static bool intel_dsc_read_pps_reg(struct intel_crtc_state *crtc_state,
+				   int pps, u32 *pps_val)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	bool dsc_split = crtc_state->dsc.dsc_split;
+	i915_reg_t dsc_reg0, dsc_reg1;
+	u32 pps_temp;
+
+	*pps_val = 0;
+
+	intel_dsc_get_pps_reg(crtc_state, pps, &dsc_reg0, &dsc_reg1);
+	*pps_val = intel_de_read(i915, dsc_reg0);
+	if (dsc_split) {
+		pps_temp = intel_de_read(i915, dsc_reg1);
+		if (*pps_val != pps_temp)
+			return false;
+	}
+	return true;
+}
+
+static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state *crtc_state,
+					      int pps, u32 *pps_val)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	bool is_dsc_eq;
+
+	is_dsc_eq = intel_dsc_read_pps_reg(crtc_state, pps, pps_val);
+	drm_WARN_ON(&i915->drm, !is_dsc_eq);
+}
+
+static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
+{
+	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
+	u32 pps_temp1, pps_temp2;
+
+	/* Readout PPS_0 and PPS_1 registers */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp1);
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp2);
+
+	vdsc_cfg->bits_per_pixel = pps_temp2;
+
+	if (pps_temp1 & DSC_NATIVE_420_ENABLE)
+		vdsc_cfg->bits_per_pixel >>= 1;
+
+	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
+}
+
 void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
 	enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
-	enum pipe pipe = crtc->pipe;
 	enum intel_display_power_domain power_domain;
 	intel_wakeref_t wakeref;
-	u32 dss_ctl1, dss_ctl2, pps0 = 0, pps1 = 0, pps_temp0 = 0, pps_temp1 = 1;
+	u32 dss_ctl1, dss_ctl2;
 
 	if (!intel_dsc_source_support(crtc_state))
 		return;
@@ -960,36 +1144,7 @@ void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
 	crtc_state->dsc.dsc_split = (dss_ctl2 & RIGHT_BRANCH_VDSC_ENABLE) &&
 		(dss_ctl1 & JOINER_ENABLE);
 
-	/* FIXME: add more state readout as needed */
-
-	/* PPS0 & PPS1 */
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		pps1 = intel_de_read(dev_priv, DSCA_PICTURE_PARAMETER_SET_1);
-		if (crtc_state->dsc.dsc_split) {
-			pps_temp1 = intel_de_read(dev_priv, DSCC_PICTURE_PARAMETER_SET_1);
-			drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
-		}
-	} else {
-		pps0 = intel_de_read(dev_priv,
-				     ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe));
-		pps1 = intel_de_read(dev_priv,
-				     ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe));
-		if (crtc_state->dsc.dsc_split) {
-			pps_temp0 = intel_de_read(dev_priv,
-						  ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe));
-			pps_temp1 = intel_de_read(dev_priv,
-						  ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe));
-			drm_WARN_ON(&dev_priv->drm, pps0 != pps_temp0);
-			drm_WARN_ON(&dev_priv->drm, pps1 != pps_temp1);
-		}
-	}
-
-	vdsc_cfg->bits_per_pixel = pps1;
-
-	if (pps0 & DSC_NATIVE_420_ENABLE)
-		vdsc_cfg->bits_per_pixel >>= 1;
-
-	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
+	intel_dsc_get_pps_config(crtc_state);
 out:
 	intel_display_power_put(dev_priv, power_domain, wakeref);
 }
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [Intel-gfx] [PATCH v3 4/7] drm/i915/vdsc: Use MACRO to cleanup intel_dsc_get_pps_reg
  2023-07-17 10:09 [Intel-gfx] [PATCH v3 0/7] Add DSC PPS readout Suraj Kandpal
                   ` (2 preceding siblings ...)
  2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 3/7] drm/i915/vdsc: Add function to read any PPS register Suraj Kandpal
@ 2023-07-17 10:09 ` Suraj Kandpal
  2023-07-18  9:24   ` Nautiyal, Ankit K
  2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 5/7] drm/i915/vdsc: Add function to write in PPS register Suraj Kandpal
                   ` (5 subsequent siblings)
  9 siblings, 1 reply; 13+ messages in thread
From: Suraj Kandpal @ 2023-07-17 10:09 UTC (permalink / raw)
  To: intel-gfx

Use a Macro to clean up intel_dsc_get_pps_reg so that we don't have
to replicate so many if/else blocks.

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 124 ++++++----------------
 1 file changed, 32 insertions(+), 92 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 6d319f351a12..ed8fda431226 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -313,131 +313,71 @@ static void intel_dsc_get_pps_reg(struct intel_crtc_state *crtc_state, int pps,
 
 	pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
 
+#define PRE_MTL_GET_DSC_REGISTER(pps, is_pipe_dsc, pipe) do { \
+	if (is_pipe_dsc) { \
+		*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_##pps(pipe); \
+		*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_##pps(pipe); \
+	} else { \
+		*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_##pps; \
+		*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_##pps; \
+	} \
+} while (0)
+
+#define MTL_GET_DSC_REGISTER(pps, pipe) do { \
+		*dsc_reg0 = MTL_DSC0_PICTURE_PARAMETER_SET_##pps(pipe); \
+		*dsc_reg1 = MTL_DSC1_PICTURE_PARAMETER_SET_##pps(pipe); \
+} while (0)
+
 	switch (pps) {
 	case 0:
-		if (pipe_dsc) {
-			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe);
-			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe);
-		} else {
-			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_0;
-			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_0;
-		}
+		PRE_MTL_GET_DSC_REGISTER(0, pipe_dsc, pipe);
 		break;
 	case 1:
-		if (pipe_dsc) {
-			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe);
-			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe);
-		} else {
-			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_1;
-			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_1;
-		}
+		PRE_MTL_GET_DSC_REGISTER(1, pipe_dsc, pipe);
 		break;
 	case 2:
-		if (pipe_dsc) {
-			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe);
-			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe);
-		} else {
-			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_2;
-			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_2;
-		}
+		PRE_MTL_GET_DSC_REGISTER(2, pipe_dsc, pipe);
 		break;
 	case 3:
-		if (pipe_dsc) {
-			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe);
-			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe);
-		} else {
-			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_3;
-			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_3;
-		}
+		PRE_MTL_GET_DSC_REGISTER(3, pipe_dsc, pipe);
 		break;
 	case 4:
-		if (pipe_dsc) {
-			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe);
-			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe);
-		} else {
-			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_4;
-			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_4;
-		}
+		PRE_MTL_GET_DSC_REGISTER(4, pipe_dsc, pipe);
 		break;
 	case 5:
-		if (pipe_dsc) {
-			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe);
-			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe);
-		} else {
-			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_5;
-			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_5;
-		}
+		PRE_MTL_GET_DSC_REGISTER(5, pipe_dsc, pipe);
 		break;
 	case 6:
-		if (pipe_dsc) {
-			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe);
-			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe);
-		} else {
-			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_6;
-			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_6;
-		}
+		PRE_MTL_GET_DSC_REGISTER(6, pipe_dsc, pipe);
 		break;
 	case 7:
-		if (pipe_dsc) {
-			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe);
-			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe);
-		} else {
-			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_7;
-			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_7;
-		}
+		PRE_MTL_GET_DSC_REGISTER(7, pipe_dsc, pipe);
 		break;
 	case 8:
-		if (pipe_dsc) {
-			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe);
-			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe);
-		} else {
-			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_8;
-			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_8;
-		}
+		PRE_MTL_GET_DSC_REGISTER(8, pipe_dsc, pipe);
 		break;
 	case 9:
-		if (pipe_dsc) {
-			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe);
-			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe);
-		} else {
-			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_9;
-			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_9;
-		}
+		PRE_MTL_GET_DSC_REGISTER(9, pipe_dsc, pipe);
 		break;
 	case 10:
-		if (pipe_dsc) {
-			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe);
-			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe);
-		} else {
-			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_10;
-			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_10;
-		}
+		PRE_MTL_GET_DSC_REGISTER(10, pipe_dsc, pipe);
 		break;
 	case 16:
-		if (pipe_dsc) {
-			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe);
-			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe);
-		} else {
-			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_16;
-			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_16;
-		}
+		PRE_MTL_GET_DSC_REGISTER(16, pipe_dsc, pipe);
 		break;
-	/*
-	 * Since PPS_17 and PPS_18 were introduced from MTL dsc check
-	 * need not be done
-	 */
 	case 17:
-		*dsc_reg0 = MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe);
-		*dsc_reg1 = MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe);
+		MTL_GET_DSC_REGISTER(17, pipe);
 		break;
 	case 18:
-		*dsc_reg0 = MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe);
-		*dsc_reg1 = MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe);
+		MTL_GET_DSC_REGISTER(18, pipe);
 		break;
 	default:
 		MISSING_CASE(pps);
 		break;
 	}
+
+#undef PRE_MTL_GET_DSC_REGISTER
+#undef MTL_GET_DSC_REGISTER
 }
 
 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 13+ messages in thread

* Re: [Intel-gfx] [PATCH v3 4/7] drm/i915/vdsc: Use MACRO to cleanup intel_dsc_get_pps_reg
  2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 4/7] drm/i915/vdsc: Use MACRO to cleanup intel_dsc_get_pps_reg Suraj Kandpal
@ 2023-07-18  9:24   ` Nautiyal, Ankit K
  2023-07-18  9:43     ` Nautiyal, Ankit K
  0 siblings, 1 reply; 13+ messages in thread
From: Nautiyal, Ankit K @ 2023-07-18  9:24 UTC (permalink / raw)
  To: Kandpal, Suraj, intel-gfx@lists.freedesktop.org


On 7/17/2023 3:39 PM, Suraj Kandpal wrote:
> Use a Macro to clean up intel_dsc_get_pps_reg so that we don't have
> to replicate so many if/else blocks.
>
> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_vdsc.c | 124 ++++++----------------
>   1 file changed, 32 insertions(+), 92 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 6d319f351a12..ed8fda431226 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -313,131 +313,71 @@ static void intel_dsc_get_pps_reg(struct intel_crtc_state *crtc_state, int pps,
>   
>   	pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
>   
> +#define PRE_MTL_GET_DSC_REGISTER(pps, is_pipe_dsc, pipe) do { \
> +	if (is_pipe_dsc) { \
> +		*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_##pps(pipe); \
> +		*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_##pps(pipe); \
> +	} else { \
> +		*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_##pps; \
> +		*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_##pps; \

I think it will be more efficient to add an enum intel_dsc_engine and 
have a function that returns the reg for given, pps, engine and pipe.

something like:

static i915_reg_t intel_dsc_get_pps_reg(const struct intel_crtc_state 
*crtc_state, int pps, enum vdsc_engine vdsc)

Since offsets are regularly placed, we can have something like : 
ICL_DSC_PICTURE_PARAMETER_SET(engine, pps, pipe) and

DSC_PICTURE_PARAMETER_SET(engine, pps) for ICL EDP/DSI case.

Roughly it will be Offset of PPS Reg for Engine 0 + engine * 0x800 + pps 
* 4.

Though this will require quite some changes in reg macros in 
intel_vdsc_reg.h ,and also need to have a new enum for intel_dsc_engine,

but IMHO it will be easier to get the required PPS reg this way.

Regards,

Ankit


> +	} \
> +} while (0)
> +
> +#define MTL_GET_DSC_REGISTER(pps, pipe) do { \
> +		*dsc_reg0 = MTL_DSC0_PICTURE_PARAMETER_SET_##pps(pipe); \
> +		*dsc_reg1 = MTL_DSC1_PICTURE_PARAMETER_SET_##pps(pipe); \
> +} while (0)
> +
>   	switch (pps) {
>   	case 0:
> -		if (pipe_dsc) {
> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe);
> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe);
> -		} else {
> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_0;
> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_0;
> -		}
> +		PRE_MTL_GET_DSC_REGISTER(0, pipe_dsc, pipe);
>   		break;
>   	case 1:
> -		if (pipe_dsc) {
> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe);
> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe);
> -		} else {
> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_1;
> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_1;
> -		}
> +		PRE_MTL_GET_DSC_REGISTER(1, pipe_dsc, pipe);
>   		break;
>   	case 2:
> -		if (pipe_dsc) {
> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe);
> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe);
> -		} else {
> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_2;
> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_2;
> -		}
> +		PRE_MTL_GET_DSC_REGISTER(2, pipe_dsc, pipe);
>   		break;
>   	case 3:
> -		if (pipe_dsc) {
> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe);
> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe);
> -		} else {
> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_3;
> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_3;
> -		}
> +		PRE_MTL_GET_DSC_REGISTER(3, pipe_dsc, pipe);
>   		break;
>   	case 4:
> -		if (pipe_dsc) {
> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe);
> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe);
> -		} else {
> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_4;
> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_4;
> -		}
> +		PRE_MTL_GET_DSC_REGISTER(4, pipe_dsc, pipe);
>   		break;
>   	case 5:
> -		if (pipe_dsc) {
> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe);
> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe);
> -		} else {
> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_5;
> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_5;
> -		}
> +		PRE_MTL_GET_DSC_REGISTER(5, pipe_dsc, pipe);
>   		break;
>   	case 6:
> -		if (pipe_dsc) {
> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe);
> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe);
> -		} else {
> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_6;
> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_6;
> -		}
> +		PRE_MTL_GET_DSC_REGISTER(6, pipe_dsc, pipe);
>   		break;
>   	case 7:
> -		if (pipe_dsc) {
> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe);
> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe);
> -		} else {
> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_7;
> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_7;
> -		}
> +		PRE_MTL_GET_DSC_REGISTER(7, pipe_dsc, pipe);
>   		break;
>   	case 8:
> -		if (pipe_dsc) {
> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe);
> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe);
> -		} else {
> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_8;
> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_8;
> -		}
> +		PRE_MTL_GET_DSC_REGISTER(8, pipe_dsc, pipe);
>   		break;
>   	case 9:
> -		if (pipe_dsc) {
> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe);
> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe);
> -		} else {
> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_9;
> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_9;
> -		}
> +		PRE_MTL_GET_DSC_REGISTER(9, pipe_dsc, pipe);
>   		break;
>   	case 10:
> -		if (pipe_dsc) {
> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe);
> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe);
> -		} else {
> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_10;
> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_10;
> -		}
> +		PRE_MTL_GET_DSC_REGISTER(10, pipe_dsc, pipe);
>   		break;
>   	case 16:
> -		if (pipe_dsc) {
> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe);
> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe);
> -		} else {
> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_16;
> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_16;
> -		}
> +		PRE_MTL_GET_DSC_REGISTER(16, pipe_dsc, pipe);
>   		break;
> -	/*
> -	 * Since PPS_17 and PPS_18 were introduced from MTL dsc check
> -	 * need not be done
> -	 */
>   	case 17:
> -		*dsc_reg0 = MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe);
> -		*dsc_reg1 = MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe);
> +		MTL_GET_DSC_REGISTER(17, pipe);
>   		break;
>   	case 18:
> -		*dsc_reg0 = MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe);
> -		*dsc_reg1 = MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe);
> +		MTL_GET_DSC_REGISTER(18, pipe);
>   		break;
>   	default:
>   		MISSING_CASE(pps);
>   		break;
>   	}
> +
> +#undef PRE_MTL_GET_DSC_REGISTER
> +#undef MTL_GET_DSC_REGISTER
>   }
>   
>   static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [Intel-gfx] [PATCH v3 4/7] drm/i915/vdsc: Use MACRO to cleanup intel_dsc_get_pps_reg
  2023-07-18  9:24   ` Nautiyal, Ankit K
@ 2023-07-18  9:43     ` Nautiyal, Ankit K
  0 siblings, 0 replies; 13+ messages in thread
From: Nautiyal, Ankit K @ 2023-07-18  9:43 UTC (permalink / raw)
  To: Kandpal, Suraj, intel-gfx@lists.freedesktop.org


On 7/18/2023 2:54 PM, Nautiyal, Ankit K wrote:
> On 7/17/2023 3:39 PM, Suraj Kandpal wrote:
>> Use a Macro to clean up intel_dsc_get_pps_reg so that we don't have
>> to replicate so many if/else blocks.
>>
>> Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
>> ---
>>    drivers/gpu/drm/i915/display/intel_vdsc.c | 124 ++++++----------------
>>    1 file changed, 32 insertions(+), 92 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> index 6d319f351a12..ed8fda431226 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
>> @@ -313,131 +313,71 @@ static void intel_dsc_get_pps_reg(struct intel_crtc_state *crtc_state, int pps,
>>    
>>    	pipe_dsc = is_pipe_dsc(crtc, cpu_transcoder);
>>    
>> +#define PRE_MTL_GET_DSC_REGISTER(pps, is_pipe_dsc, pipe) do { \
>> +	if (is_pipe_dsc) { \
>> +		*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_##pps(pipe); \
>> +		*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_##pps(pipe); \
>> +	} else { \
>> +		*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_##pps; \
>> +		*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_##pps; \
> I think it will be more efficient to add an enum intel_dsc_engine and
> have a function that returns the reg for given, pps, engine and pipe.
>
> something like:
>
> static i915_reg_t intel_dsc_get_pps_reg(const struct intel_crtc_state
> *crtc_state, int pps, enum vdsc_engine vdsc)
>
> Since offsets are regularly placed, we can have something like :
> ICL_DSC_PICTURE_PARAMETER_SET(engine, pps, pipe) and
>
> DSC_PICTURE_PARAMETER_SET(engine, pps) for ICL EDP/DSI case.
>
> Roughly it will be Offset of PPS Reg for Engine 0 + engine * 0x800 + pps
> * 4.

Sorry this is incorrect example. Need to get the difference, for engine 
and pps to calculate the offset correctly.


Regards,

Ankit


>
> Though this will require quite some changes in reg macros in
> intel_vdsc_reg.h ,and also need to have a new enum for intel_dsc_engine,
>
> but IMHO it will be easier to get the required PPS reg this way.
>
> Regards,
>
> Ankit
>
>
>> +	} \
>> +} while (0)
>> +
>> +#define MTL_GET_DSC_REGISTER(pps, pipe) do { \
>> +		*dsc_reg0 = MTL_DSC0_PICTURE_PARAMETER_SET_##pps(pipe); \
>> +		*dsc_reg1 = MTL_DSC1_PICTURE_PARAMETER_SET_##pps(pipe); \
>> +} while (0)
>> +
>>    	switch (pps) {
>>    	case 0:
>> -		if (pipe_dsc) {
>> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe);
>> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe);
>> -		} else {
>> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_0;
>> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_0;
>> -		}
>> +		PRE_MTL_GET_DSC_REGISTER(0, pipe_dsc, pipe);
>>    		break;
>>    	case 1:
>> -		if (pipe_dsc) {
>> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe);
>> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe);
>> -		} else {
>> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_1;
>> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_1;
>> -		}
>> +		PRE_MTL_GET_DSC_REGISTER(1, pipe_dsc, pipe);
>>    		break;
>>    	case 2:
>> -		if (pipe_dsc) {
>> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe);
>> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe);
>> -		} else {
>> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_2;
>> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_2;
>> -		}
>> +		PRE_MTL_GET_DSC_REGISTER(2, pipe_dsc, pipe);
>>    		break;
>>    	case 3:
>> -		if (pipe_dsc) {
>> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe);
>> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe);
>> -		} else {
>> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_3;
>> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_3;
>> -		}
>> +		PRE_MTL_GET_DSC_REGISTER(3, pipe_dsc, pipe);
>>    		break;
>>    	case 4:
>> -		if (pipe_dsc) {
>> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe);
>> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe);
>> -		} else {
>> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_4;
>> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_4;
>> -		}
>> +		PRE_MTL_GET_DSC_REGISTER(4, pipe_dsc, pipe);
>>    		break;
>>    	case 5:
>> -		if (pipe_dsc) {
>> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe);
>> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe);
>> -		} else {
>> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_5;
>> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_5;
>> -		}
>> +		PRE_MTL_GET_DSC_REGISTER(5, pipe_dsc, pipe);
>>    		break;
>>    	case 6:
>> -		if (pipe_dsc) {
>> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe);
>> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe);
>> -		} else {
>> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_6;
>> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_6;
>> -		}
>> +		PRE_MTL_GET_DSC_REGISTER(6, pipe_dsc, pipe);
>>    		break;
>>    	case 7:
>> -		if (pipe_dsc) {
>> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe);
>> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe);
>> -		} else {
>> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_7;
>> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_7;
>> -		}
>> +		PRE_MTL_GET_DSC_REGISTER(7, pipe_dsc, pipe);
>>    		break;
>>    	case 8:
>> -		if (pipe_dsc) {
>> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe);
>> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe);
>> -		} else {
>> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_8;
>> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_8;
>> -		}
>> +		PRE_MTL_GET_DSC_REGISTER(8, pipe_dsc, pipe);
>>    		break;
>>    	case 9:
>> -		if (pipe_dsc) {
>> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe);
>> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe);
>> -		} else {
>> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_9;
>> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_9;
>> -		}
>> +		PRE_MTL_GET_DSC_REGISTER(9, pipe_dsc, pipe);
>>    		break;
>>    	case 10:
>> -		if (pipe_dsc) {
>> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe);
>> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe);
>> -		} else {
>> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_10;
>> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_10;
>> -		}
>> +		PRE_MTL_GET_DSC_REGISTER(10, pipe_dsc, pipe);
>>    		break;
>>    	case 16:
>> -		if (pipe_dsc) {
>> -			*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe);
>> -			*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe);
>> -		} else {
>> -			*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_16;
>> -			*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_16;
>> -		}
>> +		PRE_MTL_GET_DSC_REGISTER(16, pipe_dsc, pipe);
>>    		break;
>> -	/*
>> -	 * Since PPS_17 and PPS_18 were introduced from MTL dsc check
>> -	 * need not be done
>> -	 */
>>    	case 17:
>> -		*dsc_reg0 = MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe);
>> -		*dsc_reg1 = MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe);
>> +		MTL_GET_DSC_REGISTER(17, pipe);
>>    		break;
>>    	case 18:
>> -		*dsc_reg0 = MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe);
>> -		*dsc_reg1 = MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe);
>> +		MTL_GET_DSC_REGISTER(18, pipe);
>>    		break;
>>    	default:
>>    		MISSING_CASE(pps);
>>    		break;
>>    	}
>> +
>> +#undef PRE_MTL_GET_DSC_REGISTER
>> +#undef MTL_GET_DSC_REGISTER
>>    }
>>    
>>    static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)

^ permalink raw reply	[flat|nested] 13+ messages in thread

* [Intel-gfx] [PATCH v3 5/7] drm/i915/vdsc: Add function to write in PPS register
  2023-07-17 10:09 [Intel-gfx] [PATCH v3 0/7] Add DSC PPS readout Suraj Kandpal
                   ` (3 preceding siblings ...)
  2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 4/7] drm/i915/vdsc: Use MACRO to cleanup intel_dsc_get_pps_reg Suraj Kandpal
@ 2023-07-17 10:09 ` Suraj Kandpal
  2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 6/7] drm/i915/vdsc: Fill the intel_dsc_get_pps_config function Suraj Kandpal
                   ` (4 subsequent siblings)
  9 siblings, 0 replies; 13+ messages in thread
From: Suraj Kandpal @ 2023-07-17 10:09 UTC (permalink / raw)
  To: intel-gfx

Now that we have a function that reads any PPS register based
on intel_dsc_pps enum provided lets create a function that can
write on any PPS.

--v2
-Changes need as PPS enum was dropped
-Remove duplicated code in intel_dsc_write_pps_reg [Jani]

--v3
-Use dsc_split instead of num_vdsc_instances [Ankit]

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 272 +++-------------------
 1 file changed, 29 insertions(+), 243 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index ed8fda431226..2f0362241059 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -303,7 +303,7 @@ int intel_dsc_get_num_vdsc_instances(const struct intel_crtc_state *crtc_state)
 	return num_vdsc_instances;
 }
 
-static void intel_dsc_get_pps_reg(struct intel_crtc_state *crtc_state, int pps,
+static void intel_dsc_get_pps_reg(const struct intel_crtc_state *crtc_state, int pps,
 				  i915_reg_t *dsc_reg0, i915_reg_t *dsc_reg1)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -380,6 +380,20 @@ static void intel_dsc_get_pps_reg(struct intel_crtc_state *crtc_state, int pps,
 #undef MTL_GET_DSC_REGISTER
 }
 
+static void intel_dsc_write_pps_reg(const struct intel_crtc_state *crtc_state,
+				    int pps, u32 pps_val)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	i915_reg_t dsc_reg0, dsc_reg1;
+
+	intel_dsc_get_pps_reg(crtc_state, pps, &dsc_reg0, &dsc_reg1);
+	intel_de_write(i915, dsc_reg0, pps_val);
+	if (crtc_state->dsc.dsc_split) {
+		intel_de_write(i915, dsc_reg1, pps_val);
+	}
+}
+
 static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -414,149 +428,41 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 	if (vdsc_cfg->vbr_enable)
 		pps_val |= DSC_VBR_ENABLE;
 	drm_dbg_kms(&dev_priv->drm, "PPS0 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_0,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_0,
-				       pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe),
-			       pps_val);
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe),
-				       pps_val);
-	}
+	intel_dsc_write_pps_reg(crtc_state, 0, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_1 registers */
 	pps_val = 0;
 	pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel);
 	drm_dbg_kms(&dev_priv->drm, "PPS1 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_1,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_1,
-				       pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe),
-			       pps_val);
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe),
-				       pps_val);
-	}
+	intel_dsc_write_pps_reg(crtc_state, 1, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_2 registers */
 	pps_val = 0;
 	pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) |
 		DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances);
 	drm_dbg_kms(&dev_priv->drm, "PPS2 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_2,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_2,
-				       pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe),
-			       pps_val);
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe),
-				       pps_val);
-	}
+	intel_dsc_write_pps_reg(crtc_state, 2, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_3 registers */
 	pps_val = 0;
 	pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) |
 		DSC_SLICE_WIDTH(vdsc_cfg->slice_width);
 	drm_dbg_kms(&dev_priv->drm, "PPS3 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_3,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_3,
-				       pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe),
-			       pps_val);
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe),
-				       pps_val);
-	}
+	intel_dsc_write_pps_reg(crtc_state, 3, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_4 registers */
 	pps_val = 0;
 	pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) |
 		DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay);
 	drm_dbg_kms(&dev_priv->drm, "PPS4 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_4,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_4,
-				       pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe),
-			       pps_val);
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe),
-				       pps_val);
-	}
+	intel_dsc_write_pps_reg(crtc_state, 4, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_5 registers */
 	pps_val = 0;
 	pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) |
 		DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval);
 	drm_dbg_kms(&dev_priv->drm, "PPS5 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_5,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_5,
-				       pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe),
-			       pps_val);
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe),
-				       pps_val);
-	}
+	intel_dsc_write_pps_reg(crtc_state, 5, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_6 registers */
 	pps_val = 0;
@@ -565,100 +471,28 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) |
 		DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp);
 	drm_dbg_kms(&dev_priv->drm, "PPS6 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_6,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_6,
-				       pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe),
-			       pps_val);
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe),
-				       pps_val);
-	}
+	intel_dsc_write_pps_reg(crtc_state, 6, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_7 registers */
 	pps_val = 0;
 	pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) |
 		DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset);
 	drm_dbg_kms(&dev_priv->drm, "PPS7 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_7,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_7,
-				       pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe),
-			       pps_val);
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe),
-				       pps_val);
-	}
+	intel_dsc_write_pps_reg(crtc_state, 7, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_8 registers */
 	pps_val = 0;
 	pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) |
 		DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset);
 	drm_dbg_kms(&dev_priv->drm, "PPS8 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_8,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_8,
-				       pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe),
-			       pps_val);
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe),
-				       pps_val);
-	}
+	intel_dsc_write_pps_reg(crtc_state, 8, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_9 registers */
 	pps_val = 0;
 	pps_val |= DSC_RC_MODEL_SIZE(vdsc_cfg->rc_model_size) |
 		DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST);
 	drm_dbg_kms(&dev_priv->drm, "PPS9 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_9,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv, DSCC_PICTURE_PARAMETER_SET_9,
-				       pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe),
-			       pps_val);
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe),
-				       pps_val);
-	}
+	intel_dsc_write_pps_reg(crtc_state, 9, pps_val);
 
 	/* Populate PICTURE_PARAMETER_SET_10 registers */
 	pps_val = 0;
@@ -667,25 +501,7 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) |
 		DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST);
 	drm_dbg_kms(&dev_priv->drm, "PPS10 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_10,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv,
-				       DSCC_PICTURE_PARAMETER_SET_10, pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe),
-			       pps_val);
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe),
-				       pps_val);
-	}
+	intel_dsc_write_pps_reg(crtc_state, 10, pps_val);
 
 	/* Populate Picture parameter set 16 */
 	pps_val = 0;
@@ -695,51 +511,21 @@ static void intel_dsc_pps_configure(const struct intel_crtc_state *crtc_state)
 		DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height /
 					vdsc_cfg->slice_height);
 	drm_dbg_kms(&dev_priv->drm, "PPS16 = 0x%08x\n", pps_val);
-	if (!is_pipe_dsc(crtc, cpu_transcoder)) {
-		intel_de_write(dev_priv, DSCA_PICTURE_PARAMETER_SET_16,
-			       pps_val);
-		/*
-		 * If 2 VDSC instances are needed, configure PPS for second
-		 * VDSC
-		 */
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv,
-				       DSCC_PICTURE_PARAMETER_SET_16, pps_val);
-	} else {
-		intel_de_write(dev_priv,
-			       ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe),
-			       pps_val);
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv,
-				       ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe),
-				       pps_val);
-	}
+	intel_dsc_write_pps_reg(crtc_state, 16, pps_val);
 
 	if (DISPLAY_VER(dev_priv) >= 14) {
 		/* Populate PICTURE_PARAMETER_SET_17 registers */
 		pps_val = 0;
 		pps_val |= DSC_SL_BPG_OFFSET(vdsc_cfg->second_line_bpg_offset);
 		drm_dbg_kms(&dev_priv->drm, "PPS17 = 0x%08x\n", pps_val);
-		intel_de_write(dev_priv,
-			       MTL_DSC0_PICTURE_PARAMETER_SET_17(pipe),
-			       pps_val);
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv,
-				       MTL_DSC1_PICTURE_PARAMETER_SET_17(pipe),
-				       pps_val);
+		intel_dsc_write_pps_reg(crtc_state, 17, pps_val);
 
 		/* Populate PICTURE_PARAMETER_SET_18 registers */
 		pps_val = 0;
 		pps_val |= DSC_NSL_BPG_OFFSET(vdsc_cfg->nsl_bpg_offset) |
 			   DSC_SL_OFFSET_ADJ(vdsc_cfg->second_line_offset_adj);
 		drm_dbg_kms(&dev_priv->drm, "PPS18 = 0x%08x\n", pps_val);
-		intel_de_write(dev_priv,
-			       MTL_DSC0_PICTURE_PARAMETER_SET_18(pipe),
-			       pps_val);
-		if (crtc_state->dsc.dsc_split)
-			intel_de_write(dev_priv,
-				       MTL_DSC1_PICTURE_PARAMETER_SET_18(pipe),
-				       pps_val);
+		intel_dsc_write_pps_reg(crtc_state, 18, pps_val);
 	}
 
 	/* Populate the RC_BUF_THRESH registers */
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [Intel-gfx] [PATCH v3 6/7] drm/i915/vdsc: Fill the intel_dsc_get_pps_config function
  2023-07-17 10:09 [Intel-gfx] [PATCH v3 0/7] Add DSC PPS readout Suraj Kandpal
                   ` (4 preceding siblings ...)
  2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 5/7] drm/i915/vdsc: Add function to write in PPS register Suraj Kandpal
@ 2023-07-17 10:09 ` Suraj Kandpal
  2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 7/7] drm/i915/display: Compare the readout dsc pps params Suraj Kandpal
                   ` (3 subsequent siblings)
  9 siblings, 0 replies; 13+ messages in thread
From: Suraj Kandpal @ 2023-07-17 10:09 UTC (permalink / raw)
  To: intel-gfx

We have setup both the read and write functions so we can
move ahead and fill in all the readout state from PPS register
into the crtc_state so we can send it for comparision.

--v2
-Shorten comment to just PPSX rather than having the whole
"Readout PPSX register" [Jani]
-Remove pps_temp reinitialization as its being initialized in
the read function [Jani]
-Use REG_FIELD_GET to readout certain fields of dsc registers
[Jani]

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c     | 99 +++++++++++++++++--
 .../gpu/drm/i915/display/intel_vdsc_regs.h    |  3 +
 2 files changed, 96 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 2f0362241059..8c57a42bb8f7 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -828,18 +828,105 @@ static void intel_dsc_read_and_verify_pps_reg(struct intel_crtc_state *crtc_stat
 static void intel_dsc_get_pps_config(struct intel_crtc_state *crtc_state)
 {
 	struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
-	u32 pps_temp1, pps_temp2;
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+	u32 pps_temp;
+
+	/* PPS_0 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp);
 
-	/* Readout PPS_0 and PPS_1 registers */
-	intel_dsc_read_and_verify_pps_reg(crtc_state, 0, &pps_temp1);
-	intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp2);
+	vdsc_cfg->bits_per_component = (pps_temp & DSC_BPC_MASK) >> DSC_BPC_SHIFT;
+	vdsc_cfg->line_buf_depth =
+		(pps_temp & DSC_LINE_BUF_DEPTH_MASK) >> DSC_LINE_BUF_DEPTH_SHIFT;
+	vdsc_cfg->block_pred_enable = pps_temp & DSC_BLOCK_PREDICTION;
+	vdsc_cfg->convert_rgb = pps_temp & DSC_COLOR_SPACE_CONVERSION;
+	vdsc_cfg->simple_422 = pps_temp & DSC_422_ENABLE;
+	vdsc_cfg->native_422 = pps_temp & DSC_NATIVE_422_ENABLE;
+	vdsc_cfg->native_420 = pps_temp & DSC_NATIVE_420_ENABLE;
+	vdsc_cfg->vbr_enable = pps_temp & DSC_VBR_ENABLE;
 
-	vdsc_cfg->bits_per_pixel = pps_temp2;
+	/* PPS_1 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 1, &pps_temp);
 
-	if (pps_temp1 & DSC_NATIVE_420_ENABLE)
+	vdsc_cfg->bits_per_pixel = pps_temp;
+
+	if (vdsc_cfg->native_420)
 		vdsc_cfg->bits_per_pixel >>= 1;
 
 	crtc_state->dsc.compressed_bpp = vdsc_cfg->bits_per_pixel >> 4;
+
+	/* PPS_2 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 2, &pps_temp);
+
+	vdsc_cfg->pic_width = REG_FIELD_GET(DSC_PIC_WIDTH_MASK, pps_temp);
+	vdsc_cfg->pic_height = REG_FIELD_GET(DSC_PIC_HEIGHT_MASK, pps_temp);
+
+	/* PPS_3 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 3, &pps_temp);
+
+	vdsc_cfg->slice_width = REG_FIELD_GET(DSC_SLICE_WIDTH_MASK, pps_temp);
+	vdsc_cfg->slice_height = REG_FIELD_GET(DSC_SLICE_HEIGHT_MASK, pps_temp);
+
+	/* PPS_4 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 4, &pps_temp);
+
+	vdsc_cfg->initial_dec_delay = REG_FIELD_GET(DSC_INITIAL_DEC_DELAY_MASK, pps_temp);
+	vdsc_cfg->initial_xmit_delay = REG_FIELD_GET(DSC_INITIAL_XMIT_DELAY_MASK, pps_temp);
+
+	/* PPS_5 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 5, &pps_temp);
+
+	vdsc_cfg->scale_decrement_interval = REG_FIELD_GET(DSC_SCALE_DEC_INT_MASK, pps_temp);
+	vdsc_cfg->scale_increment_interval = REG_FIELD_GET(DSC_SCALE_INC_INT_MASK, pps_temp);
+
+	/* PPS_6 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 6, &pps_temp);
+
+	vdsc_cfg->initial_scale_value = REG_FIELD_GET(DSC_INITIAL_SCALE_VALUE_MASK, pps_temp);
+	vdsc_cfg->first_line_bpg_offset = REG_FIELD_GET(DSC_FIRST_LINE_BPG_OFFSET_MASK, pps_temp);
+	vdsc_cfg->flatness_min_qp = REG_FIELD_GET(DSC_FLATNESS_MIN_QP_MASK, pps_temp);
+	vdsc_cfg->flatness_max_qp = REG_FIELD_GET(DSC_FLATNESS_MAX_QP_MASK, pps_temp);
+
+	/* PPS_7 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 7, &pps_temp);
+
+	vdsc_cfg->nfl_bpg_offset = REG_FIELD_GET(DSC_NFL_BPG_OFFSET_MASK, pps_temp);
+	vdsc_cfg->slice_bpg_offset = REG_FIELD_GET(DSC_SLICE_BPG_OFFSET_MASK, pps_temp);
+
+	/* PPS_8 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 8, &pps_temp);
+
+	vdsc_cfg->initial_offset = REG_FIELD_GET(DSC_INITIAL_OFFSET_MASK, pps_temp);
+	vdsc_cfg->final_offset = REG_FIELD_GET(DSC_FINAL_OFFSET_MASK, pps_temp);
+
+	/* PPS_9 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 9, &pps_temp);
+
+	vdsc_cfg->rc_model_size = REG_FIELD_GET(DSC_RC_MODEL_SIZE_MASK, pps_temp);
+
+	/* PPS_10 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 10, &pps_temp);
+
+	vdsc_cfg->rc_quant_incr_limit0 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT0_MASK, pps_temp);
+	vdsc_cfg->rc_quant_incr_limit1 = REG_FIELD_GET(DSC_RC_QUANT_INC_LIMIT1_MASK, pps_temp);
+
+	/* PPS_16 */
+	intel_dsc_read_and_verify_pps_reg(crtc_state, 16, &pps_temp);
+
+	vdsc_cfg->slice_chunk_size = REG_FIELD_GET(DSC_SLICE_CHUNK_SIZE_MASK, pps_temp);
+
+	if (DISPLAY_VER(i915) >= 14) {
+		/* PPS_17 */
+		intel_dsc_read_and_verify_pps_reg(crtc_state, 17, &pps_temp);
+
+		vdsc_cfg->second_line_bpg_offset = REG_FIELD_GET(DSC_SL_BPG_OFFSET_MASK, pps_temp);
+
+		/* PPS_18 */
+		intel_dsc_read_and_verify_pps_reg(crtc_state, 18, &pps_temp);
+
+		vdsc_cfg->nsl_bpg_offset = REG_FIELD_GET(DSC_NSL_BPG_OFFSET_MASK, pps_temp);
+		vdsc_cfg->second_line_offset_adj = REG_FIELD_GET(DSC_SL_OFFSET_ADJ_MASK, pps_temp);
+	}
 }
 
 void intel_dsc_get_config(struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
index 785ede31116e..ebd1a59615f7 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc_regs.h
@@ -99,6 +99,9 @@
 #define  DSC_BPC_SHIFT			8
 #define  DSC_VER_MIN_SHIFT		4
 #define  DSC_VER_MAJ			(0x1 << 0)
+#define  DSC_LINE_BUF_DEPTH_MASK	REG_GENMASK(15, 12)
+#define  DSC_BPC_MASK			REG_GENMASK(11, 8)
+
 
 #define DSCA_PICTURE_PARAMETER_SET_1		_MMIO(0x6B204)
 #define DSCC_PICTURE_PARAMETER_SET_1		_MMIO(0x6BA04)
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [Intel-gfx] [PATCH v3 7/7] drm/i915/display: Compare the readout dsc pps params
  2023-07-17 10:09 [Intel-gfx] [PATCH v3 0/7] Add DSC PPS readout Suraj Kandpal
                   ` (5 preceding siblings ...)
  2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 6/7] drm/i915/vdsc: Fill the intel_dsc_get_pps_config function Suraj Kandpal
@ 2023-07-17 10:09 ` Suraj Kandpal
  2023-07-17 14:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC PPS readout (rev3) Patchwork
                   ` (2 subsequent siblings)
  9 siblings, 0 replies; 13+ messages in thread
From: Suraj Kandpal @ 2023-07-17 10:09 UTC (permalink / raw)
  To: intel-gfx

With the dsc config being readout and filled in crtc_state add
macros and use them to compare current and previous PPS param in
DSC.

--v2
-Remove version check [Jani]
-Remove dupe macro for dsc pipe compare and use the existing ones
[Jani]

Signed-off-by: Suraj Kandpal <suraj.kandpal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c | 31 ++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 43cba98f7753..9c407ceb082e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5376,6 +5376,37 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
 	PIPE_CONF_CHECK_I(master_transcoder);
 	PIPE_CONF_CHECK_X(bigjoiner_pipes);
 
+	PIPE_CONF_CHECK_BOOL(dsc.config.block_pred_enable);
+	PIPE_CONF_CHECK_BOOL(dsc.config.convert_rgb);
+	PIPE_CONF_CHECK_BOOL(dsc.config.simple_422);
+	PIPE_CONF_CHECK_BOOL(dsc.config.native_422);
+	PIPE_CONF_CHECK_BOOL(dsc.config.native_420);
+	PIPE_CONF_CHECK_BOOL(dsc.config.vbr_enable);
+	PIPE_CONF_CHECK_I(dsc.config.line_buf_depth);
+	PIPE_CONF_CHECK_I(dsc.config.bits_per_component);
+	PIPE_CONF_CHECK_I(dsc.config.pic_width);
+	PIPE_CONF_CHECK_I(dsc.config.pic_height);
+	PIPE_CONF_CHECK_I(dsc.config.slice_width);
+	PIPE_CONF_CHECK_I(dsc.config.slice_height);
+	PIPE_CONF_CHECK_I(dsc.config.initial_dec_delay);
+	PIPE_CONF_CHECK_I(dsc.config.initial_xmit_delay);
+	PIPE_CONF_CHECK_I(dsc.config.scale_decrement_interval);
+	PIPE_CONF_CHECK_I(dsc.config.scale_increment_interval);
+	PIPE_CONF_CHECK_I(dsc.config.initial_scale_value);
+	PIPE_CONF_CHECK_I(dsc.config.first_line_bpg_offset);
+	PIPE_CONF_CHECK_I(dsc.config.flatness_min_qp);
+	PIPE_CONF_CHECK_I(dsc.config.flatness_max_qp);
+	PIPE_CONF_CHECK_I(dsc.config.slice_bpg_offset);
+	PIPE_CONF_CHECK_I(dsc.config.nfl_bpg_offset);
+	PIPE_CONF_CHECK_I(dsc.config.initial_offset);
+	PIPE_CONF_CHECK_I(dsc.config.final_offset);
+	PIPE_CONF_CHECK_I(dsc.config.rc_model_size);
+	PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit0);
+	PIPE_CONF_CHECK_I(dsc.config.rc_quant_incr_limit1);
+	PIPE_CONF_CHECK_I(dsc.config.slice_chunk_size);
+	PIPE_CONF_CHECK_I(dsc.config.second_line_bpg_offset);
+	PIPE_CONF_CHECK_I(dsc.config.nsl_bpg_offset);
+
 	PIPE_CONF_CHECK_I(dsc.compression_enable);
 	PIPE_CONF_CHECK_I(dsc.dsc_split);
 	PIPE_CONF_CHECK_I(dsc.compressed_bpp);
-- 
2.25.1


^ permalink raw reply related	[flat|nested] 13+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC PPS readout (rev3)
  2023-07-17 10:09 [Intel-gfx] [PATCH v3 0/7] Add DSC PPS readout Suraj Kandpal
                   ` (6 preceding siblings ...)
  2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 7/7] drm/i915/display: Compare the readout dsc pps params Suraj Kandpal
@ 2023-07-17 14:48 ` Patchwork
  2023-07-17 14:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
  2023-07-17 15:07 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
  9 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2023-07-17 14:48 UTC (permalink / raw)
  To: Suraj Kandpal; +Cc: intel-gfx

== Series Details ==

Series: Add DSC PPS readout (rev3)
URL   : https://patchwork.freedesktop.org/series/120456/
State : warning

== Summary ==

Error: dim checkpatch failed
35e5b6fe7614 drm/i915/vdsc: Refactor dsc register field macro
e09ea59f2e49 drm/i915/vdsc: Add a check for dsc split cases
d8a331ec760b drm/i915/vdsc: Add function to read any PPS register
a0e2e1595c46 drm/i915/vdsc: Use MACRO to cleanup intel_dsc_get_pps_reg
-:19: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#19: FILE: drivers/gpu/drm/i915/display/intel_vdsc.c:373:
+#define PRE_MTL_GET_DSC_REGISTER(pps, is_pipe_dsc, pipe) do { \
+	if (is_pipe_dsc) { \
+		*dsc_reg0 = ICL_DSC0_PICTURE_PARAMETER_SET_##pps(pipe); \
+		*dsc_reg1 = ICL_DSC1_PICTURE_PARAMETER_SET_##pps(pipe); \
+	} else { \
+		*dsc_reg0 = DSCA_PICTURE_PARAMETER_SET_##pps; \
+		*dsc_reg1 = DSCC_PICTURE_PARAMETER_SET_##pps; \
+	} \
+} while (0)

-:29: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'pipe' - possible side-effects?
#29: FILE: drivers/gpu/drm/i915/display/intel_vdsc.c:383:
+#define MTL_GET_DSC_REGISTER(pps, pipe) do { \
+		*dsc_reg0 = MTL_DSC0_PICTURE_PARAMETER_SET_##pps(pipe); \
+		*dsc_reg1 = MTL_DSC1_PICTURE_PARAMETER_SET_##pps(pipe); \
+} while (0)

total: 0 errors, 0 warnings, 2 checks, 163 lines checked
05fc5c372fe4 drm/i915/vdsc: Add function to write in PPS register
6e552a852efe drm/i915/vdsc: Fill the intel_dsc_get_pps_config function
d3b81dba16cb drm/i915/display: Compare the readout dsc pps params



^ permalink raw reply	[flat|nested] 13+ messages in thread

* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add DSC PPS readout (rev3)
  2023-07-17 10:09 [Intel-gfx] [PATCH v3 0/7] Add DSC PPS readout Suraj Kandpal
                   ` (7 preceding siblings ...)
  2023-07-17 14:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC PPS readout (rev3) Patchwork
@ 2023-07-17 14:48 ` Patchwork
  2023-07-17 15:07 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
  9 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2023-07-17 14:48 UTC (permalink / raw)
  To: Suraj Kandpal; +Cc: intel-gfx

== Series Details ==

Series: Add DSC PPS readout (rev3)
URL   : https://patchwork.freedesktop.org/series/120456/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+drivers/gpu/drm/i915/display/intel_display_types.h:1884:17: warning: unreplaced symbol 'encoder'
+drivers/gpu/drm/i915/display/intel_display_types.h:1884:9: warning: unreplaced symbol 'break'
+drivers/gpu/drm/i915/display/intel_display_types.h:1884:9: warning: unreplaced symbol 'case'
+drivers/gpu/drm/i915/display/intel_display_types.h:1885:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1885:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1886:9: warning: too many warnings
+drivers/gpu/drm/i915/display/intel_display_types.h:1886:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1887:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1888:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1889:17: warning: unreplaced symbol 'return'
+drivers/gpu/drm/i915/display/intel_display_types.h:1890:9: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:1891:17: warning: unreplaced symbol 'return'
+drivers/gpu/drm/i915/display/intel_display_types.h:1910:9: warning: unreplaced symbol 'intel_encoder'
+drivers/gpu/drm/i915/display/intel_display_types.h:1957:24: warning: trying to copy expression type 31
+drivers/gpu/drm/i915/display/intel_display_types.h:1957:24: warning: trying to copy expression type 31
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:15: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:60:15: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:60:15: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:73:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:73:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:73:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:75:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:75:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:75:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:76:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:76:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:76:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:77:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:77:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:77:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:79:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:79:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:79:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:79:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:79:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:80:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:80:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:80:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:80:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:80:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:93:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:93:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:93:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:95:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:95:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:95:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:96:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:96:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:96:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:97:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:97:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:97:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:99:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:99:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:99:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:21: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:99:21: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:99:21: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/instrumented-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:112:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:112:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:112:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:115:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:115:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:115:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:127:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:127:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:127:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:130:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:130:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:130:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:139:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:139:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:139:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:142:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:142:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:142:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:26:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:26:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:26:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:42:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:42:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:42:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:58:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:58:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:58:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:97:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:97:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:97:1: warning: unreplaced symbol 'return'



^ permalink raw reply	[flat|nested] 13+ messages in thread

* [Intel-gfx] ✗ Fi.CI.BAT: failure for Add DSC PPS readout (rev3)
  2023-07-17 10:09 [Intel-gfx] [PATCH v3 0/7] Add DSC PPS readout Suraj Kandpal
                   ` (8 preceding siblings ...)
  2023-07-17 14:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-07-17 15:07 ` Patchwork
  9 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2023-07-17 15:07 UTC (permalink / raw)
  To: Suraj Kandpal; +Cc: intel-gfx

[-- Attachment #1: Type: text/plain, Size: 12784 bytes --]

== Series Details ==

Series: Add DSC PPS readout (rev3)
URL   : https://patchwork.freedesktop.org/series/120456/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_13390 -> Patchwork_120456v3
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_120456v3 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_120456v3, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/index.html

Participating hosts (41 -> 42)
------------------------------

  Additional (2): bat-atsm-1 fi-pnv-d510 
  Missing    (1): fi-snb-2520m 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_120456v3:

### IGT changes ###

#### Possible regressions ####

  * igt@dmabuf@all-tests@dma_fence:
    - bat-dg2-11:         [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13390/bat-dg2-11/igt@dmabuf@all-tests@dma_fence.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-dg2-11/igt@dmabuf@all-tests@dma_fence.html

  
Known issues
------------

  Here are the changes found in Patchwork_120456v3 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@core_auth@basic-auth:
    - bat-adlp-11:        NOTRUN -> [ABORT][3] ([i915#8011])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-adlp-11/igt@core_auth@basic-auth.html

  * igt@dmabuf@all-tests@sanitycheck:
    - bat-dg2-11:         [PASS][4] -> [ABORT][5] ([i915#7699] / [i915#8144])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13390/bat-dg2-11/igt@dmabuf@all-tests@sanitycheck.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-dg2-11/igt@dmabuf@all-tests@sanitycheck.html

  * igt@gem_exec_suspend@basic-s0@lmem0:
    - bat-atsm-1:         NOTRUN -> [DMESG-WARN][6] ([i915#8841]) +3 similar issues
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-atsm-1/igt@gem_exec_suspend@basic-s0@lmem0.html

  * igt@gem_exec_suspend@basic-s3@lmem0:
    - bat-atsm-1:         NOTRUN -> [DMESG-WARN][7] ([i915#8504] / [i915#8841])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-atsm-1/igt@gem_exec_suspend@basic-s3@lmem0.html

  * igt@gem_mmap@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][8] ([i915#4083])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-atsm-1/igt@gem_mmap@basic.html

  * igt@gem_render_tiled_blits@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][9] ([i915#4079]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-atsm-1/igt@gem_render_tiled_blits@basic.html

  * igt@gem_tiled_fence_blits@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][10] ([i915#4077]) +2 similar issues
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-atsm-1/igt@gem_tiled_fence_blits@basic.html

  * igt@i915_pm_rpm@basic-rte:
    - fi-skl-guc:         [PASS][11] -> [FAIL][12] ([i915#7940])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13390/fi-skl-guc/igt@i915_pm_rpm@basic-rte.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/fi-skl-guc/igt@i915_pm_rpm@basic-rte.html

  * igt@i915_pm_rps@basic-api:
    - bat-atsm-1:         NOTRUN -> [SKIP][13] ([i915#6621])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-atsm-1/igt@i915_pm_rps@basic-api.html

  * igt@i915_suspend@basic-s3-without-i915:
    - fi-pnv-d510:        NOTRUN -> [ABORT][14] ([i915#8844])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/fi-pnv-d510/igt@i915_suspend@basic-s3-without-i915.html
    - bat-atsm-1:         NOTRUN -> [SKIP][15] ([i915#6645])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-atsm-1/igt@i915_suspend@basic-s3-without-i915.html

  * igt@kms_addfb_basic@size-max:
    - bat-atsm-1:         NOTRUN -> [SKIP][16] ([i915#6077]) +36 similar issues
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-atsm-1/igt@kms_addfb_basic@size-max.html

  * igt@kms_chamelium_hpd@common-hpd-after-suspend:
    - bat-jsl-1:          NOTRUN -> [SKIP][17] ([i915#7828])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-jsl-1/igt@kms_chamelium_hpd@common-hpd-after-suspend.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
    - bat-atsm-1:         NOTRUN -> [SKIP][18] ([i915#6078]) +19 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-atsm-1/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html

  * igt@kms_flip@basic-flip-vs-wf_vblank:
    - bat-atsm-1:         NOTRUN -> [SKIP][19] ([i915#6166]) +3 similar issues
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-atsm-1/igt@kms_flip@basic-flip-vs-wf_vblank.html

  * igt@kms_force_connector_basic@force-load-detect:
    - bat-atsm-1:         NOTRUN -> [SKIP][20] ([i915#6093]) +3 similar issues
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-atsm-1/igt@kms_force_connector_basic@force-load-detect.html

  * igt@kms_pipe_crc_basic@read-crc-frame-sequence:
    - bat-atsm-1:         NOTRUN -> [SKIP][21] ([i915#1836]) +6 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-atsm-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence.html

  * igt@kms_prop_blob@basic:
    - bat-atsm-1:         NOTRUN -> [SKIP][22] ([i915#7357])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-atsm-1/igt@kms_prop_blob@basic.html

  * igt@kms_psr@primary_page_flip:
    - fi-pnv-d510:        NOTRUN -> [SKIP][23] ([fdo#109271]) +37 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/fi-pnv-d510/igt@kms_psr@primary_page_flip.html

  * igt@kms_psr@sprite_plane_onoff:
    - bat-atsm-1:         NOTRUN -> [SKIP][24] ([i915#1072]) +3 similar issues
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-atsm-1/igt@kms_psr@sprite_plane_onoff.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - bat-atsm-1:         NOTRUN -> [SKIP][25] ([i915#6094])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-atsm-1/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@prime_vgem@basic-fence-flip:
    - bat-atsm-1:         NOTRUN -> [SKIP][26] ([fdo#109295] / [i915#6078])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-atsm-1/igt@prime_vgem@basic-fence-flip.html

  * igt@prime_vgem@basic-gtt:
    - bat-atsm-1:         NOTRUN -> [SKIP][27] ([fdo#109295] / [i915#4077]) +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-atsm-1/igt@prime_vgem@basic-gtt.html

  * igt@prime_vgem@basic-write:
    - bat-atsm-1:         NOTRUN -> [SKIP][28] ([fdo#109295]) +2 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-atsm-1/igt@prime_vgem@basic-write.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-cfl-8700k:       [FAIL][29] ([i915#7940]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13390/fi-cfl-8700k/igt@i915_pm_rpm@basic-pci-d3-state.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/fi-cfl-8700k/igt@i915_pm_rpm@basic-pci-d3-state.html

  * igt@i915_pm_rpm@module-reload:
    - fi-rkl-11600:       [FAIL][31] ([i915#7940]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13390/fi-rkl-11600/igt@i915_pm_rpm@module-reload.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/fi-rkl-11600/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live@migrate:
    - bat-dg2-11:         [DMESG-WARN][33] ([i915#7699]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13390/bat-dg2-11/igt@i915_selftest@live@migrate.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-dg2-11/igt@i915_selftest@live@migrate.html
    - bat-jsl-1:          [INCOMPLETE][35] ([i915#8504]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13390/bat-jsl-1/igt@i915_selftest@live@migrate.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-jsl-1/igt@i915_selftest@live@migrate.html

  * igt@kms_chamelium_frames@dp-crc-fast:
    - {bat-dg2-13}:       [DMESG-WARN][37] ([Intel XE#485]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13390/bat-dg2-13/igt@kms_chamelium_frames@dp-crc-fast.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-dg2-13/igt@kms_chamelium_frames@dp-crc-fast.html

  
#### Warnings ####

  * igt@i915_module_load@load:
    - bat-adlp-11:        [ABORT][39] ([i915#4423]) -> [DMESG-WARN][40] ([i915#4423])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13390/bat-adlp-11/igt@i915_module_load@load.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-adlp-11/igt@i915_module_load@load.html

  * igt@kms_psr@sprite_plane_onoff:
    - bat-rplp-1:         [ABORT][41] ([i915#8442] / [i915#8712]) -> [ABORT][42] ([i915#8442] / [i915#8668] / [i915#8712])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13390/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [Intel XE#485]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/485
  [Intel XE#486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/486
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
  [i915#6077]: https://gitlab.freedesktop.org/drm/intel/issues/6077
  [i915#6078]: https://gitlab.freedesktop.org/drm/intel/issues/6078
  [i915#6093]: https://gitlab.freedesktop.org/drm/intel/issues/6093
  [i915#6094]: https://gitlab.freedesktop.org/drm/intel/issues/6094
  [i915#6166]: https://gitlab.freedesktop.org/drm/intel/issues/6166
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
  [i915#7357]: https://gitlab.freedesktop.org/drm/intel/issues/7357
  [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
  [i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
  [i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
  [i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
  [i915#8144]: https://gitlab.freedesktop.org/drm/intel/issues/8144
  [i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
  [i915#8504]: https://gitlab.freedesktop.org/drm/intel/issues/8504
  [i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
  [i915#8712]: https://gitlab.freedesktop.org/drm/intel/issues/8712
  [i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
  [i915#8844]: https://gitlab.freedesktop.org/drm/intel/issues/8844
  [i915#8879]: https://gitlab.freedesktop.org/drm/intel/issues/8879


Build changes
-------------

  * Linux: CI_DRM_13390 -> Patchwork_120456v3

  CI-20190529: 20190529
  CI_DRM_13390: 3d28151face410f5cafffdb42710041f889dc733 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7388: 7388
  Patchwork_120456v3: 3d28151face410f5cafffdb42710041f889dc733 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

3e6516b14819 drm/i915/display: Compare the readout dsc pps params
267ce58a85f2 drm/i915/vdsc: Fill the intel_dsc_get_pps_config function
b3d0d6a16c6b drm/i915/vdsc: Add function to write in PPS register
a2c256fb3c79 drm/i915/vdsc: Use MACRO to cleanup intel_dsc_get_pps_reg
9f1114b88151 drm/i915/vdsc: Add function to read any PPS register
9bd2a6acd299 drm/i915/vdsc: Add a check for dsc split cases
d9508a160555 drm/i915/vdsc: Refactor dsc register field macro

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120456v3/index.html

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^ permalink raw reply	[flat|nested] 13+ messages in thread

end of thread, other threads:[~2023-07-18  9:43 UTC | newest]

Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-07-17 10:09 [Intel-gfx] [PATCH v3 0/7] Add DSC PPS readout Suraj Kandpal
2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 1/7] drm/i915/vdsc: Refactor dsc register field macro Suraj Kandpal
2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 2/7] drm/i915/vdsc: Add a check for dsc split cases Suraj Kandpal
2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 3/7] drm/i915/vdsc: Add function to read any PPS register Suraj Kandpal
2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 4/7] drm/i915/vdsc: Use MACRO to cleanup intel_dsc_get_pps_reg Suraj Kandpal
2023-07-18  9:24   ` Nautiyal, Ankit K
2023-07-18  9:43     ` Nautiyal, Ankit K
2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 5/7] drm/i915/vdsc: Add function to write in PPS register Suraj Kandpal
2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 6/7] drm/i915/vdsc: Fill the intel_dsc_get_pps_config function Suraj Kandpal
2023-07-17 10:09 ` [Intel-gfx] [PATCH v3 7/7] drm/i915/display: Compare the readout dsc pps params Suraj Kandpal
2023-07-17 14:48 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DSC PPS readout (rev3) Patchwork
2023-07-17 14:48 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-07-17 15:07 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork

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