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From: John Harrison <john.c.harrison@intel.com>
To: Andi Shyti <andi.shyti@linux.intel.com>,
	Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: janusz.krzysztofik@intel.com, matthew.d.roper@intel.com,
	intel-gfx@lists.freedesktop.org,
	Jonathan Cavitt <jonathan.cavitt@intel.com>,
	chris.p.wilson@linux.intel.com, nirmoy.das@intel.com
Subject: Re: [Intel-gfx] [PATCH v3 1/4] drm/i915: Define and use GuC and CTB TLB invalidation routines
Date: Tue, 3 Oct 2023 13:29:52 -0700	[thread overview]
Message-ID: <34c8cffc-ece1-dab4-1e41-4fc8b632157d@intel.com> (raw)
In-Reply-To: <ZRxEOCI6Xq1UEnlw@ashyti-mobl2.lan>

On 10/3/2023 09:41, Andi Shyti wrote:
> [...]
>
>>> -		mmio_invalidate_full(gt);
>>> +		if (INTEL_GUC_SUPPORTS_TLB_INVALIDATION(guc)) {
>>> +			if (intel_guc_is_ready(guc))
>>> +				intel_guc_invalidate_tlb_full(guc);
>>> +		} else {
>>> +			/*
>>> +			 * Fall back to old path if GuC is disabled.
>>> +			 * This is safe because GuC is not enabled and not writing to MMIO.
>>> +			 */
>> It is safe for intel_guc_is_ready() transitioning from false to true during GuC init? No way for some path to start issuing invalidations as that is happening?
>>
>>> +			mmio_invalidate_full(gt);
>>> +		}
> supernitpick: as we are at this, brackets are not required.
Braces are required on the first half of the 'if' because it is a double 
if and the else applies to the top level not the inner level. And my 
understanding of the style guide is that lop-sided bracing is incorrect. 
i.e. never have "} else". Plus while it might be syntactically valid to 
not have braces around the five line else clause because it is only one 
actual code statement, it massively helps readability of the code to 
have the braces present.

John.

>
> Andi


  reply	other threads:[~2023-10-03 20:30 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-02 17:24 [Intel-gfx] [PATCH v3 1/4] drm/i915: Define and use GuC and CTB TLB invalidation routines Jonathan Cavitt
2023-10-02 17:24 ` [Intel-gfx] [PATCH v3 2/4] drm/i915: No TLB invalidation on wedged or suspended GT Jonathan Cavitt
2023-10-03 10:35   ` Tvrtko Ursulin
2023-10-03 11:50   ` Jani Nikula
2023-10-02 17:24 ` [Intel-gfx] [PATCH v3 3/4] drm/i915: Perform TLB invalidation on all GTs during suspend/resume Jonathan Cavitt
2023-10-03 11:48   ` Jani Nikula
2023-10-03 15:59     ` Andi Shyti
2023-10-03 18:52       ` John Harrison
2023-10-04  7:34         ` Jani Nikula
2023-10-02 17:24 ` [Intel-gfx] [PATCH v3 4/4] drm/i915/gt: Increase sleep in gt_tlb selftest sanitycheck Jonathan Cavitt
2023-10-02 23:42 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v3,1/4] drm/i915: Define and use GuC and CTB TLB invalidation routines Patchwork
2023-10-02 23:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-03  0:01 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-10-03 10:28 ` [Intel-gfx] [PATCH v3 1/4] " Tvrtko Ursulin
2023-10-03 16:41   ` Andi Shyti
2023-10-03 20:29     ` John Harrison [this message]
2023-10-03 21:29       ` Andi Shyti
2023-10-04  7:54     ` Tvrtko Ursulin
2023-10-03 20:23   ` John Harrison
2023-10-04  8:12     ` Tvrtko Ursulin
2023-10-03 11:06 ` Tvrtko Ursulin

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