[PATCH v4 00/13] drm/i915/display: Add DC3CO support

[PATCH v4 00/13] drm/i915/display: Add DC3CO support

[Dibin Moolakadan Subrahmanian]

This series adds initial DC3CO support for display version 35+ and adds
debugfs visibility into DC3CO count/residency.

The series also includes required PSR/ALPM updates for DC3CO enablement.

This series is based on the CMTG enablement series currently under
review:
https://patchwork.freedesktop.org/series/157664/

DC3CO is not enabled by this series since power_domains->allowed_dc_mask
is not updated to include DC3CO.

TODO:
- Enable DC3CO in power_domains->allowed_dc_mask

Changes in v2:
- Move dc3co state from intel_atomic_state to display->power
- Squash cleanup and related patches to reduce series from 19 to 13
  patches

Changes in v3:
- Fix trigger always returning zero in intel_dc3co_compute_state().

Changes in v4:
- Call intel_display_power_set_target_dc_state() only when
  DC3CO is supported.
- Add as_sdp_supported check for Panel Replay trigger.
- Add 1:1 pipe-port mapping check for display version 35
  in intel_dc3co_port_pipe_compatible() and change 
  dc3co eligibility compute logic.
- Re-arm DC3CO work in PSR resume, and schedule it 
  from intel_psr_post_plane_update() to cover cases
  where no PSR flush occurs.
- Remove dc state validation that could break the fallback mechanism.
- Keep dc5_reg initialization in the xe3lp debugfs
  to avoid invalid register access.

Dibin Moolakadan Subrahmanian (13):
  drm/i915/display: Remove TGL DC3CO support
  drm/i915/display: Switch DC3CO enable from standalone bit to DC level
    encoding
  drm/i915/display: Use FIELD_PREP() for DC state enable bits
  drm/i915/display: Add DC3CO DC_STATE enable/disable support
  drm/i915/display: Add DC3CO support check
  drm/i915/display: Add HAS_DC3CO() macro
  drm/i915/display: Add DC3CO eligibility computation
  drm/i915/display: Store DC3CO eligibility in PSR state
  drm/i915/display: PSR2: Set idle_frames to 0 for DC3CO
  drm/i915/display: Enable DC3CO idle protocol in ALPM
  drm/i915/display: PSR Add delayed work to exit DC3CO
  drm/i915/display: Add helper to enable DC counter
  drm/i915/display: Add DC3CO count and residency in dmc debugfs

 drivers/gpu/drm/i915/display/intel_alpm.c     |   6 +
 drivers/gpu/drm/i915/display/intel_display.c  | 102 +++++++-
 .../gpu/drm/i915/display/intel_display_core.h |   3 +-
 .../drm/i915/display/intel_display_device.h   |   1 +
 .../drm/i915/display/intel_display_power.c    |  44 +++-
 .../drm/i915/display/intel_display_power.h    |  23 ++
 .../i915/display/intel_display_power_well.c   |  36 ++-
 .../i915/display/intel_display_power_well.h   |   1 +
 .../gpu/drm/i915/display/intel_display_regs.h |  14 +-
 .../drm/i915/display/intel_display_types.h    |   7 +-
 drivers/gpu/drm/i915/display/intel_dmc.c      |  16 +-
 drivers/gpu/drm/i915/display/intel_dmc_regs.h |   2 +
 drivers/gpu/drm/i915/display/intel_dmc_wl.c   |   2 +-
 drivers/gpu/drm/i915/display/intel_psr.c      | 245 +++++-------------
 drivers/gpu/drm/i915/display/intel_psr_regs.h |   1 +
 15 files changed, 285 insertions(+), 218 deletions(-)

-- 
2.43.0

[PATCH v4 01/13] drm/i915/display: Remove TGL DC3CO support

[Dibin Moolakadan Subrahmanian]

Remove all Tiger Lake DC3CO-related functions from intel_psr.c and
intel_display_power_well.c, as the feature is not enabled and not used.
Also remove the TGL/DG1 DC3CO count debugfs entry from intel_dmc.c,
as DC3CO is not active on those platforms. A new debugfs entry for
Xe3LP will be added in a subsequent patch.

Remove the unused dc3co_exitline field from struct intel_psr and
struct intel_crtc_state, along with the corresponding EXITLINE register
read in intel_psr_get_config().

Changes in v2:
- Squash "Remove unused PSR dc3co_exitline field" and
  "Remove unused dc3co_exitline from crtc_state" into this patch

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 .../i915/display/intel_display_power_well.c   |  25 ---
 .../drm/i915/display/intel_display_types.h    |   3 -
 drivers/gpu/drm/i915/display/intel_dmc.c      |   6 -
 drivers/gpu/drm/i915/display/intel_psr.c      | 171 ------------------
 4 files changed, 205 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 04bd0dde5bed..2f0d0a77c1a2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -866,23 +866,6 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
 	power_domains->dc_state = val & mask;
 }
 
-static void tgl_enable_dc3co(struct intel_display *display)
-{
-	drm_dbg_kms(display->drm, "Enabling DC3CO\n");
-	gen9_set_dc_state(display, DC_STATE_EN_DC3CO);
-}
-
-static void tgl_disable_dc3co(struct intel_display *display)
-{
-	drm_dbg_kms(display->drm, "Disabling DC3CO\n");
-	intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0);
-	gen9_set_dc_state(display, DC_STATE_DISABLE);
-	/*
-	 * Delay of 200us DC3CO Exit time B.Spec 49196
-	 */
-	usleep_range(200, 210);
-}
-
 static void assert_can_enable_dc5(struct intel_display *display)
 {
 	enum i915_power_well_id high_pg;
@@ -1061,11 +1044,6 @@ void gen9_disable_dc_states(struct intel_display *display)
 	struct intel_cdclk_config cdclk_config = {};
 	u32 old_state = power_domains->dc_state;
 
-	if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) {
-		tgl_disable_dc3co(display);
-		return;
-	}
-
 	if (HAS_DISPLAY(display)) {
 		intel_dmc_wl_get_noreg(display);
 		gen9_set_dc_state(display, DC_STATE_DISABLE);
@@ -1114,9 +1092,6 @@ static void gen9_dc_off_power_well_disable(struct intel_display *display,
 		return;
 
 	switch (power_domains->target_dc_state) {
-	case DC_STATE_EN_DC3CO:
-		tgl_enable_dc3co(display);
-		break;
 	case DC_STATE_EN_UPTO_DC6:
 		skl_enable_dc6(display);
 		break;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index f44be5c689ae..1cfc585530dc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1184,7 +1184,6 @@ struct intel_crtc_state {
 	bool pkg_c_latency_used;
 	/* Only used for state verification. */
 	enum intel_panel_replay_dsc_support panel_replay_dsc_support;
-	u32 dc3co_exitline;
 	u16 su_y_granularity;
 	u8 active_non_psr_pipes;
 	u8 entry_setup_frames;
@@ -1776,9 +1775,7 @@ struct intel_psr {
 	bool source_panel_replay_support;
 	bool sink_panel_replay_support;
 	bool panel_replay_enabled;
-	u32 dc3co_exitline;
 	u32 dc3co_exit_delay;
-	struct delayed_work dc3co_work;
 	u8 entry_setup_frames;
 
 	u8 io_wake_lines;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 481fb65b7110..4785001644f5 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -1647,19 +1647,13 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 		   DMC_VERSION_MINOR(dmc->version));
 
 	if (DISPLAY_VER(display) >= 12) {
-		intel_reg_t dc3co_reg;
-
 		if (display->platform.dgfx || DISPLAY_VER(display) >= 14) {
-			dc3co_reg = DG1_DMC_DEBUG3;
 			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
 		} else {
-			dc3co_reg = TGL_DMC_DEBUG3;
 			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
 			dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
 		}
 
-		seq_printf(m, "DC3CO count: %d\n",
-			   intel_de_read(display, dc3co_reg));
 	} else {
 		dc5_reg = display->platform.broxton ? BXT_DMC_DC3_DC5_COUNT :
 			SKL_DMC_DC3_DC5_COUNT;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b0414bd1dc6b..730ca7af7873 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -88,22 +88,6 @@
  * issues the self-refresh re-enable code is done from a work queue, which
  * must be correctly synchronized/cancelled when shutting down the pipe."
  *
- * DC3CO (DC3 clock off)
- *
- * On top of PSR2, GEN12 adds a intermediate power savings state that turns
- * clock off automatically during PSR2 idle state.
- * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep sleep
- * entry/exit allows the HW to enter a low-power state even when page flipping
- * periodically (for instance a 30fps video playback scenario).
- *
- * Every time a flips occurs PSR2 will get out of deep sleep state(if it was),
- * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after 6
- * frames, if no other flip occurs and the function above is executed, DC3CO is
- * disabled and PSR2 is configured to enter deep sleep, resetting again in case
- * of another flip.
- * Front buffer modifications do not trigger DC3CO activation on purpose as it
- * would bring a lot of complexity and most of the moderns systems will only
- * use page flips.
  */
 
 /*
@@ -1217,108 +1201,6 @@ static void psr2_program_idle_frames(struct intel_dp *intel_dp,
 		     EDP_PSR2_IDLE_FRAMES(idle_frames));
 }
 
-static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp)
-{
-	struct intel_display *display = to_intel_display(intel_dp);
-
-	psr2_program_idle_frames(intel_dp, 0);
-	intel_display_power_set_target_dc_state(display, DC_STATE_EN_DC3CO);
-}
-
-static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp)
-{
-	struct intel_display *display = to_intel_display(intel_dp);
-
-	intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
-	psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp));
-}
-
-static void tgl_dc3co_disable_work(struct work_struct *work)
-{
-	struct intel_dp *intel_dp =
-		container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
-
-	mutex_lock(&intel_dp->psr.lock);
-	/* If delayed work is pending, it is not idle */
-	if (delayed_work_pending(&intel_dp->psr.dc3co_work))
-		goto unlock;
-
-	tgl_psr2_disable_dc3co(intel_dp);
-unlock:
-	mutex_unlock(&intel_dp->psr.lock);
-}
-
-static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp)
-{
-	if (!intel_dp->psr.dc3co_exitline)
-		return;
-
-	cancel_delayed_work(&intel_dp->psr.dc3co_work);
-	/* Before PSR2 exit disallow dc3co*/
-	tgl_psr2_disable_dc3co(intel_dp);
-}
-
-static bool
-dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp,
-			      struct intel_crtc_state *crtc_state)
-{
-	struct intel_display *display = to_intel_display(intel_dp);
-	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
-	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
-	enum port port = dig_port->base.port;
-
-	if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
-		return pipe <= PIPE_B && port <= PORT_B;
-	else
-		return pipe == PIPE_A && port == PORT_A;
-}
-
-static void
-tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
-				  struct intel_crtc_state *crtc_state)
-{
-	struct intel_display *display = to_intel_display(intel_dp);
-	const u32 crtc_vdisplay = crtc_state->uapi.adjusted_mode.crtc_vdisplay;
-	struct i915_power_domains *power_domains = &display->power.domains;
-	u32 exit_scanlines;
-
-	/*
-	 * FIXME: Due to the changed sequence of activating/deactivating DC3CO,
-	 * disable DC3CO until the changed dc3co activating/deactivating sequence
-	 * is applied. B.Specs:49196
-	 */
-	return;
-
-	/*
-	 * DMC's DC3CO exit mechanism has an issue with Selective Fecth
-	 * TODO: when the issue is addressed, this restriction should be removed.
-	 */
-	if (crtc_state->enable_psr2_sel_fetch)
-		return;
-
-	if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC3CO))
-		return;
-
-	if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
-		return;
-
-	/* Wa_16011303918:adl-p */
-	if (intel_display_wa(display, INTEL_DISPLAY_WA_16011303918))
-		return;
-
-	/*
-	 * DC3CO Exit time 200us B.Spec 49196
-	 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) + 1
-	 */
-	exit_scanlines =
-		intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode, 200) + 1;
-
-	if (drm_WARN_ON(display->drm, exit_scanlines > crtc_vdisplay))
-		return;
-
-	crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
-}
-
 static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
 					      struct intel_crtc_state *crtc_state)
 {
@@ -1688,8 +1570,6 @@ static bool intel_psr2_config_valid(struct intel_dp *intel_dp,
 		return false;
 	}
 
-	tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
-
 	return true;
 }
 
@@ -2004,12 +1884,6 @@ void intel_psr_get_config(struct intel_encoder *encoder,
 	}
 
 	pipe_config->enable_psr2_su_region_et = intel_dp->psr.su_region_et_enabled;
-
-	if (DISPLAY_VER(display) >= 12) {
-		val = intel_de_read(display,
-				    TRANS_EXITLINE(display, cpu_transcoder));
-		pipe_config->dc3co_exitline = REG_FIELD_GET(EXITLINE_MASK, val);
-	}
 unlock:
 	mutex_unlock(&intel_dp->psr.lock);
 }
@@ -2137,16 +2011,6 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp,
 
 	psr_irq_control(intel_dp);
 
-	/*
-	 * TODO: if future platforms supports DC3CO in more than one
-	 * transcoder, EXITLINE will need to be unset when disabling PSR
-	 */
-	if (intel_dp->psr.dc3co_exitline)
-		intel_de_rmw(display,
-			     TRANS_EXITLINE(display, cpu_transcoder),
-			     EXITLINE_MASK,
-			     intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT | EXITLINE_ENABLE);
-
 	if (HAS_PSR_HW_TRACKING(display) && HAS_PSR2_SEL_FETCH(display))
 		intel_de_rmw(display, CHICKEN_PAR1_1, IGNORE_PSR2_HW_TRACKING,
 			     intel_dp->psr.psr2_sel_fetch_enabled ?
@@ -2246,7 +2110,6 @@ static void intel_psr_enable_locked(struct intel_dp *intel_dp,
 	/* DC5/DC6 requires at least 6 idle frames */
 	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
 	intel_dp->psr.dc3co_exit_delay = val;
-	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
 	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state->enable_psr2_sel_fetch;
 	intel_dp->psr.su_region_et_enabled = crtc_state->enable_psr2_su_region_et;
 	intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
@@ -2325,8 +2188,6 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
 		intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder),
 			     TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
 	} else if (intel_dp->psr.sel_update_enabled) {
-		tgl_disallow_dc3co_on_psr2_exit(intel_dp);
-
 		val = intel_de_rmw(display,
 				   EDP_PSR2_CTL(display, cpu_transcoder),
 				   EDP_PSR2_ENABLE, 0);
@@ -2468,7 +2329,6 @@ void intel_psr_disable(struct intel_dp *intel_dp,
 
 	mutex_unlock(&intel_dp->psr.lock);
 	cancel_work_sync(&intel_dp->psr.work);
-	cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
 }
 
 /**
@@ -2499,7 +2359,6 @@ void intel_psr_pause(struct intel_dp *intel_dp)
 	mutex_unlock(&psr->lock);
 
 	cancel_work_sync(&psr->work);
-	cancel_delayed_work_sync(&psr->dc3co_work);
 }
 
 /**
@@ -3650,34 +3509,6 @@ void intel_psr_invalidate(struct intel_display *display,
 		mutex_unlock(&intel_dp->psr.lock);
 	}
 }
-/*
- * When we will be completely rely on PSR2 S/W tracking in future,
- * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
- * event also therefore tgl_dc3co_flush_locked() require to be changed
- * accordingly in future.
- */
-static void
-tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
-		       enum fb_op_origin origin)
-{
-	struct intel_display *display = to_intel_display(intel_dp);
-
-	if (!intel_dp->psr.dc3co_exitline || !intel_dp->psr.sel_update_enabled ||
-	    !intel_dp->psr.active)
-		return;
-
-	/*
-	 * At every frontbuffer flush flip event modified delay of delayed work,
-	 * when delayed work schedules that means display has been idle.
-	 */
-	if (!(frontbuffer_bits &
-	    INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
-		return;
-
-	tgl_psr2_enable_dc3co(intel_dp);
-	mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work,
-			 intel_dp->psr.dc3co_exit_delay);
-}
 
 static void _psr_flush_handle(struct intel_dp *intel_dp)
 {
@@ -3764,7 +3595,6 @@ void intel_psr_flush(struct intel_display *display,
 		if (origin == ORIGIN_FLIP ||
 		    (origin == ORIGIN_CURSOR_UPDATE &&
 		     !intel_dp->psr.psr2_sel_fetch_enabled)) {
-			tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin);
 			goto unlock;
 		}
 
@@ -3823,7 +3653,6 @@ void intel_psr_init(struct intel_dp *intel_dp)
 		intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;
 
 	INIT_WORK(&intel_dp->psr.work, intel_psr_work);
-	INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, tgl_dc3co_disable_work);
 	mutex_init(&intel_dp->psr.lock);
 }
 
-- 
2.43.0

[PATCH v4 02/13] drm/i915/display: Switch DC3CO enable from standalone bit to DC level encoding

[Dibin Moolakadan Subrahmanian]

On platforms prior to xe3, DC3CO was controlled via a standalone enable
bit. Starting with xe3, DC3CO is encoded as part of the existing
DC_STATE_EN_UPTO_DC* field.

No functional change, as DC3CO is not enabled on platforms prior to xe3.

Changes in v2:
- Update commit header (Uma Shankar)

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c      | 6 +++---
 drivers/gpu/drm/i915/display/intel_display_power_well.c | 4 ++--
 drivers/gpu/drm/i915/display/intel_display_regs.h       | 2 +-
 drivers/gpu/drm/i915/display/intel_dmc_wl.c             | 2 +-
 4 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 751e6b7d4a29..c70971ffd9f0 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -267,7 +267,7 @@ sanitize_target_dc_state(struct intel_display *display,
 	static const u32 states[] = {
 		DC_STATE_EN_UPTO_DC6,
 		DC_STATE_EN_UPTO_DC5,
-		DC_STATE_EN_DC3CO,
+		DC_STATE_EN_UPTO_DC3CO,
 		DC_STATE_DISABLE,
 	};
 	int i;
@@ -999,10 +999,10 @@ static u32 get_allowed_dc_mask(struct intel_display *display, int enable_dc)
 
 	switch (requested_dc) {
 	case 4:
-		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
+		mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC6;
 		break;
 	case 3:
-		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
+		mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC5;
 		break;
 	case 2:
 		mask |= DC_STATE_EN_UPTO_DC6;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 2f0d0a77c1a2..611f784d8a7a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -772,7 +772,7 @@ static u32 gen9_dc_mask(struct intel_display *display)
 	mask = DC_STATE_EN_UPTO_DC5;
 
 	if (DISPLAY_VER(display) >= 12)
-		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
+		mask |= DC_STATE_EN_UPTO_DC3CO | DC_STATE_EN_UPTO_DC6
 					  | DC_STATE_EN_DC9;
 	else if (DISPLAY_VER(display) == 11)
 		mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
@@ -1022,7 +1022,7 @@ static void bxt_verify_dpio_phy_power_wells(struct intel_display *display)
 static bool gen9_dc_off_power_well_enabled(struct intel_display *display,
 					   struct i915_power_well *power_well)
 {
-	return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
+	return ((intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC3CO) == 0 &&
 		(intel_de_read(display, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 4321f8b529da..680e7dfdcf1b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -3070,13 +3070,13 @@ enum skl_power_gate {
 /* GEN9 DC */
 #define DC_STATE_EN			_MMIO(0x45504)
 #define  DC_STATE_DISABLE		0
-#define  DC_STATE_EN_DC3CO		REG_BIT(30)
 #define  DC_STATE_DC3CO_STATUS		REG_BIT(29)
 #define  HOLD_PHY_CLKREQ_PG1_LATCH	REG_BIT(21)
 #define  HOLD_PHY_PG1_LATCH		REG_BIT(20)
 #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
 #define  DC_STATE_EN_DC9		(1 << 3)
 #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
+#define  DC_STATE_EN_UPTO_DC3CO		(3 << 0)
 #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
 
 #define  DC_STATE_DEBUG                  _MMIO(0x45520)
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
index b007343721e1..ab4e0e9573df 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
@@ -267,7 +267,7 @@ static bool intel_dmc_wl_check_range(struct intel_display *display,
 	 * the DMC and requires a DC exit for proper access.
 	 */
 	switch (dc_state) {
-	case DC_STATE_EN_DC3CO:
+	case DC_STATE_EN_UPTO_DC3CO:
 		ranges = xe3lpd_dc3co_dmc_ranges;
 		break;
 	case DC_STATE_EN_UPTO_DC5:
-- 
2.43.0

[PATCH v4 03/13] drm/i915/display: Use FIELD_PREP() for DC state enable bits

[Dibin Moolakadan Subrahmanian]

Replace open-coded shifts with REG_GENMASK() and REG_FIELD_PREP()
for the DC state enable field.

Suggested-by: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_regs.h | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index 680e7dfdcf1b..efd1a3e56f76 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -3073,11 +3073,12 @@ enum skl_power_gate {
 #define  DC_STATE_DC3CO_STATUS		REG_BIT(29)
 #define  HOLD_PHY_CLKREQ_PG1_LATCH	REG_BIT(21)
 #define  HOLD_PHY_PG1_LATCH		REG_BIT(20)
-#define  DC_STATE_EN_UPTO_DC5		(1 << 0)
 #define  DC_STATE_EN_DC9		(1 << 3)
-#define  DC_STATE_EN_UPTO_DC6		(2 << 0)
-#define  DC_STATE_EN_UPTO_DC3CO		(3 << 0)
-#define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
+#define  DC_STATE_EN_UPTO_DC5_DC6_MASK   REG_GENMASK(1, 0)
+#define  DC_STATE_EN_DISABLE		REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 0)
+#define  DC_STATE_EN_UPTO_DC5		REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 1)
+#define  DC_STATE_EN_UPTO_DC6		REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 2)
+#define  DC_STATE_EN_UPTO_DC3CO	REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 3)
 
 #define  DC_STATE_DEBUG                  _MMIO(0x45520)
 #define  DC_STATE_DEBUG_MASK_CORES	(1 << 0)
-- 
2.43.0

[PATCH v4 04/13] drm/i915/display: Add DC3CO DC_STATE enable/disable support

[Dibin Moolakadan Subrahmanian]

Add DC3CO handling to the dc_off power well sequencing and disable the
DMC wakelock when exiting DC3CO.

BSpec: 75253
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 .../drm/i915/display/intel_display_power_well.c  | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 611f784d8a7a..3ea080d0e21e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -866,6 +866,13 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
 	power_domains->dc_state = val & mask;
 }
 
+static void xe3lpd_enable_dc3co(struct intel_display *display)
+{
+	drm_dbg_kms(display->drm, "Enabling DC3CO\n");
+	intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC3CO);
+	gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC3CO);
+}
+
 static void assert_can_enable_dc5(struct intel_display *display)
 {
 	enum i915_power_well_id high_pg;
@@ -1054,9 +1061,13 @@ void gen9_disable_dc_states(struct intel_display *display)
 	}
 
 	if (old_state == DC_STATE_EN_UPTO_DC5 ||
-	    old_state == DC_STATE_EN_UPTO_DC6)
+	    old_state == DC_STATE_EN_UPTO_DC6 ||
+	    old_state == DC_STATE_EN_UPTO_DC3CO)
 		intel_dmc_wl_disable(display);
 
+	if (old_state == DC_STATE_EN_UPTO_DC3CO)
+		return;
+
 	intel_cdclk_get_cdclk(display, &cdclk_config);
 	/* Can't read out voltage_level so can't use intel_cdclk_changed() */
 	drm_WARN_ON(display->drm,
@@ -1092,6 +1103,9 @@ static void gen9_dc_off_power_well_disable(struct intel_display *display,
 		return;
 
 	switch (power_domains->target_dc_state) {
+	case DC_STATE_EN_UPTO_DC3CO:
+		xe3lpd_enable_dc3co(display);
+		break;
 	case DC_STATE_EN_UPTO_DC6:
 		skl_enable_dc6(display);
 		break;
-- 
2.43.0

[PATCH v4 05/13] drm/i915/display: Add DC3CO support check

[Dibin Moolakadan Subrahmanian]

Add intel_display_power_dc3co_supported() helper to query DC3CO
support from allowed_dc_mask.

Changes in v2:
- Squash "Add helper to check DC3CO support" patch into this patch

Changes in v4:
- Remove introduced dc state validation,as it may break
  fall back mechanism (sashiko)

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
 drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index c70971ffd9f0..4b91747b38f1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -302,6 +302,7 @@ void intel_display_power_set_target_dc_state(struct intel_display *display,
 	struct i915_power_domains *power_domains = &display->power.domains;
 
 	mutex_lock(&power_domains->lock);
+
 	power_well = lookup_power_well(display, SKL_DISP_DC_OFF);
 
 	if (drm_WARN_ON(display->drm, !power_well))
@@ -358,6 +359,13 @@ u32 intel_display_power_get_current_dc_state(struct intel_display *display)
 	return current_dc_state;
 }
 
+bool intel_display_power_dc3co_supported(struct intel_display *display)
+{
+	struct i915_power_domains *power_domains = &display->power.domains;
+
+	return (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) == DC_STATE_EN_UPTO_DC3CO;
+}
+
 static void __async_put_domains_mask(struct i915_power_domains *power_domains,
 				     struct intel_power_domain_mask *mask)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index d616d5d09cbe..05880e9da89f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -186,6 +186,7 @@ void intel_display_power_resume(struct intel_display *display);
 void intel_display_power_set_target_dc_state(struct intel_display *display,
 					     u32 state);
 u32 intel_display_power_get_current_dc_state(struct intel_display *display);
+bool intel_display_power_dc3co_supported(struct intel_display *display);
 
 bool intel_display_power_is_enabled(struct intel_display *display,
 				    enum intel_display_power_domain domain);
-- 
2.43.0

[PATCH v4 06/13] drm/i915/display: Add HAS_DC3CO() macro

[Dibin Moolakadan Subrahmanian]

Add HAS_DC3CO() to identify platforms supporting DC3CO.
DC3CO is supported from display version 35 onwards.

BSpec: 75253
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_device.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
index 12e5a522a299..f61c930ab079 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.h
+++ b/drivers/gpu/drm/i915/display/intel_display_device.h
@@ -159,6 +159,7 @@ struct intel_display_platforms {
 #define HAS_CUR_FBC(__display)		(!HAS_GMCH(__display) && IS_DISPLAY_VER(__display, 7, 13))
 #define HAS_D12_PLANE_MINIMIZATION(__display)	((__display)->platform.rocketlake || (__display)->platform.alderlake_s)
 #define HAS_DBUF_OVERLAP_DETECTION(__display)	(DISPLAY_RUNTIME_INFO(__display)->has_dbuf_overlap_detection)
+#define HAS_DC3CO(__display)		(DISPLAY_VER(__display) >= 35)
 #define HAS_DDI(__display)		(DISPLAY_INFO(__display)->has_ddi)
 #define HAS_DISPLAY(__display)		(DISPLAY_RUNTIME_INFO(__display)->pipe_mask != 0)
 #define HAS_DMC(__display)		(DISPLAY_RUNTIME_INFO(__display)->has_dmc)
-- 
2.43.0

[PATCH v4 07/13] drm/i915/display: Add DC3CO eligibility computation

[Dibin Moolakadan Subrahmanian]

Compute DC3CO eligibility during atomic_check based on
pipe/port constraints and runtime triggers and store
result in display->power.dc3co.

When DC3CO is allowed, request DC_STATE_EN_UPTO_DC3CO and
reduce the DC entry delay. Otherwise, retain the existing
delay and set default DC_STATE_EN_UPTO_DC6.

Changes in v2:
- Move dc3co state from intel_atomic_state to display->power (Uma Shankar)
- Use #define bitmasks instead of enum for DC3CO triggers (Jani Nikula)

Changes in v3:
- Fix trigger always returning zero in intel_dc3co_compute_state().

Changes in v4:
- Call intel_display_power_set_target_dc_state() only when DC3CO is
  supported.
- For Panel replay DC3CO trigger, add check for as_sdp_supported flag
- Add 1:1 mapping check to intel_dc3co_port_pipe_compatible for
  display version 35.(Uma Shankar,Animesh Manna)
- Add guard for intel_dc3co_compute_state()

BSpec: 75253
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  | 102 +++++++++++++++++-
 .../gpu/drm/i915/display/intel_display_core.h |   3 +-
 .../drm/i915/display/intel_display_power.c    |  30 ++++++
 .../drm/i915/display/intel_display_power.h    |  22 ++++
 4 files changed, 151 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 757a78c75bbf..375ffb329022 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5874,6 +5874,74 @@ static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
 	return false;
 }
 
+static bool intel_dc3co_port_pipe_compatible(struct intel_dp *intel_dp,
+					     const struct intel_crtc_state *crtc_state)
+{
+	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
+	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
+	enum port port = dig_port->base.port;
+	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
+
+	/* Need to follow 1:1 mapping because of CMTG restriction*/
+	if (DISPLAY_VER(to_intel_display(crtc_state)) == 35)
+		return num_pipes == 1 &&
+		       ((pipe == PIPE_A && port == PORT_A) ||
+			(pipe == PIPE_B && port == PORT_B));
+	else
+		return num_pipes == 1 && pipe <= PIPE_B && port <= PORT_B;
+}
+
+static void intel_dc3co_compute_state(struct intel_atomic_state *state)
+{
+	struct intel_display *display = to_intel_display(state);
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *crtc_state;
+	struct intel_encoder *encoder;
+	struct intel_dp *intel_dp;
+	u8 active_pipes = 0;
+	enum pipe pipe;
+	u32 trigger = DC3CO_TRIGGER_NONE;
+
+	if (!HAS_DC3CO(display))
+		return;
+
+	for_each_intel_crtc(display->drm, crtc)
+		active_pipes |= crtc->active ? BIT(crtc->pipe) : 0;
+
+	active_pipes = intel_calc_active_pipes(state, active_pipes);
+
+	if (hweight8(active_pipes) != 1)
+		goto done;
+
+	pipe = ffs(active_pipes) - 1;
+	crtc = intel_crtc_for_pipe(display, pipe);
+
+	crtc_state = to_intel_crtc_state(crtc->base.state);
+
+	for_each_intel_encoder_mask(display->drm, encoder,
+				    crtc_state->uapi.encoder_mask) {
+		if (encoder->type != INTEL_OUTPUT_EDP)
+			goto done;
+
+		intel_dp = enc_to_intel_dp(encoder);
+
+		if (!intel_dc3co_port_pipe_compatible(intel_dp, crtc_state))
+			goto done;
+	}
+
+	if (crtc_state->has_lobf)
+		trigger |= DC3CO_TRIGGER_LOBF;
+	if (crtc_state->has_panel_replay && intel_dp->as_sdp_supported)
+		trigger |= DC3CO_TRIGGER_PANEL_REPLAY;
+	if (crtc_state->has_sel_update)
+		trigger |= DC3CO_TRIGGER_PSR2;
+
+done:
+	intel_display_power_dc3co_update(display, !!trigger, trigger);
+	drm_dbg_kms(display->drm, "DC3CO allowed=%d trigger=0x%x\n",
+		    !!trigger, trigger);
+}
+
 static int intel_atomic_check_joiner(struct intel_atomic_state *state,
 				     struct intel_crtc *primary_crtc)
 {
@@ -6570,6 +6638,9 @@ int intel_atomic_check(struct drm_device *dev,
 				      "modeset" : "fastset");
 	}
 
+	if (intel_display_power_dc3co_supported(display))
+		intel_dc3co_compute_state(state);
+
 	return 0;
 
  fail:
@@ -7421,6 +7492,12 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
 	struct ref_tracker *wakeref = NULL;
 	int i;
+	u32 target_dc_state;
+	/*
+	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
+	 * toggling overhead at and above 60 FPS.
+	 */
+	int power_async_delay = 17;
 
 	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
 		intel_atomic_dsb_prepare(state, crtc);
@@ -7627,11 +7704,26 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		 */
 		intel_uncore_arm_unclaimed_mmio_detection(uncore);
 	}
-	/*
-	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
-	 * toggling overhead at and above 60 FPS.
-	 */
-	intel_display_power_put_async_delay(display, POWER_DOMAIN_DC_OFF, wakeref, 17);
+
+	if (intel_display_power_dc3co_supported(display)) {
+		if (intel_display_power_dc3co_allowed(display)) {
+			/*
+			 * Use minimal re-enable delay to allow DC3CO entry on
+			 * the next idle frame, unlike the 17ms guard needed to
+			 * prevent DC5/DC6 toggling overhead at 60+ FPS.
+			 */
+			power_async_delay = 1;
+			target_dc_state = DC_STATE_EN_UPTO_DC3CO;
+		} else {
+			target_dc_state = DC_STATE_EN_UPTO_DC6;
+		}
+
+		intel_display_power_set_target_dc_state(display, target_dc_state);
+	}
+
+	intel_display_power_put_async_delay(display,
+					    POWER_DOMAIN_DC_OFF, wakeref, power_async_delay);
+
 	intel_display_rpm_put(display, state->wakeref);
 
 	/*
diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
index 3dc5ac75a98b..e24accf473d7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_core.h
+++ b/drivers/gpu/drm/i915/display/intel_display_core.h
@@ -537,7 +537,8 @@ struct intel_display {
 
 	struct {
 		struct i915_power_domains domains;
-
+		/* DC3CO eligibility state */
+		struct intel_dc3co_state dc3co;
 		/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
 		u32 chv_phy_control;
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 4b91747b38f1..b0f40e4233c8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -366,6 +366,35 @@ bool intel_display_power_dc3co_supported(struct intel_display *display)
 	return (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) == DC_STATE_EN_UPTO_DC3CO;
 }
 
+void intel_display_power_dc3co_update(struct intel_display *display,
+				      bool allowed, u32 trigger)
+{
+	struct intel_dc3co_state *dc3co = &display->power.dc3co;
+
+	if (!HAS_DC3CO(display))
+		return;
+
+	mutex_lock(&dc3co->lock);
+	dc3co->allowed = allowed;
+	dc3co->trigger = trigger;
+	mutex_unlock(&dc3co->lock);
+}
+
+bool intel_display_power_dc3co_allowed(struct intel_display *display)
+{
+	struct intel_dc3co_state *dc3co = &display->power.dc3co;
+	bool allowed;
+
+	if (!HAS_DC3CO(display))
+		return false;
+
+	mutex_lock(&dc3co->lock);
+	allowed = dc3co->allowed;
+	mutex_unlock(&dc3co->lock);
+
+	return allowed;
+}
+
 static void __async_put_domains_mask(struct i915_power_domains *power_domains,
 				     struct intel_power_domain_mask *mask)
 {
@@ -1045,6 +1074,7 @@ int intel_power_domains_init(struct intel_display *display)
 		sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
 
 	mutex_init(&power_domains->lock);
+	mutex_init(&display->power.dc3co.lock);
 
 	INIT_DELAYED_WORK(&power_domains->async_put_work,
 			  intel_display_power_put_async_work);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 05880e9da89f..0b1a06f88ae5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -131,6 +131,25 @@ struct intel_power_domain_mask {
 	DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);
 };
 
+/*
+ * DC3CO enabling triggers (bitmask).
+ * DC3CO may be enabled when at least one of these triggers is active.
+ * Additional constraints may still apply.
+ */
+#define DC3CO_TRIGGER_NONE		(0)
+#define DC3CO_TRIGGER_PSR2		BIT(0)
+#define DC3CO_TRIGGER_LOBF		BIT(1)
+#define DC3CO_TRIGGER_PANEL_REPLAY	BIT(2)
+#define DC3CO_TRIGGER_ALL		(DC3CO_TRIGGER_PSR2 | \
+					 DC3CO_TRIGGER_LOBF | \
+					 DC3CO_TRIGGER_PANEL_REPLAY)
+
+struct intel_dc3co_state {
+	struct mutex lock; /* Protects allowed and trigger fields */
+	bool allowed; /* DC3CO eligibility result */
+	u32 trigger; /* Bitmask of active DC3CO triggers */
+};
+
 struct i915_power_domains {
 	/*
 	 * Power wells needed for initialization at driver init and suspend
@@ -187,6 +206,9 @@ void intel_display_power_set_target_dc_state(struct intel_display *display,
 					     u32 state);
 u32 intel_display_power_get_current_dc_state(struct intel_display *display);
 bool intel_display_power_dc3co_supported(struct intel_display *display);
+void intel_display_power_dc3co_update(struct intel_display *display,
+				      bool allowed, u32 trigger);
+bool intel_display_power_dc3co_allowed(struct intel_display *display);
 
 bool intel_display_power_is_enabled(struct intel_display *display,
 				    enum intel_display_power_domain domain);
-- 
2.43.0

[PATCH v4 08/13] drm/i915/display: Store DC3CO eligibility in PSR state

[Dibin Moolakadan Subrahmanian]

Store DC3CO eligibility in intel_dp->psr during
intel_psr_post_plane_update() so PSR configuration
can take DC3CO into account.

This will be used to control PSR2 parameters such as idle frames.

Changes in v2:
- Use intel_display_power_dc3co_allowed(display) instead
  of intel_dc3co_allowed(state)

Changes in v4:
- Update psr.dc3co_eligible before
  intel_psr_enable_locked() call (sashiko)

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_types.h | 2 ++
 drivers/gpu/drm/i915/display/intel_psr.c           | 7 +++++++
 2 files changed, 9 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 1cfc585530dc..c21f5d1e2003 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1770,6 +1770,8 @@ struct intel_psr {
 	ktime_t last_exit;
 	bool sink_not_reliable;
 	bool irq_aux_error;
+	/* DC3CO eligibility used to control PSR configuration */
+	bool dc3co_eligible;
 	u16 su_w_granularity;
 	u16 su_y_granularity;
 	bool source_panel_replay_support;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 730ca7af7873..d4b294beecef 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2300,6 +2300,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 	intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
 	intel_dp->psr.active_non_psr_pipes = 0;
 	intel_dp->psr.pkg_c_latency_used = 0;
+	intel_dp->psr.dc3co_eligible = false;
 }
 
 /**
@@ -3090,10 +3091,14 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
 	const struct intel_crtc_state *crtc_state =
 		intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_encoder *encoder;
+	bool dc3co_eligible;
 
 	if (!crtc_state->has_psr)
 		return;
 
+	dc3co_eligible = intel_display_power_dc3co_allowed(display) &&
+			      intel_display_power_dc3co_supported(display);
+
 	verify_panel_replay_dsc_state(crtc_state);
 
 	for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
@@ -3121,6 +3126,8 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
 			keep_disabled = true;
 		}
 
+		intel_dp->psr.dc3co_eligible = dc3co_eligible;
+
 		if (!psr->enabled && !keep_disabled)
 			intel_psr_enable_locked(intel_dp, crtc_state);
 		else if (psr->enabled && !crtc_state->wm_level_disabled)
-- 
2.43.0

[PATCH v4 09/13] drm/i915/display: PSR2: Set idle_frames to 0 for DC3CO

[Dibin Moolakadan Subrahmanian]

Force idle_frames to 0 when DC3CO is eligible.

Changes in v2:
- Extend existing Wa_16025596647 condition
  instead of adding a new if block (Uma Shankar)

BSpec: 75253
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index d4b294beecef..b4ce3d49d76e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1079,10 +1079,11 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
 	u32 psr_val = 0;
 	u8 idle_frames;
 
-	/* Wa_16025596647 */
-	if ((DISPLAY_VER(display) == 20 ||
-	     IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
-	    is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used)
+	/* DC3CO / Wa_16025596647 */
+	if (intel_dp->psr.dc3co_eligible ||
+	    ((DISPLAY_VER(display) == 20 ||
+	      IS_DISPLAY_VERx100_STEP(display, 3000, STEP_A0, STEP_B0)) &&
+	     is_dc5_dc6_blocked(intel_dp) && intel_dp->psr.pkg_c_latency_used))
 		idle_frames = 0;
 	else
 		idle_frames = psr_compute_idle_frames(intel_dp);
-- 
2.43.0

[PATCH v4 10/13] drm/i915/display: Enable DC3CO idle protocol in ALPM

[Dibin Moolakadan Subrahmanian]

Add PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL bit definition and set it
when DC3CO is allowed.

Changes in v2:
- Squash "Define DC3CO idle protocol bit in PR_ALPM_CTL"
  into this patch (Uma Shankar)
- Use intel_display_power_dc3co_allowed(display)
  instead of intel_dc3co_allowed(state)

BSpec: 75253
Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_alpm.c     | 6 ++++++
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_alpm.c b/drivers/gpu/drm/i915/display/intel_alpm.c
index a7350ce8e716..6394d1568b54 100644
--- a/drivers/gpu/drm/i915/display/intel_alpm.c
+++ b/drivers/gpu/drm/i915/display/intel_alpm.c
@@ -389,6 +389,12 @@ static void lnl_alpm_configure(struct intel_dp *intel_dp,
 			if (crtc_state->disable_as_sdp_when_pr_active)
 				pr_alpm_ctl |= PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE;
 
+			if (intel_display_power_dc3co_allowed(display) &&
+			    intel_display_power_dc3co_supported(display))
+				pr_alpm_ctl |= PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
+			else
+				pr_alpm_ctl &= ~PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL;
+
 			intel_de_write(display, PR_ALPM_CTL(display, cpu_transcoder),
 				       pr_alpm_ctl);
 		}
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 8afbf5a38335..16a9e3af198d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -268,6 +268,7 @@
 
 #define _PR_ALPM_CTL_A	0x60948
 #define PR_ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _PR_ALPM_CTL_A)
+#define  PR_ALPM_CTL_USE_DC3CO_IDLE_PROTOCOL			BIT(7)
 #define  PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU	BIT(6)
 #define  PR_ALPM_CTL_RFB_UPDATE_CONTROL				BIT(5)
 #define  PR_ALPM_CTL_AS_SDP_TRANSMISSION_IN_ACTIVE_DISABLE	BIT(4)
-- 
2.43.0

[PATCH v4 11/13] drm/i915/display: PSR Add delayed work to exit DC3CO

[Dibin Moolakadan Subrahmanian]

For DC3CO, idle_frames is programmed to 0, so PSR does not
enter deep sleep. Add delayed work to schedule DC3CO exit
after an idle duration derived from frame time (minimum
equivalent of 6 frames).

The work is re-armed from the PSR flush path on relevant frontbuffer
activity. Once the display remains idle, DC3CO is disabled, idle frames
are reprogrammed to their normal value, and DC6 is enabled to allow
deeper power savings.

Changes in v2:
- Squash "PSR set idle frames while exit from DC3CO"
  into this patch (Uma Shankar)
- Add cancel_delayed_work() in intel_psr_disable_locked()
  before clearing dc3co_eligible (Uma Shankar)

Changes in v4:
- Re-arm cancelled DC3CO work in psr resume
- Schedule DC3CO work from intel_psr_post_plane_update(). This is to
  make sure DC3CO work scheduling will happen even without psr flush,
  which may be a valid scenario.

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  2 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 62 ++++++++++++++++++-
 2 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index c21f5d1e2003..decbda47f65c 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1772,6 +1772,8 @@ struct intel_psr {
 	bool irq_aux_error;
 	/* DC3CO eligibility used to control PSR configuration */
 	bool dc3co_eligible;
+	/* DC3CO disable work */
+	struct delayed_work dc3co_work;
 	u16 su_w_granularity;
 	u16 su_y_granularity;
 	bool source_panel_replay_support;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index b4ce3d49d76e..ceb0f615754e 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -1765,6 +1765,51 @@ static bool intel_psr_needs_wa_18037818876(struct intel_dp *intel_dp,
 		!crtc_state->has_sel_update);
 }
 
+static void psr2_dc3co_disable_locked(struct intel_dp *intel_dp)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	if (intel_dp->psr.dc3co_eligible) {
+		intel_dp->psr.dc3co_eligible = false;
+		intel_display_power_set_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
+		psr2_program_idle_frames(intel_dp, psr_compute_idle_frames(intel_dp));
+	}
+}
+
+static void psr2_dc3co_disable_work(struct work_struct *work)
+{
+	struct intel_dp *intel_dp =
+		container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
+
+	mutex_lock(&intel_dp->psr.lock);
+	psr2_dc3co_disable_locked(intel_dp);
+	mutex_unlock(&intel_dp->psr.lock);
+}
+
+static void
+psr2_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int frontbuffer_bits,
+			enum fb_op_origin origin)
+{
+	struct intel_display *display = to_intel_display(intel_dp);
+
+	if (!intel_dp->psr.dc3co_eligible)
+		return;
+
+	if (!intel_dp->psr.sel_update_enabled ||
+	    !intel_dp->psr.active)
+		return;
+	/*
+	 * At every frontbuffer flush flip event modified delay of delayed work,
+	 * when delayed work schedules that means display has been idle.
+	 */
+	if (!(frontbuffer_bits &
+	    INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
+		return;
+
+	mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work,
+			 intel_dp->psr.dc3co_exit_delay);
+}
+
 static
 void intel_psr_set_non_psr_pipes(struct intel_dp *intel_dp,
 				 struct intel_crtc_state *crtc_state)
@@ -2301,6 +2346,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
 	intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
 	intel_dp->psr.active_non_psr_pipes = 0;
 	intel_dp->psr.pkg_c_latency_used = 0;
+	cancel_delayed_work(&intel_dp->psr.dc3co_work);
 	intel_dp->psr.dc3co_eligible = false;
 }
 
@@ -2331,6 +2377,7 @@ void intel_psr_disable(struct intel_dp *intel_dp,
 
 	mutex_unlock(&intel_dp->psr.lock);
 	cancel_work_sync(&intel_dp->psr.work);
+	cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
 }
 
 /**
@@ -2361,6 +2408,7 @@ void intel_psr_pause(struct intel_dp *intel_dp)
 	mutex_unlock(&psr->lock);
 
 	cancel_work_sync(&psr->work);
+	cancel_delayed_work_sync(&psr->dc3co_work);
 }
 
 /**
@@ -2387,8 +2435,13 @@ void intel_psr_resume(struct intel_dp *intel_dp)
 		goto out;
 	}
 
-	if (--intel_dp->psr.pause_counter == 0)
+	if (--intel_dp->psr.pause_counter == 0) {
 		intel_psr_activate(intel_dp);
+		/* re-arm cancelled dc3c3o work from pause*/
+		if (intel_dp->psr.dc3co_eligible)
+			mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work,
+					 intel_dp->psr.dc3co_exit_delay);
+	}
 
 out:
 	mutex_unlock(&psr->lock);
@@ -3145,6 +3198,11 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
 		 */
 		intel_dp->psr.busy_frontbuffer_bits = 0;
 
+		if (intel_dp->psr.dc3co_eligible) {
+			mod_delayed_work(display->wq.unordered, &intel_dp->psr.dc3co_work,
+					 intel_dp->psr.dc3co_exit_delay);
+		}
+
 		mutex_unlock(&psr->lock);
 	}
 }
@@ -3603,6 +3661,7 @@ void intel_psr_flush(struct intel_display *display,
 		if (origin == ORIGIN_FLIP ||
 		    (origin == ORIGIN_CURSOR_UPDATE &&
 		     !intel_dp->psr.psr2_sel_fetch_enabled)) {
+			psr2_dc3co_flush_locked(intel_dp, frontbuffer_bits, origin);
 			goto unlock;
 		}
 
@@ -3661,6 +3720,7 @@ void intel_psr_init(struct intel_dp *intel_dp)
 		intel_dp->psr.link_standby = connector->panel.vbt.psr.full_link;
 
 	INIT_WORK(&intel_dp->psr.work, intel_psr_work);
+	INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work, psr2_dc3co_disable_work);
 	mutex_init(&intel_dp->psr.lock);
 }
 
-- 
2.43.0

[PATCH v4 12/13] drm/i915/display: Add helper to enable DC counter

[Dibin Moolakadan Subrahmanian]

Add xe3lpd_enable_dc_count() to enable the DC_COUNT_EN register.
Also define DC_STATE_DC3CO_RESIDENCY to read DC3CO residency.
Needed to retrieve DC residency for DC3CO.

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display_power_well.c | 5 +++++
 drivers/gpu/drm/i915/display/intel_display_power_well.h | 1 +
 drivers/gpu/drm/i915/display/intel_display_regs.h       | 5 +++++
 drivers/gpu/drm/i915/display/intel_dmc.c                | 3 +++
 4 files changed, 14 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 3ea080d0e21e..0e7e6a2b1547 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -866,6 +866,11 @@ void gen9_set_dc_state(struct intel_display *display, u32 state)
 	power_domains->dc_state = val & mask;
 }
 
+void xe3lpd_enable_dc_count(struct intel_display *display)
+{
+	intel_de_write(display, DC_COUNT_EN, DC_COUNT_EN_COUNTER_ENABLE);
+}
+
 static void xe3lpd_enable_dc3co(struct intel_display *display)
 {
 	drm_dbg_kms(display->drm, "Enabling DC3CO\n");
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index 8f5524da2d06..0ce64b894436 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -159,6 +159,7 @@ void gen9_set_dc_state(struct intel_display *display, u32 state);
 void gen9_disable_dc_states(struct intel_display *display);
 void bxt_enable_dc9(struct intel_display *display);
 void bxt_disable_dc9(struct intel_display *display);
+void xe3lpd_enable_dc_count(struct intel_display *display);
 
 extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
 extern const struct i915_power_well_ops chv_pipe_power_well_ops;
diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h
index efd1a3e56f76..875cd06f2566 100644
--- a/drivers/gpu/drm/i915/display/intel_display_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
@@ -3084,6 +3084,11 @@ enum skl_power_gate {
 #define  DC_STATE_DEBUG_MASK_CORES	(1 << 0)
 #define  DC_STATE_DEBUG_MASK_MEMORY_UP	(1 << 1)
 
+#define DC_COUNT_EN			_MMIO(0x457B4)
+#define DC_COUNT_EN_COUNTER_ENABLE	REG_BIT(31)
+
+#define DC_STATE_DC3CO_RESIDENCY	_MMIO(0x457B8)
+
 #define D_COMP_BDW			_MMIO(0x138144)
 
 /* Pipe WM_LINETIME - watermark line time */
diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index 4785001644f5..a133785c815b 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -941,6 +941,9 @@ void intel_dmc_load_program(struct intel_display *display)
 
 	gen9_set_dc_state_debugmask(display);
 
+	if (DISPLAY_VER(display) >= 35)
+		xe3lpd_enable_dc_count(display);
+
 	pipedmc_clock_gating_wa(display, false);
 }
 
-- 
2.43.0

[PATCH v4 13/13] drm/i915/display: Add DC3CO count and residency in dmc debugfs

[Dibin Moolakadan Subrahmanian]

Expose DC3CO count and residency for xe3lp platforms via debugfs.

Changes in v4:
- Keep dc5_reg register initialization to avoid any
  invalid access (sashiko)

Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dmc.c      | 9 ++++++++-
 drivers/gpu/drm/i915/display/intel_dmc_regs.h | 2 ++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c b/drivers/gpu/drm/i915/display/intel_dmc.c
index a133785c815b..5ffe2b1c3c51 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc.c
+++ b/drivers/gpu/drm/i915/display/intel_dmc.c
@@ -1650,7 +1650,14 @@ static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused)
 		   DMC_VERSION_MINOR(dmc->version));
 
 	if (DISPLAY_VER(display) >= 12) {
-		if (display->platform.dgfx || DISPLAY_VER(display) >= 14) {
+		if (DISPLAY_VER(display) >= 35) {
+			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
+			seq_printf(m, "DC3CO count: %d\n",
+				   intel_de_read(display, XE3P_DMC_DC3CO_COUNT));
+
+			seq_printf(m, "DC3CO residency: %d\n",
+				   intel_de_read(display, DC_STATE_DC3CO_RESIDENCY));
+		} else if (display->platform.dgfx || DISPLAY_VER(display) >= 14) {
 			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
 		} else {
 			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
index 38e342b45af0..1998549b6318 100644
--- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
@@ -531,6 +531,8 @@ enum pipedmc_event_id {
 #define TGL_DMC_DEBUG3		_MMIO(0x101090)
 #define DG1_DMC_DEBUG3		_MMIO(0x13415c)
 
+#define XE3P_DMC_DC3CO_COUNT	_MMIO(0x8f05C)
+
 #define DMC_WAKELOCK_CFG	_MMIO(0x8F1B0)
 #define  DMC_WAKELOCK_CFG_ENABLE REG_BIT(31)
 #define DMC_WAKELOCK1_CTL	_MMIO(0x8F140)
-- 
2.43.0

✓ i915.CI.BAT: success for drm/i915/display: Add DC3CO support (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 2748 bytes --]

== Series Details ==

Series: drm/i915/display: Add DC3CO support (rev4)
URL   : https://patchwork.freedesktop.org/series/163939/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_18556 -> Patchwork_163939v4
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/index.html

Participating hosts (42 -> 40)
------------------------------

  Missing    (2): bat-dg2-13 fi-snb-2520m 

New tests
---------

  New tests have been introduced between CI_DRM_18556 and Patchwork_163939v4:

### New IGT tests (15) ###

  * igt@kms_flip@basic-flip-vs-dpms@c-vga1:
    - Statuses : 2 pass(s)
    - Exec time: [0.91] s

  * igt@kms_flip@basic-flip-vs-modeset@c-vga1:
    - Statuses : 2 pass(s)
    - Exec time: [0.95] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-hdmi-a1:
    - Statuses : 7 pass(s)
    - Exec time: [0.83, 1.59] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-hdmi-a2:
    - Statuses : 4 pass(s)
    - Exec time: [1.05, 1.27] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@a-vga1:
    - Statuses : 5 pass(s)
    - Exec time: [1.09, 1.89] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@b-hdmi-a1:
    - Statuses : 7 pass(s)
    - Exec time: [0.80, 1.45] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@b-hdmi-a2:
    - Statuses : 4 pass(s)
    - Exec time: [1.02, 1.20] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@b-vga1:
    - Statuses : 5 pass(s)
    - Exec time: [1.00, 1.78] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a1:
    - Statuses : 6 pass(s)
    - Exec time: [0.81, 1.45] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-hdmi-a2:
    - Statuses : 5 pass(s)
    - Exec time: [1.03, 2.83] s

  * igt@kms_flip@basic-flip-vs-wf_vblank@c-vga1:
    - Statuses : 2 pass(s)
    - Exec time: [1.15, 1.17] s

  * igt@kms_flip@basic-plain-flip@a-hdmi-a2:
    - Statuses : 4 pass(s)
    - Exec time: [0.79, 0.87] s

  * igt@kms_flip@basic-plain-flip@b-hdmi-a2:
    - Statuses : 4 pass(s)
    - Exec time: [0.74, 0.80] s

  * igt@kms_flip@basic-plain-flip@c-hdmi-a2:
    - Statuses : 5 pass(s)
    - Exec time: [0.75, 2.71] s

  * igt@kms_flip@basic-plain-flip@c-vga1:
    - Statuses : 2 pass(s)
    - Exec time: [0.86, 0.88] s

  


Changes
-------

  No changes found


Build changes
-------------

  * Linux: CI_DRM_18556 -> Patchwork_163939v4

  CI-20190529: 20190529
  CI_DRM_18556: 1e5fbf0d628cd02dced6cfb1ebe39717f121fb4c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8937: 8937
  Patchwork_163939v4: 1e5fbf0d628cd02dced6cfb1ebe39717f121fb4c @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/index.html

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✗ i915.CI.Full: failure for drm/i915/display: Add DC3CO support (rev4)

[Patchwork]

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== Series Details ==

Series: drm/i915/display: Add DC3CO support (rev4)
URL   : https://patchwork.freedesktop.org/series/163939/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_18556_full -> Patchwork_163939v4_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_163939v4_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_163939v4_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_163939v4_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_eio@in-flight-suspend:
    - shard-snb:          [PASS][1] -> [DMESG-WARN][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-snb7/igt@gem_eio@in-flight-suspend.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-snb6/igt@gem_eio@in-flight-suspend.html

  
#### Warnings ####

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-mtlp:         [SKIP][3] ([i915#15740]) -> [SKIP][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-mtlp-6/igt@kms_pm_dc@dc3co-vpb-simulation.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-mtlp-6/igt@kms_pm_dc@dc3co-vpb-simulation.html

  
New tests
---------

  New tests have been introduced between CI_DRM_18556_full and Patchwork_163939v4_full:

### New IGT tests (10) ###

  * igt@kms_flip@2x-absolute-wf_vblank-interruptible@ab-hdmi-a1-hdmi-a2:
    - Statuses : 1 pass(s)
    - Exec time: [11.00] s

  * igt@kms_flip@2x-absolute-wf_vblank-interruptible@ac-hdmi-a1-hdmi-a2:
    - Statuses : 1 pass(s)
    - Exec time: [10.91] s

  * igt@kms_flip@2x-absolute-wf_vblank-interruptible@bc-hdmi-a1-hdmi-a2:
    - Statuses : 1 pass(s)
    - Exec time: [10.97] s

  * igt@kms_flip@2x-dpms-vs-vblank-race-interruptible@ab-hdmi-a1-hdmi-a2:
    - Statuses : 1 pass(s)
    - Exec time: [4.82] s

  * igt@kms_flip@2x-dpms-vs-vblank-race-interruptible@ac-hdmi-a1-hdmi-a2:
    - Statuses : 1 pass(s)
    - Exec time: [4.42] s

  * igt@kms_flip@2x-dpms-vs-vblank-race-interruptible@bc-hdmi-a1-hdmi-a2:
    - Statuses : 1 pass(s)
    - Exec time: [4.30] s

  * igt@kms_flip@flip-vs-fences-interruptible@a-hdmi-a2:
    - Statuses : 2 pass(s)
    - Exec time: [5.41, 10.21] s

  * igt@kms_flip@flip-vs-fences-interruptible@b-hdmi-a2:
    - Statuses : 2 pass(s)
    - Exec time: [5.41, 10.15] s

  * igt@kms_flip@flip-vs-fences-interruptible@c-hdmi-a2:
    - Statuses : 2 pass(s)
    - Exec time: [5.40, 10.13] s

  * igt@perf@blocking@1-vecs0:
    - Statuses : 1 pass(s)
    - Exec time: [10.02] s

  

Known issues
------------

  Here are the changes found in Patchwork_163939v4_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@dmabuf@all-tests:
    - shard-tglu:         NOTRUN -> [SKIP][5] ([i915#15931])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@dmabuf@all-tests.html

  * igt@gem_basic@multigpu-create-close:
    - shard-tglu:         NOTRUN -> [SKIP][6] ([i915#7697])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@gem_basic@multigpu-create-close.html

  * igt@gem_ccs@ctrl-surf-copy:
    - shard-rkl:          NOTRUN -> [SKIP][7] ([i915#3555] / [i915#9323])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_ccs@ctrl-surf-copy.html

  * igt@gem_ccs@large-ctrl-surf-copy:
    - shard-tglu-1:       NOTRUN -> [SKIP][8] ([i915#13008])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@gem_ccs@large-ctrl-surf-copy.html

  * igt@gem_ccs@suspend-resume:
    - shard-tglu:         NOTRUN -> [SKIP][9] ([i915#9323])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@gem_ccs@suspend-resume.html

  * igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0:
    - shard-dg2:          [PASS][10] -> [INCOMPLETE][11] ([i915#13356])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-1/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-4/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0.html

  * igt@gem_close_race@multigpu-basic-process:
    - shard-rkl:          NOTRUN -> [SKIP][12] ([i915#7697])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@gem_close_race@multigpu-basic-process.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-tglu-1:       NOTRUN -> [SKIP][13] ([i915#7697])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_ctx_persistence@engines-mixed-process:
    - shard-snb:          NOTRUN -> [SKIP][14] ([i915#1099])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-snb4/igt@gem_ctx_persistence@engines-mixed-process.html

  * igt@gem_ctx_persistence@heartbeat-hostile:
    - shard-dg2:          NOTRUN -> [SKIP][15] ([i915#8555])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-8/igt@gem_ctx_persistence@heartbeat-hostile.html

  * igt@gem_eio@in-flight-suspend:
    - shard-glk11:        NOTRUN -> [INCOMPLETE][16] ([i915#13390])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk11/igt@gem_eio@in-flight-suspend.html

  * igt@gem_eio@suspend:
    - shard-dg2:          [PASS][17] -> [ABORT][18] ([i915#15131])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-6/igt@gem_eio@suspend.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-10/igt@gem_eio@suspend.html

  * igt@gem_exec_balancer@parallel-dmabuf-import-out-fence:
    - shard-tglu-1:       NOTRUN -> [SKIP][19] ([i915#4525])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@gem_exec_balancer@parallel-dmabuf-import-out-fence.html

  * igt@gem_exec_balancer@parallel-ordering:
    - shard-rkl:          NOTRUN -> [SKIP][20] ([i915#4525]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_exec_balancer@parallel-ordering.html

  * igt@gem_exec_capture@capture-invisible@smem0:
    - shard-glk:          NOTRUN -> [SKIP][21] ([i915#6334]) +1 other test skip
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk5/igt@gem_exec_capture@capture-invisible@smem0.html

  * igt@gem_exec_capture@capture-recoverable:
    - shard-rkl:          NOTRUN -> [SKIP][22] ([i915#6344])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@gem_exec_capture@capture-recoverable.html

  * igt@gem_exec_fence@concurrent:
    - shard-dg2:          NOTRUN -> [SKIP][23] ([i915#4812])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_exec_fence@concurrent.html

  * igt@gem_exec_flush@basic-uc-set-default:
    - shard-dg2:          NOTRUN -> [SKIP][24] ([i915#3539])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_exec_flush@basic-uc-set-default.html

  * igt@gem_exec_reloc@basic-wc:
    - shard-rkl:          NOTRUN -> [SKIP][25] ([i915#3281]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_exec_reloc@basic-wc.html

  * igt@gem_exec_reloc@basic-write-wc-active:
    - shard-dg2:          NOTRUN -> [SKIP][26] ([i915#3281]) +2 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_exec_reloc@basic-write-wc-active.html

  * igt@gem_exec_schedule@preempt-queue-contexts-chain:
    - shard-dg2:          NOTRUN -> [SKIP][27] ([i915#4537] / [i915#4812])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_exec_schedule@preempt-queue-contexts-chain.html

  * igt@gem_exec_suspend@basic-s3-devices:
    - shard-dg1:          [PASS][28] -> [DMESG-WARN][29] ([i915#4423]) +4 other tests dmesg-warn
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-16/igt@gem_exec_suspend@basic-s3-devices.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-13/igt@gem_exec_suspend@basic-s3-devices.html

  * igt@gem_fence_thrash@bo-copy:
    - shard-dg2:          NOTRUN -> [SKIP][30] ([i915#4860])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_fence_thrash@bo-copy.html

  * igt@gem_lmem_swapping@parallel-random-verify:
    - shard-rkl:          NOTRUN -> [SKIP][31] ([i915#4613]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@gem_lmem_swapping@parallel-random-verify.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][32] ([i915#4613]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_lmem_swapping@random:
    - shard-glk:          NOTRUN -> [SKIP][33] ([i915#4613]) +2 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk2/igt@gem_lmem_swapping@random.html

  * igt@gem_lmem_swapping@smem-oom:
    - shard-tglu:         NOTRUN -> [SKIP][34] ([i915#4613]) +1 other test skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@gem_lmem_swapping@smem-oom.html

  * igt@gem_mmap_gtt@fault-concurrent-y:
    - shard-dg2:          NOTRUN -> [SKIP][35] ([i915#4077]) +5 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_mmap_gtt@fault-concurrent-y.html

  * igt@gem_mmap_wc@invalid-flags:
    - shard-dg2:          NOTRUN -> [SKIP][36] ([i915#4083]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_mmap_wc@invalid-flags.html

  * igt@gem_partial_pwrite_pread@reads-uncached:
    - shard-rkl:          NOTRUN -> [SKIP][37] ([i915#3282]) +4 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_partial_pwrite_pread@reads-uncached.html

  * igt@gem_pread@display:
    - shard-dg2:          NOTRUN -> [SKIP][38] ([i915#3282])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_pread@display.html

  * igt@gem_pread@exhaustion:
    - shard-tglu-1:       NOTRUN -> [WARN][39] ([i915#2658])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@gem_pread@exhaustion.html

  * igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
    - shard-rkl:          NOTRUN -> [SKIP][40] ([i915#4270])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html

  * igt@gem_pxp@fail-invalid-protected-context:
    - shard-dg2:          NOTRUN -> [SKIP][41] ([i915#4270])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_pxp@fail-invalid-protected-context.html

  * igt@gem_pxp@hw-rejects-pxp-buffer:
    - shard-rkl:          NOTRUN -> [SKIP][42] ([i915#13717])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_pxp@hw-rejects-pxp-buffer.html

  * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][43] ([i915#5190] / [i915#8428]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled.html

  * igt@gem_softpin@noreloc-s3:
    - shard-rkl:          [PASS][44] -> [INCOMPLETE][45] ([i915#13809] / [i915#16226])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-2/igt@gem_softpin@noreloc-s3.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@gem_softpin@noreloc-s3.html

  * igt@gem_userptr_blits@coherency-unsync:
    - shard-rkl:          NOTRUN -> [SKIP][46] ([i915#3297]) +2 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_userptr_blits@coherency-unsync.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-tglu-1:       NOTRUN -> [SKIP][47] ([i915#3297]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-glk:          NOTRUN -> [SKIP][48] ([i915#3323])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk3/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
    - shard-dg2:          NOTRUN -> [SKIP][49] ([i915#3297] / [i915#4880])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-dg2:          NOTRUN -> [SKIP][50] ([i915#2856])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-glk:          NOTRUN -> [ABORT][51] ([i915#5566])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk3/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@bb-large:
    - shard-tglu-1:       NOTRUN -> [SKIP][52] ([i915#2527] / [i915#2856])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@gen9_exec_parse@bb-large.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-tglu:         NOTRUN -> [SKIP][53] ([i915#2527] / [i915#2856]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@gen9_exec_parse@shadow-peek.html

  * igt@i915_module_load@reload-no-display:
    - shard-tglu-1:       NOTRUN -> [DMESG-WARN][54] ([i915#13029] / [i915#14545])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@i915_module_load@reload-no-display.html

  * igt@i915_pm_freq_api@freq-reset-multiple:
    - shard-tglu:         NOTRUN -> [SKIP][55] ([i915#8399]) +1 other test skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@i915_pm_freq_api@freq-reset-multiple.html

  * igt@i915_pm_freq_api@freq-suspend:
    - shard-tglu-1:       NOTRUN -> [SKIP][56] ([i915#8399])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@i915_pm_freq_api@freq-suspend.html

  * igt@i915_power@sanity:
    - shard-mtlp:         [PASS][57] -> [SKIP][58] ([i915#7984])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-mtlp-6/igt@i915_power@sanity.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-mtlp-6/igt@i915_power@sanity.html

  * igt@i915_query@test-query-geometry-subslices:
    - shard-rkl:          NOTRUN -> [SKIP][59] ([i915#5723])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@i915_query@test-query-geometry-subslices.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-glk:          NOTRUN -> [INCOMPLETE][60] ([i915#16182] / [i915#4817]) +1 other test incomplete
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk6/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@i915_suspend@forcewake:
    - shard-rkl:          [PASS][61] -> [INCOMPLETE][62] ([i915#4817])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@i915_suspend@forcewake.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@i915_suspend@forcewake.html

  * igt@intel_hwmon@hwmon-read:
    - shard-tglu:         NOTRUN -> [SKIP][63] ([i915#7707])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@intel_hwmon@hwmon-read.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-rkl:          NOTRUN -> [SKIP][64] ([i915#12454] / [i915#12712])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-snb:          NOTRUN -> [SKIP][65] ([i915#1769])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-snb4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1:
    - shard-tglu:         [PASS][66] -> [FAIL][67] ([i915#15662]) +1 other test fail
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-tglu-2/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-4/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-90:
    - shard-dg2:          NOTRUN -> [SKIP][68] +4 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-8/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
    - shard-tglu:         NOTRUN -> [SKIP][69] ([i915#5286]) +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-rkl:          NOTRUN -> [SKIP][70] ([i915#5286]) +3 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-tglu-1:       NOTRUN -> [SKIP][71] ([i915#5286]) +2 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-mtlp:         [PASS][72] -> [FAIL][73] ([i915#15733] / [i915#5138])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-mtlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-mtlp-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][74] ([i915#3638]) +2 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-rkl:          NOTRUN -> [SKIP][75] ([i915#3828]) +1 other test skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-4/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-180:
    - shard-dg2:          NOTRUN -> [SKIP][76] ([i915#4538] / [i915#5190])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-1:
    - shard-glk11:        NOTRUN -> [SKIP][77] +91 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk11/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-c-hdmi-a-2:
    - shard-glk10:        NOTRUN -> [SKIP][78] +77 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk10/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][79] ([i915#14544] / [i915#6095]) +3 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][80] ([i915#6095]) +175 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-16/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][81] ([i915#14098] / [i915#14544] / [i915#6095]) +1 other test skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][82] ([i915#10307] / [i915#6095]) +89 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][83] ([i915#12313])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][84] ([i915#6095]) +44 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][85] ([i915#14098] / [i915#6095]) +38 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][86] ([i915#12805])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [ABORT][87] ([i915#15132])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [INCOMPLETE][88] ([i915#15582] / [i915#16205]) +1 other test incomplete
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk8/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-b-dp-3:
    - shard-dg2:          NOTRUN -> [SKIP][89] ([i915#6095]) +3 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-10/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-b-dp-3.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][90] ([i915#6095]) +61 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][91] ([i915#6095]) +29 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [SKIP][92] +360 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk3/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-tglu-1:       NOTRUN -> [SKIP][93] ([i915#3742])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_cdclk@plane-scaling:
    - shard-tglu:         NOTRUN -> [SKIP][94] ([i915#3742])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_cdclk@plane-scaling.html

  * igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][95] ([i915#13783]) +3 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-6/igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3.html

  * igt@kms_chamelium_frames@dp-crc-multiple:
    - shard-dg2:          NOTRUN -> [SKIP][96] ([i915#11151] / [i915#7828]) +1 other test skip
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_chamelium_frames@dp-crc-multiple.html

  * igt@kms_chamelium_frames@dp-crc-single:
    - shard-tglu-1:       NOTRUN -> [SKIP][97] ([i915#11151] / [i915#7828]) +3 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_chamelium_frames@dp-crc-single.html

  * igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
    - shard-rkl:          NOTRUN -> [SKIP][98] ([i915#11151] / [i915#7828]) +1 other test skip
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html

  * igt@kms_chamelium_hpd@dp-hpd-storm:
    - shard-tglu:         NOTRUN -> [SKIP][99] ([i915#11151] / [i915#7828]) +3 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_chamelium_hpd@dp-hpd-storm.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][100] ([i915#15865]) +1 other test skip
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-type-0-suspend-resume:
    - shard-tglu:         NOTRUN -> [SKIP][101] ([i915#15330])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_content_protection@dp-mst-type-0-suspend-resume.html

  * igt@kms_content_protection@legacy:
    - shard-dg2:          NOTRUN -> [SKIP][102] ([i915#15865])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@legacy-hdcp14:
    - shard-tglu:         NOTRUN -> [SKIP][103] ([i915#15865])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@kms_content_protection@legacy-hdcp14.html

  * igt@kms_content_protection@mei-interface:
    - shard-tglu-1:       NOTRUN -> [SKIP][104] ([i915#15865]) +1 other test skip
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_content_protection@mei-interface.html

  * igt@kms_cursor_crc@cursor-onscreen-256x85:
    - shard-tglu:         [PASS][105] -> [FAIL][106] ([i915#13566]) +1 other test fail
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-tglu-2/igt@kms_cursor_crc@cursor-onscreen-256x85.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-3/igt@kms_cursor_crc@cursor-onscreen-256x85.html

  * igt@kms_cursor_crc@cursor-random-128x42:
    - shard-rkl:          [PASS][107] -> [FAIL][108] ([i915#13566])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-3/igt@kms_cursor_crc@cursor-random-128x42.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_cursor_crc@cursor-random-128x42.html

  * igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [FAIL][109] ([i915#13566]) +3 other tests fail
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-rkl:          NOTRUN -> [SKIP][110] ([i915#13049]) +3 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [FAIL][111] ([i915#13566]) +1 other test fail
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
    - shard-dg2:          NOTRUN -> [SKIP][112] ([i915#13046] / [i915#5354]) +1 other test skip
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-8/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - shard-rkl:          NOTRUN -> [SKIP][113] ([i915#4103]) +1 other test skip
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-rkl:          NOTRUN -> [SKIP][114] ([i915#9723])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-tglu-1:       NOTRUN -> [SKIP][115] ([i915#13691])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-rkl:          NOTRUN -> [SKIP][116] ([i915#3555] / [i915#3804])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][117] ([i915#3804])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-rkl:          NOTRUN -> [SKIP][118] ([i915#13749])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-4/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-rkl:          NOTRUN -> [SKIP][119] ([i915#13707])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-rkl:          NOTRUN -> [SKIP][120] ([i915#3840])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-rkl:          NOTRUN -> [SKIP][121] ([i915#3555] / [i915#3840])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][122] ([i915#9878])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk6/igt@kms_fbcon_fbt@fbc-suspend.html
    - shard-rkl:          [PASS][123] -> [ABORT][124] ([i915#15132])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-5/igt@kms_fbcon_fbt@fbc-suspend.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_feature_discovery@display-3x:
    - shard-dg2:          NOTRUN -> [SKIP][125] ([i915#16081])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_feature_discovery@display-3x.html

  * igt@kms_feature_discovery@display-4x:
    - shard-tglu-1:       NOTRUN -> [SKIP][126] ([i915#16081])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_feature_discovery@display-4x.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-rkl:          NOTRUN -> [SKIP][127] ([i915#9337])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_feature_discovery@psr1:
    - shard-tglu:         NOTRUN -> [SKIP][128] ([i915#658])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-absolute-wf_vblank-interruptible:
    - shard-tglu-1:       NOTRUN -> [SKIP][129] ([i915#3637] / [i915#9934]) +2 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][130] ([i915#9934]) +5 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-dg2:          NOTRUN -> [SKIP][131] ([i915#9934]) +3 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@2x-plain-flip-interruptible:
    - shard-tglu:         NOTRUN -> [SKIP][132] ([i915#3637] / [i915#9934]) +5 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@kms_flip@2x-plain-flip-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][133] ([i915#15643]) +1 other test skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling:
    - shard-dg2:          NOTRUN -> [SKIP][134] ([i915#15643])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-dg2:          NOTRUN -> [SKIP][135] ([i915#15643] / [i915#5190])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-tglu:         NOTRUN -> [SKIP][136] ([i915#15643]) +1 other test skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
    - shard-rkl:          NOTRUN -> [SKIP][137] ([i915#15643])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][138] ([i915#15104] / [i915#15990])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-glk11:        NOTRUN -> [INCOMPLETE][139] ([i915#10056])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk11/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-offscreen-pri-indfb-draw-blt:
    - shard-snb:          NOTRUN -> [SKIP][140] +88 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-snb4/igt@kms_frontbuffer_tracking@fbchdr-1p-offscreen-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-shrfb-plflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][141] ([i915#15989]) +19 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-rgb565-draw-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][142] ([i915#15989]) +5 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_frontbuffer_tracking@fbchdr-rgb565-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-rkl:          NOTRUN -> [SKIP][143] ([i915#1825]) +2 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][144] ([i915#15990] / [i915#8708]) +5 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt:
    - shard-dg2:          NOTRUN -> [SKIP][145] ([i915#15991] / [i915#5354]) +5 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render:
    - shard-tglu-1:       NOTRUN -> [SKIP][146] +52 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-pri-indfb-multidraw:
    - shard-dg2:          NOTRUN -> [SKIP][147] ([i915#15102]) +9 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-draw-render:
    - shard-tglu-1:       NOTRUN -> [SKIP][148] ([i915#15102]) +17 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-rte:
    - shard-rkl:          NOTRUN -> [SKIP][149] ([i915#15102]) +20 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-rkl:          NOTRUN -> [SKIP][150] +54 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@hdr-1p-offscreen-pri-shrfb-draw-mmap-gtt:
    - shard-tglu:         NOTRUN -> [SKIP][151] ([i915#15989]) +9 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_frontbuffer_tracking@hdr-1p-offscreen-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@hdr-1p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-rkl:          [PASS][152] -> [SKIP][153] ([i915#15989]) +17 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@hdr-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][154] ([i915#15990]) +5 other tests skip
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-mmap-gtt:
    - shard-glk:          [PASS][155] -> [SKIP][156] +28 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-glk8/igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-mmap-gtt.html
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk2/igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-pwrite:
    - shard-tglu-1:       NOTRUN -> [SKIP][157] ([i915#15989]) +10 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][158] ([i915#15102] / [i915#3023]) +11 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-spr-indfb-draw-render:
    - shard-dg2:          NOTRUN -> [SKIP][159] ([i915#15991]) +14 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psrhdr-rgb565-draw-blt:
    - shard-tglu:         NOTRUN -> [SKIP][160] ([i915#15102]) +17 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_frontbuffer_tracking@psrhdr-rgb565-draw-blt.html

  * igt@kms_hdmi_inject@inject-4k:
    - shard-mtlp:         [PASS][161] -> [SKIP][162] ([i915#15725])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-mtlp-3/igt@kms_hdmi_inject@inject-4k.html
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-mtlp-1/igt@kms_hdmi_inject@inject-4k.html

  * igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-1-xrgb2101010:
    - shard-dg2:          NOTRUN -> [SKIP][163] ([i915#16012]) +1 other test skip
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-4/igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-1-xrgb2101010.html

  * igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-2-xrgb2101010:
    - shard-rkl:          NOTRUN -> [INCOMPLETE][164] ([i915#15436])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-2-xrgb2101010.html

  * igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-3-xrgb16161616f:
    - shard-dg1:          NOTRUN -> [SKIP][165] ([i915#16012]) +5 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-12/igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-3-xrgb16161616f.html

  * igt@kms_hdr@invalid-hdr:
    - shard-tglu-1:       NOTRUN -> [SKIP][166] ([i915#16012] / [i915#3555] / [i915#8228])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-1-xrgb16161616f:
    - shard-rkl:          NOTRUN -> [SKIP][167] ([i915#16012]) +1 other test skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-1-xrgb16161616f.html
    - shard-tglu-1:       NOTRUN -> [SKIP][168] ([i915#16012]) +1 other test skip
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-1-xrgb16161616f.html

  * igt@kms_hdr@static-toggle-suspend@pipe-a-hdmi-a-3-xrgb16161616f:
    - shard-dg2:          NOTRUN -> [SKIP][169] ([i915#16011]) +1 other test skip
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-6/igt@kms_hdr@static-toggle-suspend@pipe-a-hdmi-a-3-xrgb16161616f.html

  * igt@kms_hdr@static-toggle@pipe-a-hdmi-a-1-xrgb16161616f:
    - shard-rkl:          NOTRUN -> [SKIP][170] ([i915#16011]) +3 other tests skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_hdr@static-toggle@pipe-a-hdmi-a-1-xrgb16161616f.html

  * igt@kms_hdr@static-toggle@pipe-a-hdmi-a-4-xrgb2101010:
    - shard-dg1:          NOTRUN -> [SKIP][171] ([i915#16011]) +5 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-16/igt@kms_hdr@static-toggle@pipe-a-hdmi-a-4-xrgb2101010.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-tglu:         NOTRUN -> [SKIP][172] ([i915#15460])
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][173] ([i915#15459])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][174] ([i915#15460])
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          NOTRUN -> [SKIP][175] ([i915#15815])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-rkl:          NOTRUN -> [SKIP][176] ([i915#6301])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_panel_fitting@legacy:
    - shard-tglu:         NOTRUN -> [SKIP][177] ([i915#6301])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_panel_fitting@legacy.html

  * igt@kms_pipe_stress@stress-xrgb8888-yftiled:
    - shard-rkl:          NOTRUN -> [SKIP][178] ([i915#14712])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html

  * igt@kms_plane@pixel-format-4-tiled-modifier:
    - shard-tglu:         NOTRUN -> [SKIP][179] ([i915#15709])
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@kms_plane@pixel-format-4-tiled-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-ccs-modifier:
    - shard-rkl:          NOTRUN -> [SKIP][180] ([i915#15709]) +3 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_plane@pixel-format-y-tiled-ccs-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier:
    - shard-tglu-1:       NOTRUN -> [SKIP][181] ([i915#15709])
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier@pipe-a-plane-7:
    - shard-tglu-1:       NOTRUN -> [SKIP][182] ([i915#15608]) +1 other test skip
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier@pipe-a-plane-7.html

  * igt@kms_plane@pixel-format-y-tiled-modifier@pipe-b-plane-7:
    - shard-tglu:         NOTRUN -> [SKIP][183] ([i915#15608]) +1 other test skip
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_plane@pixel-format-y-tiled-modifier@pipe-b-plane-7.html

  * igt@kms_plane@pixel-format-yf-tiled-modifier:
    - shard-dg2:          NOTRUN -> [SKIP][184] ([i915#15709])
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_plane@pixel-format-yf-tiled-modifier.html

  * igt@kms_plane_alpha_blend@alpha-basic:
    - shard-glk:          NOTRUN -> [FAIL][185] ([i915#12178])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk9/igt@kms_plane_alpha_blend@alpha-basic.html

  * igt@kms_plane_alpha_blend@alpha-basic@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][186] ([i915#7862]) +1 other test fail
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk9/igt@kms_plane_alpha_blend@alpha-basic@pipe-a-hdmi-a-1.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb:
    - shard-glk:          NOTRUN -> [FAIL][187] ([i915#10647] / [i915#12169])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk3/igt@kms_plane_alpha_blend@alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][188] ([i915#10647]) +1 other test fail
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk3/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-rkl:          NOTRUN -> [SKIP][189] ([i915#3555]) +2 other tests skip
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a:
    - shard-rkl:          NOTRUN -> [SKIP][190] ([i915#15329]) +3 other tests skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-tglu:         NOTRUN -> [SKIP][191] ([i915#12343] / [i915#9812])
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-rkl:          NOTRUN -> [SKIP][192] ([i915#12343] / [i915#5354])
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-tglu-1:       NOTRUN -> [SKIP][193] ([i915#12343] / [i915#9812])
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-tglu-1:       NOTRUN -> [SKIP][194] ([i915#3828])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_lpsp@screens-disabled:
    - shard-dg2:          NOTRUN -> [SKIP][195] ([i915#8430])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_pm_lpsp@screens-disabled.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-tglu:         NOTRUN -> [SKIP][196] ([i915#15073]) +1 other test skip
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-rkl:          [PASS][197] -> [SKIP][198] ([i915#15073]) +1 other test skip
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-3/igt@kms_pm_rpm@modeset-non-lpsp.html
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-dg1:          [PASS][199] -> [SKIP][200] ([i915#15073]) +2 other tests skip
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-13/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-14/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_prime@d3hot:
    - shard-tglu-1:       NOTRUN -> [SKIP][201] ([i915#6524])
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_prime@d3hot.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf:
    - shard-snb:          NOTRUN -> [SKIP][202] ([i915#11520])
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-snb4/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area:
    - shard-dg2:          NOTRUN -> [SKIP][203] ([i915#11520]) +2 other tests skip
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf:
    - shard-glk10:        NOTRUN -> [SKIP][204] ([i915#11520]) +1 other test skip
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk10/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
    - shard-tglu:         NOTRUN -> [SKIP][205] ([i915#11520]) +3 other tests skip
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html
    - shard-glk11:        NOTRUN -> [SKIP][206] ([i915#11520])
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk11/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-tglu-1:       NOTRUN -> [SKIP][207] ([i915#11520]) +3 other tests skip
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area:
    - shard-rkl:          NOTRUN -> [SKIP][208] ([i915#11520]) +4 other tests skip
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area:
    - shard-glk:          NOTRUN -> [SKIP][209] ([i915#11520]) +7 other tests skip
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk5/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-tglu:         NOTRUN -> [SKIP][210] ([i915#9683])
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-rkl:          NOTRUN -> [SKIP][211] ([i915#9683])
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-psr-cursor-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][212] ([i915#1072] / [i915#9732]) +8 other tests skip
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_psr@fbc-psr-cursor-mmap-gtt.html

  * igt@kms_psr@pr-cursor-plane-onoff:
    - shard-tglu-1:       NOTRUN -> [SKIP][213] ([i915#9732]) +11 other tests skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_psr@pr-cursor-plane-onoff.html

  * igt@kms_psr@pr-primary-page-flip:
    - shard-tglu:         NOTRUN -> [SKIP][214] ([i915#9732]) +8 other tests skip
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@kms_psr@pr-primary-page-flip.html

  * igt@kms_psr@psr-sprite-plane-onoff:
    - shard-rkl:          NOTRUN -> [SKIP][215] ([i915#1072] / [i915#9732]) +11 other tests skip
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_psr@psr-sprite-plane-onoff.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-dg2:          NOTRUN -> [SKIP][216] ([i915#12755] / [i915#15867])
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
    - shard-tglu:         NOTRUN -> [SKIP][217] ([i915#5289])
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-dg2:          NOTRUN -> [SKIP][218] ([i915#5190]) +1 other test skip
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-8/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-dg2:          NOTRUN -> [SKIP][219] ([i915#3555]) +2 other tests skip
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-tglu-1:       NOTRUN -> [SKIP][220] ([i915#3555])
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-tglu:         NOTRUN -> [SKIP][221] ([i915#3555])
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_vblank@ts-continuation-dpms-suspend:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][222] ([i915#12276]) +1 other test incomplete
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk10/igt@kms_vblank@ts-continuation-dpms-suspend.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-tglu:         NOTRUN -> [SKIP][223] ([i915#9906]) +1 other test skip
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@kms_vrr@flip-basic-fastset.html

  * igt@kms_vrr@flip-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][224] ([i915#15243] / [i915#3555])
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_vrr@flip-dpms.html

  * igt@perf@blocking@0-rcs0:
    - shard-tglu:         [PASS][225] -> [FAIL][226] ([i915#10538]) +1 other test fail
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-tglu-10/igt@perf@blocking@0-rcs0.html
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-9/igt@perf@blocking@0-rcs0.html

  * igt@perf_pmu@rc6-all-gts:
    - shard-rkl:          NOTRUN -> [SKIP][227] ([i915#8516])
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@perf_pmu@rc6-all-gts.html

  * igt@prime_vgem@basic-write:
    - shard-rkl:          NOTRUN -> [SKIP][228] ([i915#3291] / [i915#3708])
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@prime_vgem@basic-write.html

  * igt@prime_vgem@fence-write-hang:
    - shard-tglu:         NOTRUN -> [SKIP][229] +53 other tests skip
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@prime_vgem@fence-write-hang.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
    - shard-rkl:          NOTRUN -> [SKIP][230] ([i915#9917])
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html

  * igt@tools_test@sysfs_l3_parity:
    - shard-dg2:          NOTRUN -> [SKIP][231] ([i915#4818])
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@tools_test@sysfs_l3_parity.html

  
#### Possible fixes ####

  * igt@gem_eio@suspend:
    - shard-rkl:          [ABORT][232] ([i915#15131]) -> [PASS][233]
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@gem_eio@suspend.html
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@gem_eio@suspend.html

  * igt@gem_workarounds@suspend-resume:
    - shard-rkl:          [ABORT][234] ([i915#15152]) -> [PASS][235]
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@gem_workarounds@suspend-resume.html
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@gem_workarounds@suspend-resume.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-rkl:          [INCOMPLETE][236] ([i915#13356]) -> [PASS][237]
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@i915_pm_rpm@system-suspend.html
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@i915_pm_rpm@system-suspend.html

  * igt@i915_pm_rps@reset:
    - shard-snb:          [TIMEOUT][238] ([i915#16162]) -> [PASS][239]
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-snb4/igt@i915_pm_rps@reset.html
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-snb4/igt@i915_pm_rps@reset.html

  * igt@kms_async_flips@async-flip-suspend-resume:
    - shard-rkl:          [INCOMPLETE][240] ([i915#12761]) -> [PASS][241]
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-3/igt@kms_async_flips@async-flip-suspend-resume.html
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-5/igt@kms_async_flips@async-flip-suspend-resume.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-0:
    - shard-dg1:          [DMESG-WARN][242] ([i915#4423]) -> [PASS][243]
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-15/igt@kms_big_fb@y-tiled-8bpp-rotate-0.html
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-15/igt@kms_big_fb@y-tiled-8bpp-rotate-0.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          [INCOMPLETE][244] ([i915#15582]) -> [PASS][245]
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-2.html
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-2:
    - shard-rkl:          [FAIL][246] ([i915#13566]) -> [PASS][247] +1 other test pass
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-4/igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-2.html
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-7/igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-2.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-valid-mode:
    - shard-rkl:          [ABORT][248] -> [PASS][249] +1 other test pass
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-valid-mode.html
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-rkl:          [INCOMPLETE][250] ([i915#10056]) -> [PASS][251]
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-draw-render:
    - shard-dg2:          [SKIP][252] ([i915#15989]) -> [PASS][253] +2 other tests pass
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-6/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-draw-render.html
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-10/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-onoff:
    - shard-rkl:          [SKIP][254] ([i915#15989]) -> [PASS][255] +7 other tests pass
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-onoff.html
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-dg2:          [SKIP][256] ([i915#15459]) -> [PASS][257]
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-10/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-dg1:          [SKIP][258] ([i915#15073]) -> [PASS][259]
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-19/igt@kms_pm_rpm@dpms-lpsp.html
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-15/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-rkl:          [SKIP][260] ([i915#15073]) -> [PASS][261] +1 other test pass
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-3/igt@kms_pm_rpm@modeset-lpsp.html
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-dg2:          [SKIP][262] ([i915#15073]) -> [PASS][263] +1 other test pass
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-4/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-6/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_vblank@ts-continuation-suspend:
    - shard-dg2:          [ABORT][264] ([i915#15132]) -> [PASS][265]
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-10/igt@kms_vblank@ts-continuation-suspend.html
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-8/igt@kms_vblank@ts-continuation-suspend.html

  * igt@perf_pmu@busy-double-start@vecs1:
    - shard-dg2:          [FAIL][266] ([i915#4349]) -> [PASS][267] +4 other tests pass
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-4/igt@perf_pmu@busy-double-start@vecs1.html
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-6/igt@perf_pmu@busy-double-start@vecs1.html

  
#### Warnings ####

  * igt@gem_ccs@block-copy-compressed:
    - shard-rkl:          [SKIP][268] ([i915#14544] / [i915#3555] / [i915#9323]) -> [SKIP][269] ([i915#3555] / [i915#9323])
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_ccs@block-copy-compressed.html
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@gem_ccs@block-copy-compressed.html

  * igt@gem_ccs@large-ctrl-surf-copy:
    - shard-rkl:          [SKIP][270] ([i915#13008]) -> [SKIP][271] ([i915#13008] / [i915#14544])
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@gem_ccs@large-ctrl-surf-copy.html
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@gem_ccs@large-ctrl-surf-copy.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-rkl:          [SKIP][272] ([i915#14544] / [i915#7697]) -> [SKIP][273] ([i915#7697])
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_close_race@multigpu-basic-threads.html
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_exec_balancer@parallel:
    - shard-rkl:          [SKIP][274] ([i915#4525]) -> [SKIP][275] ([i915#14544] / [i915#4525])
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-2/igt@gem_exec_balancer@parallel.html
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_balancer@parallel-out-fence:
    - shard-rkl:          [SKIP][276] ([i915#14544] / [i915#4525]) -> [SKIP][277] ([i915#4525]) +1 other test skip
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_exec_balancer@parallel-out-fence.html
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@gem_exec_balancer@parallel-out-fence.html

  * igt@gem_exec_reloc@basic-cpu-noreloc:
    - shard-rkl:          [SKIP][278] ([i915#14544] / [i915#3281]) -> [SKIP][279] ([i915#3281]) +6 other tests skip
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_exec_reloc@basic-cpu-noreloc.html
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_exec_reloc@basic-cpu-noreloc.html

  * igt@gem_exec_reloc@basic-gtt-wc-noreloc:
    - shard-rkl:          [SKIP][280] ([i915#3281]) -> [SKIP][281] ([i915#14544] / [i915#3281]) +2 other tests skip
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html

  * igt@gem_lmem_evict@dontneed-evict-race:
    - shard-rkl:          [SKIP][282] ([i915#4613] / [i915#7582]) -> [SKIP][283] ([i915#14544] / [i915#4613] / [i915#7582])
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-2/igt@gem_lmem_evict@dontneed-evict-race.html
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@gem_lmem_evict@dontneed-evict-race.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-rkl:          [SKIP][284] ([i915#4613]) -> [SKIP][285] ([i915#14544] / [i915#4613])
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_lmem_swapping@verify:
    - shard-rkl:          [SKIP][286] ([i915#14544] / [i915#4613]) -> [SKIP][287] ([i915#4613])
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_lmem_swapping@verify.html
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_lmem_swapping@verify.html

  * igt@gem_pread@snoop:
    - shard-rkl:          [SKIP][288] ([i915#14544] / [i915#3282]) -> [SKIP][289] ([i915#3282]) +3 other tests skip
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_pread@snoop.html
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@gem_pread@snoop.html

  * igt@gem_pwrite@basic-random:
    - shard-rkl:          [SKIP][290] ([i915#3282]) -> [SKIP][291] ([i915#14544] / [i915#3282]) +2 other tests skip
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@gem_pwrite@basic-random.html
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@gem_pwrite@basic-random.html

  * igt@gem_set_tiling_vs_blt@tiled-to-tiled:
    - shard-rkl:          [SKIP][292] ([i915#8411]) -> [SKIP][293] ([i915#14544] / [i915#8411])
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-rkl:          [SKIP][294] ([i915#14544] / [i915#8411]) -> [SKIP][295] ([i915#8411])
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-rkl:          [SKIP][296] ([i915#14544] / [i915#3297]) -> [SKIP][297] ([i915#3297]) +2 other tests skip
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_userptr_blits@create-destroy-unsync.html
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gen9_exec_parse@batch-zero-length:
    - shard-rkl:          [SKIP][298] ([i915#2527]) -> [SKIP][299] ([i915#14544] / [i915#2527])
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-2/igt@gen9_exec_parse@batch-zero-length.html
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@gen9_exec_parse@batch-zero-length.html

  * igt@i915_pm_freq_api@freq-suspend:
    - shard-rkl:          [SKIP][300] ([i915#14544] / [i915#8399]) -> [SKIP][301] ([i915#8399])
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@i915_pm_freq_api@freq-suspend.html
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@i915_pm_freq_api@freq-suspend.html

  * igt@i915_query@query-topology-unsupported:
    - shard-rkl:          [SKIP][302] ([i915#16079]) -> [SKIP][303] ([i915#14544] / [i915#16079])
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@i915_query@query-topology-unsupported.html
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@i915_query@query-topology-unsupported.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-rkl:          [SKIP][304] ([i915#14544] / [i915#9531]) -> [SKIP][305] ([i915#9531])
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-rkl:          [SKIP][306] ([i915#14544] / [i915#5286]) -> [SKIP][307] ([i915#5286]) +2 other tests skip
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-rkl:          [SKIP][308] ([i915#5286]) -> [SKIP][309] ([i915#14544] / [i915#5286])
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
    - shard-rkl:          [SKIP][310] ([i915#14544] / [i915#3638]) -> [SKIP][311] ([i915#3638])
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
    - shard-rkl:          [SKIP][312] -> [SKIP][313] ([i915#14544]) +24 other tests skip
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-2/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs:
    - shard-rkl:          [SKIP][314] ([i915#14098] / [i915#14544] / [i915#6095]) -> [SKIP][315] ([i915#14098] / [i915#6095]) +7 other tests skip
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs.html
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          [SKIP][316] ([i915#14544] / [i915#6095]) -> [SKIP][317] ([i915#6095]) +3 other tests skip
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc:
    - shard-rkl:          [SKIP][318] ([i915#14098] / [i915#6095]) -> [SKIP][319] ([i915#14098] / [i915#14544] / [i915#6095]) +1 other test skip
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc.html
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-rkl:          [SKIP][320] ([i915#12313] / [i915#14544]) -> [SKIP][321] ([i915#12313])
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs:
    - shard-rkl:          [INCOMPLETE][322] ([i915#15582]) -> [ABORT][323] ([i915#15132])
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs.html
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-rkl:          [SKIP][324] ([i915#3742]) -> [SKIP][325] ([i915#14544] / [i915#3742])
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_cdclk@mode-transition-all-outputs.html
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_chamelium_frames@dp-crc-single:
    - shard-rkl:          [SKIP][326] ([i915#11151] / [i915#7828]) -> [SKIP][327] ([i915#11151] / [i915#14544] / [i915#7828])
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_chamelium_frames@dp-crc-single.html
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_chamelium_frames@dp-crc-single.html

  * igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
    - shard-rkl:          [SKIP][328] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][329] ([i915#11151] / [i915#7828]) +5 other tests skip
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html

  * igt@kms_content_protection@mei-interface:
    - shard-rkl:          [SKIP][330] ([i915#15865]) -> [SKIP][331] ([i915#14544] / [i915#15865])
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_content_protection@mei-interface.html
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@type1:
    - shard-rkl:          [SKIP][332] ([i915#14544] / [i915#15865]) -> [SKIP][333] ([i915#15865])
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_content_protection@type1.html
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_content_protection@type1.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-rkl:          [SKIP][334] ([i915#13691]) -> [SKIP][335] ([i915#13691] / [i915#14544])
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_display_modes@extended-mode-basic.html
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dsc@dsc-basic:
    - shard-rkl:          [SKIP][336] ([i915#14544] / [i915#3555] / [i915#3840]) -> [SKIP][337] ([i915#3555] / [i915#3840])
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_dsc@dsc-basic.html
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_dsc@dsc-basic.html

  * igt@kms_feature_discovery@display-4x:
    - shard-rkl:          [SKIP][338] ([i915#14544] / [i915#16081]) -> [SKIP][339] ([i915#16081])
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_feature_discovery@display-4x.html
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_feature_discovery@display-4x.html

  * igt@kms_flip@2x-absolute-wf_vblank-interruptible:
    - shard-rkl:          [SKIP][340] ([i915#9934]) -> [SKIP][341] ([i915#14544] / [i915#9934]) +1 other test skip
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
    - shard-rkl:          [SKIP][342] ([i915#14544] / [i915#9934]) -> [SKIP][343] ([i915#9934]) +2 other tests skip
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-rkl:          [SKIP][344] ([i915#15643]) -> [SKIP][345] ([i915#14544] / [i915#15643]) +2 other tests skip
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
    - shard-rkl:          [SKIP][346] ([i915#14544] / [i915#15643]) -> [SKIP][347] ([i915#15643])
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-dg1:          [SKIP][348] ([i915#15643] / [i915#4423]) -> [SKIP][349] ([i915#15643])
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-16/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-13/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-rkl:          [SKIP][350] ([i915#14544] / [i915#1825]) -> [SKIP][351] ([i915#1825]) +4 other tests skip
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg1:          [SKIP][352] ([i915#15990] / [i915#4423] / [i915#8708]) -> [SKIP][353] ([i915#15990] / [i915#8708])
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-18/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-12/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-cur-indfb-onoff:
    - shard-rkl:          [SKIP][354] ([i915#14544]) -> [SKIP][355] +41 other tests skip
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-cur-indfb-onoff.html
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu:
    - shard-rkl:          [SKIP][356] ([i915#15102] / [i915#3023]) -> [SKIP][357] ([i915#14544] / [i915#15102] / [i915#3023]) +3 other tests skip
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu.html
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
    - shard-dg2:          [SKIP][358] ([i915#10433] / [i915#15102]) -> [SKIP][359] ([i915#15102]) +4 other tests skip
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][360] ([i915#1825]) -> [SKIP][361] ([i915#14544] / [i915#1825]) +4 other tests skip
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt.html
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt:
    - shard-dg2:          [SKIP][362] ([i915#15102]) -> [SKIP][363] ([i915#10433] / [i915#15102]) +1 other test skip
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-pwrite:
    - shard-dg1:          [SKIP][364] -> [SKIP][365] ([i915#4423])
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-12/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-pwrite.html
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-19/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-render:
    - shard-rkl:          [SKIP][366] ([i915#14544] / [i915#15102] / [i915#3023]) -> [SKIP][367] ([i915#15102] / [i915#3023]) +7 other tests skip
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][368] ([i915#14544] / [i915#15102]) -> [SKIP][369] ([i915#15102]) +13 other tests skip
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-spr-indfb-move:
    - shard-rkl:          [SKIP][370] ([i915#15102]) -> [SKIP][371] ([i915#14544] / [i915#15102]) +5 other tests skip
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-spr-indfb-move.html
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-spr-indfb-move.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-rkl:          [SKIP][372] ([i915#16012] / [i915#3555] / [i915#8228]) -> [INCOMPLETE][373] ([i915#15436])
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_hdr@bpc-switch-suspend.html
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_hdr@invalid-hdr:
    - shard-rkl:          [SKIP][374] ([i915#14544] / [i915#3555] / [i915#8228]) -> [SKIP][375] ([i915#16012] / [i915#3555] / [i915#8228])
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_hdr@invalid-hdr.html
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_hdr@invalid-hdr.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-rkl:          [SKIP][376] ([i915#15458]) -> [SKIP][377] ([i915#14544] / [i915#15458])
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-2/igt@kms_joiner@basic-ultra-joiner.html
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-rkl:          [SKIP][378] ([i915#15460]) -> [SKIP][379] ([i915#14544] / [i915#15460])
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_joiner@invalid-modeset-big-joiner.html
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-dg1:          [SKIP][380] ([i915#4423] / [i915#6301]) -> [SKIP][381] ([i915#6301])
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-13/igt@kms_panel_fitting@atomic-fastset.html
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-12/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping:
    - shard-rkl:          [SKIP][382] ([i915#15709]) -> [SKIP][383] ([i915#14544] / [i915#15709])
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping.html
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier:
    - shard-rkl:          [SKIP][384] ([i915#14544] / [i915#15709]) -> [SKIP][385] ([i915#15709]) +1 other test skip
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-dg1:          [SKIP][386] ([i915#13958] / [i915#4423]) -> [SKIP][387] ([i915#13958])
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-12/igt@kms_plane_multiple@2x-tiling-x.html
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-18/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_plane_multiple@tiling-4:
    - shard-rkl:          [SKIP][388] ([i915#14259]) -> [SKIP][389] ([i915#14259] / [i915#14544])
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-2/igt@kms_plane_multiple@tiling-4.html
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_plane_multiple@tiling-4.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-rkl:          [SKIP][390] ([i915#14544] / [i915#3828]) -> [SKIP][391] ([i915#3828])
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_pm_dc@dc5-retention-flops.html
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_prime@basic-crc-hybrid:
    - shard-rkl:          [SKIP][392] ([i915#6524]) -> [SKIP][393] ([i915#14544] / [i915#6524])
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_prime@basic-crc-hybrid.html
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_prime@basic-crc-hybrid.html

  * igt@kms_prime@d3hot:
    - shard-rkl:          [SKIP][394] ([i915#14544] / [i915#6524]) -> [SKIP][395] ([i915#6524])
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_prime@d3hot.html
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_prime@d3hot.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf:
    - shard-rkl:          [SKIP][396] ([i915#11520] / [i915#14544]) -> [SKIP][397] ([i915#11520]) +2 other tests skip
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf.html
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area:
    - shard-rkl:          [SKIP][398] ([i915#11520]) -> [SKIP][399] ([i915#11520] / [i915#14544]) +1 other test skip
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-rkl:          [SKIP][400] ([i915#14544] / [i915#9683]) -> [SKIP][401] ([i915#9683])
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_psr2_su@page_flip-nv12.html
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@pr-cursor-plane-onoff:
    - shard-rkl:          [SKIP][402] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][403] ([i915#1072] / [i915#9732]) +10 other tests skip
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_psr@pr-cursor-plane-onoff.html
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_psr@pr-cursor-plane-onoff.html

  * igt@kms_psr@psr2-primary-mmap-gtt:
    - shard-rkl:          [SKIP][404] ([i915#1072] / [i915#9732]) -> [SKIP][405] ([i915#1072] / [i915#14544] / [i915#9732]) +5 other tests skip
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_psr@psr2-primary-mmap-gtt.html
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_psr@psr2-primary-mmap-gtt.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-rkl:          [SKIP][406] ([i915#14544] / [i915#3555]) -> [SKIP][407] ([i915#3555]) +1 other test skip
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_setmode@clone-exclusive-crtc.html
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@perf@mi-rpc:
    - shard-rkl:          [SKIP][408] ([i915#14544] / [i915#2434]) -> [SKIP][409] ([i915#2434])
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@perf@mi-rpc.html
   [409]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@perf@mi-rpc.html

  * igt@perf@per-context-mode-unprivileged:
    - shard-rkl:          [SKIP][410] ([i915#2435]) -> [SKIP][411] ([i915#14544] / [i915#2435])
   [410]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@perf@per-context-mode-unprivileged.html
   [411]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@perf@per-context-mode-unprivileged.html

  * igt@sriov_basic@bind-unbind-vf:
    - shard-rkl:          [SKIP][412] ([i915#9917]) -> [SKIP][413] ([i915#14544] / [i915#9917])
   [412]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@sriov_basic@bind-unbind-vf.html
   [413]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@sriov_basic@bind-unbind-vf.html

  
  [i915#10056]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10056
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10538
  [i915#10647]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10647
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#12169]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12169
  [i915#12178]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12178
  [i915#12276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12276
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
  [i915#12454]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12454
  [i915#12712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12712
  [i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
  [i915#12761]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12761
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
  [i915#13029]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13029
  [i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#13390]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13390
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13691]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13691
  [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
  [i915#13717]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13717
  [i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
  [i915#13783]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13783
  [i915#13809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13809
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14259]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14259
  [i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
  [i915#14545]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14545
  [i915#14712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14712
  [i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
  [i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
  [i915#15104]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15104
  [i915#15131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15131
  [i915#15132]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15132
  [i915#15152]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15152
  [i915#15243]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15243
  [i915#15329]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15329
  [i915#15330]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15330
  [i915#15436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15436
  [i915#15458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15458
  [i915#15459]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15459
  [i915#15460]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15460
  [i915#15582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15582
  [i915#15608]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15608
  [i915#15643]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15643
  [i915#15662]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15662
  [i915#15709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15709
  [i915#15725]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15725
  [i915#15733]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15733
  [i915#15740]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15740
  [i915#15815]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15815
  [i915#15865]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15865
  [i915#15867]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15867
  [i915#15931]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15931
  [i915#15989]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15989
  [i915#15990]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15990
  [i915#15991]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15991
  [i915#16011]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16011
  [i915#16012]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16012
  [i915#16079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16079
  [i915#16081]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16081
  [i915#16162]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16162
  [i915#16182]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16182
  [i915#16205]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16205
  [i915#16226]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16226
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
  [i915#2435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2435
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4818]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4818
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
  [i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5566
  [i915#5723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5723
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
  [i915#6344]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6344
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
  [i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7862]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7862
  [i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
  [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
  [i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
  [i915#9878]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9878
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_18556 -> Patchwork_163939v4

  CI-20190529: 20190529
  CI_DRM_18556: 1e5fbf0d628cd02dced6cfb1ebe39717f121fb4c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8937: 8937
  Patchwork_163939v4: 1e5fbf0d628cd02dced6cfb1ebe39717f121fb4c @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/index.html

[-- Attachment #2: Type: text/html, Size: 143866 bytes --]

RE: [PATCH v4 01/13] drm/i915/display: Remove TGL DC3CO support

[Manna, Animesh]

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Wednesday, May 27, 2026 12:48 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>
> Subject: [PATCH v4 01/13] drm/i915/display: Remove TGL DC3CO support
> 
> Remove all Tiger Lake DC3CO-related functions from intel_psr.c and
> intel_display_power_well.c, as the feature is not enabled and not used.
> Also remove the TGL/DG1 DC3CO count debugfs entry from intel_dmc.c, as
> DC3CO is not active on those platforms. A new debugfs entry for Xe3LP will
> be added in a subsequent patch.
> 
> Remove the unused dc3co_exitline field from struct intel_psr and struct
> intel_crtc_state, along with the corresponding EXITLINE register read in
> intel_psr_get_config().
> 
> Changes in v2:
> - Squash "Remove unused PSR dc3co_exitline field" and
>   "Remove unused dc3co_exitline from crtc_state" into this patch
> 
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>

LGTM.
Reviewed-by: Animesh Manna <animesh.manna@intel.com>

> ---
>  .../i915/display/intel_display_power_well.c   |  25 ---
>  .../drm/i915/display/intel_display_types.h    |   3 -
>  drivers/gpu/drm/i915/display/intel_dmc.c      |   6 -
>  drivers/gpu/drm/i915/display/intel_psr.c      | 171 ------------------
>  4 files changed, 205 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 04bd0dde5bed..2f0d0a77c1a2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -866,23 +866,6 @@ void gen9_set_dc_state(struct intel_display *display,
> u32 state)
>  	power_domains->dc_state = val & mask;
>  }
> 
> -static void tgl_enable_dc3co(struct intel_display *display) -{
> -	drm_dbg_kms(display->drm, "Enabling DC3CO\n");
> -	gen9_set_dc_state(display, DC_STATE_EN_DC3CO);
> -}
> -
> -static void tgl_disable_dc3co(struct intel_display *display) -{
> -	drm_dbg_kms(display->drm, "Disabling DC3CO\n");
> -	intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0);
> -	gen9_set_dc_state(display, DC_STATE_DISABLE);
> -	/*
> -	 * Delay of 200us DC3CO Exit time B.Spec 49196
> -	 */
> -	usleep_range(200, 210);
> -}
> -
>  static void assert_can_enable_dc5(struct intel_display *display)  {
>  	enum i915_power_well_id high_pg;
> @@ -1061,11 +1044,6 @@ void gen9_disable_dc_states(struct intel_display
> *display)
>  	struct intel_cdclk_config cdclk_config = {};
>  	u32 old_state = power_domains->dc_state;
> 
> -	if (power_domains->target_dc_state == DC_STATE_EN_DC3CO) {
> -		tgl_disable_dc3co(display);
> -		return;
> -	}
> -
>  	if (HAS_DISPLAY(display)) {
>  		intel_dmc_wl_get_noreg(display);
>  		gen9_set_dc_state(display, DC_STATE_DISABLE); @@ -1114,9
> +1092,6 @@ static void gen9_dc_off_power_well_disable(struct intel_display
> *display,
>  		return;
> 
>  	switch (power_domains->target_dc_state) {
> -	case DC_STATE_EN_DC3CO:
> -		tgl_enable_dc3co(display);
> -		break;
>  	case DC_STATE_EN_UPTO_DC6:
>  		skl_enable_dc6(display);
>  		break;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index f44be5c689ae..1cfc585530dc 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1184,7 +1184,6 @@ struct intel_crtc_state {
>  	bool pkg_c_latency_used;
>  	/* Only used for state verification. */
>  	enum intel_panel_replay_dsc_support panel_replay_dsc_support;
> -	u32 dc3co_exitline;
>  	u16 su_y_granularity;
>  	u8 active_non_psr_pipes;
>  	u8 entry_setup_frames;
> @@ -1776,9 +1775,7 @@ struct intel_psr {
>  	bool source_panel_replay_support;
>  	bool sink_panel_replay_support;
>  	bool panel_replay_enabled;
> -	u32 dc3co_exitline;
>  	u32 dc3co_exit_delay;
> -	struct delayed_work dc3co_work;
>  	u8 entry_setup_frames;
> 
>  	u8 io_wake_lines;
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 481fb65b7110..4785001644f5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -1647,19 +1647,13 @@ static int intel_dmc_debugfs_status_show(struct
> seq_file *m, void *unused)
>  		   DMC_VERSION_MINOR(dmc->version));
> 
>  	if (DISPLAY_VER(display) >= 12) {
> -		intel_reg_t dc3co_reg;
> -
>  		if (display->platform.dgfx || DISPLAY_VER(display) >= 14) {
> -			dc3co_reg = DG1_DMC_DEBUG3;
>  			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
>  		} else {
> -			dc3co_reg = TGL_DMC_DEBUG3;
>  			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
>  			dc6_reg = TGL_DMC_DEBUG_DC6_COUNT;
>  		}
> 
> -		seq_printf(m, "DC3CO count: %d\n",
> -			   intel_de_read(display, dc3co_reg));
>  	} else {
>  		dc5_reg = display->platform.broxton ?
> BXT_DMC_DC3_DC5_COUNT :
>  			SKL_DMC_DC3_DC5_COUNT;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index b0414bd1dc6b..730ca7af7873 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -88,22 +88,6 @@
>   * issues the self-refresh re-enable code is done from a work queue, which
>   * must be correctly synchronized/cancelled when shutting down the pipe."
>   *
> - * DC3CO (DC3 clock off)
> - *
> - * On top of PSR2, GEN12 adds a intermediate power savings state that turns
> - * clock off automatically during PSR2 idle state.
> - * The smaller overhead of DC3co entry/exit vs. the overhead of PSR2 deep
> sleep
> - * entry/exit allows the HW to enter a low-power state even when page
> flipping
> - * periodically (for instance a 30fps video playback scenario).
> - *
> - * Every time a flips occurs PSR2 will get out of deep sleep state(if it was),
> - * so DC3CO is enabled and tgl_dc3co_disable_work is schedule to run after
> 6
> - * frames, if no other flip occurs and the function above is executed, DC3CO
> is
> - * disabled and PSR2 is configured to enter deep sleep, resetting again in
> case
> - * of another flip.
> - * Front buffer modifications do not trigger DC3CO activation on purpose as
> it
> - * would bring a lot of complexity and most of the moderns systems will only
> - * use page flips.
>   */
> 
>  /*
> @@ -1217,108 +1201,6 @@ static void psr2_program_idle_frames(struct
> intel_dp *intel_dp,
>  		     EDP_PSR2_IDLE_FRAMES(idle_frames));
>  }
> 
> -static void tgl_psr2_enable_dc3co(struct intel_dp *intel_dp) -{
> -	struct intel_display *display = to_intel_display(intel_dp);
> -
> -	psr2_program_idle_frames(intel_dp, 0);
> -	intel_display_power_set_target_dc_state(display,
> DC_STATE_EN_DC3CO);
> -}
> -
> -static void tgl_psr2_disable_dc3co(struct intel_dp *intel_dp) -{
> -	struct intel_display *display = to_intel_display(intel_dp);
> -
> -	intel_display_power_set_target_dc_state(display,
> DC_STATE_EN_UPTO_DC6);
> -	psr2_program_idle_frames(intel_dp,
> psr_compute_idle_frames(intel_dp));
> -}
> -
> -static void tgl_dc3co_disable_work(struct work_struct *work) -{
> -	struct intel_dp *intel_dp =
> -		container_of(work, typeof(*intel_dp), psr.dc3co_work.work);
> -
> -	mutex_lock(&intel_dp->psr.lock);
> -	/* If delayed work is pending, it is not idle */
> -	if (delayed_work_pending(&intel_dp->psr.dc3co_work))
> -		goto unlock;
> -
> -	tgl_psr2_disable_dc3co(intel_dp);
> -unlock:
> -	mutex_unlock(&intel_dp->psr.lock);
> -}
> -
> -static void tgl_disallow_dc3co_on_psr2_exit(struct intel_dp *intel_dp) -{
> -	if (!intel_dp->psr.dc3co_exitline)
> -		return;
> -
> -	cancel_delayed_work(&intel_dp->psr.dc3co_work);
> -	/* Before PSR2 exit disallow dc3co*/
> -	tgl_psr2_disable_dc3co(intel_dp);
> -}
> -
> -static bool
> -dc3co_is_pipe_port_compatible(struct intel_dp *intel_dp,
> -			      struct intel_crtc_state *crtc_state)
> -{
> -	struct intel_display *display = to_intel_display(intel_dp);
> -	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> -	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> -	enum port port = dig_port->base.port;
> -
> -	if (display->platform.alderlake_p || DISPLAY_VER(display) >= 14)
> -		return pipe <= PIPE_B && port <= PORT_B;
> -	else
> -		return pipe == PIPE_A && port == PORT_A;
> -}
> -
> -static void
> -tgl_dc3co_exitline_compute_config(struct intel_dp *intel_dp,
> -				  struct intel_crtc_state *crtc_state)
> -{
> -	struct intel_display *display = to_intel_display(intel_dp);
> -	const u32 crtc_vdisplay = crtc_state-
> >uapi.adjusted_mode.crtc_vdisplay;
> -	struct i915_power_domains *power_domains = &display-
> >power.domains;
> -	u32 exit_scanlines;
> -
> -	/*
> -	 * FIXME: Due to the changed sequence of activating/deactivating
> DC3CO,
> -	 * disable DC3CO until the changed dc3co activating/deactivating
> sequence
> -	 * is applied. B.Specs:49196
> -	 */
> -	return;
> -
> -	/*
> -	 * DMC's DC3CO exit mechanism has an issue with Selective Fecth
> -	 * TODO: when the issue is addressed, this restriction should be
> removed.
> -	 */
> -	if (crtc_state->enable_psr2_sel_fetch)
> -		return;
> -
> -	if (!(power_domains->allowed_dc_mask & DC_STATE_EN_DC3CO))
> -		return;
> -
> -	if (!dc3co_is_pipe_port_compatible(intel_dp, crtc_state))
> -		return;
> -
> -	/* Wa_16011303918:adl-p */
> -	if (intel_display_wa(display, INTEL_DISPLAY_WA_16011303918))
> -		return;
> -
> -	/*
> -	 * DC3CO Exit time 200us B.Spec 49196
> -	 * PSR2 transcoder Early Exit scanlines = ROUNDUP(200 / line time) +
> 1
> -	 */
> -	exit_scanlines =
> -		intel_usecs_to_scanlines(&crtc_state->uapi.adjusted_mode,
> 200) + 1;
> -
> -	if (drm_WARN_ON(display->drm, exit_scanlines > crtc_vdisplay))
> -		return;
> -
> -	crtc_state->dc3co_exitline = crtc_vdisplay - exit_scanlines;
> -}
> -
>  static bool intel_psr2_sel_fetch_config_valid(struct intel_dp *intel_dp,
>  					      struct intel_crtc_state *crtc_state)
> { @@ -1688,8 +1570,6 @@ static bool intel_psr2_config_valid(struct intel_dp
> *intel_dp,
>  		return false;
>  	}
> 
> -	tgl_dc3co_exitline_compute_config(intel_dp, crtc_state);
> -
>  	return true;
>  }
> 
> @@ -2004,12 +1884,6 @@ void intel_psr_get_config(struct intel_encoder
> *encoder,
>  	}
> 
>  	pipe_config->enable_psr2_su_region_et = intel_dp-
> >psr.su_region_et_enabled;
> -
> -	if (DISPLAY_VER(display) >= 12) {
> -		val = intel_de_read(display,
> -				    TRANS_EXITLINE(display, cpu_transcoder));
> -		pipe_config->dc3co_exitline =
> REG_FIELD_GET(EXITLINE_MASK, val);
> -	}
>  unlock:
>  	mutex_unlock(&intel_dp->psr.lock);
>  }
> @@ -2137,16 +2011,6 @@ static void intel_psr_enable_source(struct
> intel_dp *intel_dp,
> 
>  	psr_irq_control(intel_dp);
> 
> -	/*
> -	 * TODO: if future platforms supports DC3CO in more than one
> -	 * transcoder, EXITLINE will need to be unset when disabling PSR
> -	 */
> -	if (intel_dp->psr.dc3co_exitline)
> -		intel_de_rmw(display,
> -			     TRANS_EXITLINE(display, cpu_transcoder),
> -			     EXITLINE_MASK,
> -			     intel_dp->psr.dc3co_exitline << EXITLINE_SHIFT |
> EXITLINE_ENABLE);
> -
>  	if (HAS_PSR_HW_TRACKING(display) &&
> HAS_PSR2_SEL_FETCH(display))
>  		intel_de_rmw(display, CHICKEN_PAR1_1,
> IGNORE_PSR2_HW_TRACKING,
>  			     intel_dp->psr.psr2_sel_fetch_enabled ?
> @@ -2246,7 +2110,6 @@ static void intel_psr_enable_locked(struct intel_dp
> *intel_dp,
>  	/* DC5/DC6 requires at least 6 idle frames */
>  	val = usecs_to_jiffies(intel_get_frame_time_us(crtc_state) * 6);
>  	intel_dp->psr.dc3co_exit_delay = val;
> -	intel_dp->psr.dc3co_exitline = crtc_state->dc3co_exitline;
>  	intel_dp->psr.psr2_sel_fetch_enabled = crtc_state-
> >enable_psr2_sel_fetch;
>  	intel_dp->psr.su_region_et_enabled = crtc_state-
> >enable_psr2_su_region_et;
>  	intel_dp->psr.psr2_sel_fetch_cff_enabled = false; @@ -2325,8
> +2188,6 @@ static void intel_psr_exit(struct intel_dp *intel_dp)
>  		intel_de_rmw(display, TRANS_DP2_CTL(intel_dp-
> >psr.transcoder),
>  			     TRANS_DP2_PANEL_REPLAY_ENABLE, 0);
>  	} else if (intel_dp->psr.sel_update_enabled) {
> -		tgl_disallow_dc3co_on_psr2_exit(intel_dp);
> -
>  		val = intel_de_rmw(display,
>  				   EDP_PSR2_CTL(display, cpu_transcoder),
>  				   EDP_PSR2_ENABLE, 0);
> @@ -2468,7 +2329,6 @@ void intel_psr_disable(struct intel_dp *intel_dp,
> 
>  	mutex_unlock(&intel_dp->psr.lock);
>  	cancel_work_sync(&intel_dp->psr.work);
> -	cancel_delayed_work_sync(&intel_dp->psr.dc3co_work);
>  }
> 
>  /**
> @@ -2499,7 +2359,6 @@ void intel_psr_pause(struct intel_dp *intel_dp)
>  	mutex_unlock(&psr->lock);
> 
>  	cancel_work_sync(&psr->work);
> -	cancel_delayed_work_sync(&psr->dc3co_work);
>  }
> 
>  /**
> @@ -3650,34 +3509,6 @@ void intel_psr_invalidate(struct intel_display
> *display,
>  		mutex_unlock(&intel_dp->psr.lock);
>  	}
>  }
> -/*
> - * When we will be completely rely on PSR2 S/W tracking in future,
> - * intel_psr_flush() will invalidate and flush the PSR for ORIGIN_FLIP
> - * event also therefore tgl_dc3co_flush_locked() require to be changed
> - * accordingly in future.
> - */
> -static void
> -tgl_dc3co_flush_locked(struct intel_dp *intel_dp, unsigned int
> frontbuffer_bits,
> -		       enum fb_op_origin origin)
> -{
> -	struct intel_display *display = to_intel_display(intel_dp);
> -
> -	if (!intel_dp->psr.dc3co_exitline || !intel_dp-
> >psr.sel_update_enabled ||
> -	    !intel_dp->psr.active)
> -		return;
> -
> -	/*
> -	 * At every frontbuffer flush flip event modified delay of delayed
> work,
> -	 * when delayed work schedules that means display has been idle.
> -	 */
> -	if (!(frontbuffer_bits &
> -	    INTEL_FRONTBUFFER_ALL_MASK(intel_dp->psr.pipe)))
> -		return;
> -
> -	tgl_psr2_enable_dc3co(intel_dp);
> -	mod_delayed_work(display->wq.unordered, &intel_dp-
> >psr.dc3co_work,
> -			 intel_dp->psr.dc3co_exit_delay);
> -}
> 
>  static void _psr_flush_handle(struct intel_dp *intel_dp)  { @@ -3764,7
> +3595,6 @@ void intel_psr_flush(struct intel_display *display,
>  		if (origin == ORIGIN_FLIP ||
>  		    (origin == ORIGIN_CURSOR_UPDATE &&
>  		     !intel_dp->psr.psr2_sel_fetch_enabled)) {
> -			tgl_dc3co_flush_locked(intel_dp, frontbuffer_bits,
> origin);
>  			goto unlock;
>  		}
> 
> @@ -3823,7 +3653,6 @@ void intel_psr_init(struct intel_dp *intel_dp)
>  		intel_dp->psr.link_standby = connector-
> >panel.vbt.psr.full_link;
> 
>  	INIT_WORK(&intel_dp->psr.work, intel_psr_work);
> -	INIT_DELAYED_WORK(&intel_dp->psr.dc3co_work,
> tgl_dc3co_disable_work);
>  	mutex_init(&intel_dp->psr.lock);
>  }
> 
> --
> 2.43.0

✓ i915.CI.Full: success for drm/i915/display: Add DC3CO support (rev4)

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 108123 bytes --]

== Series Details ==

Series: drm/i915/display: Add DC3CO support (rev4)
URL   : https://patchwork.freedesktop.org/series/163939/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_18556_full -> Patchwork_163939v4_full
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_163939v4_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_163939v4_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_163939v4_full:

### IGT changes ###

#### Warnings ####

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-mtlp:         [SKIP][1] ([i915#15740]) -> [SKIP][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-mtlp-6/igt@kms_pm_dc@dc3co-vpb-simulation.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-mtlp-6/igt@kms_pm_dc@dc3co-vpb-simulation.html

  
Known issues
------------

  Here are the changes found in Patchwork_163939v4_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@dmabuf@all-tests:
    - shard-tglu:         NOTRUN -> [SKIP][3] ([i915#15931])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@dmabuf@all-tests.html

  * igt@gem_basic@multigpu-create-close:
    - shard-tglu:         NOTRUN -> [SKIP][4] ([i915#7697])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@gem_basic@multigpu-create-close.html

  * igt@gem_ccs@ctrl-surf-copy:
    - shard-rkl:          NOTRUN -> [SKIP][5] ([i915#3555] / [i915#9323])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_ccs@ctrl-surf-copy.html

  * igt@gem_ccs@large-ctrl-surf-copy:
    - shard-tglu-1:       NOTRUN -> [SKIP][6] ([i915#13008])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@gem_ccs@large-ctrl-surf-copy.html

  * igt@gem_ccs@suspend-resume:
    - shard-tglu:         NOTRUN -> [SKIP][7] ([i915#9323])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@gem_ccs@suspend-resume.html

  * igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0:
    - shard-dg2:          [PASS][8] -> [INCOMPLETE][9] ([i915#13356])
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-1/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-4/igt@gem_ccs@suspend-resume@linear-compressed-compfmt0-lmem0-lmem0.html

  * igt@gem_close_race@multigpu-basic-process:
    - shard-rkl:          NOTRUN -> [SKIP][10] ([i915#7697])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@gem_close_race@multigpu-basic-process.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-tglu-1:       NOTRUN -> [SKIP][11] ([i915#7697])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_ctx_persistence@engines-mixed-process:
    - shard-snb:          NOTRUN -> [SKIP][12] ([i915#1099])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-snb4/igt@gem_ctx_persistence@engines-mixed-process.html

  * igt@gem_ctx_persistence@heartbeat-hostile:
    - shard-dg2:          NOTRUN -> [SKIP][13] ([i915#8555])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-8/igt@gem_ctx_persistence@heartbeat-hostile.html

  * igt@gem_eio@in-flight-suspend:
    - shard-snb:          [PASS][14] -> [DMESG-WARN][15] ([i915#13390])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-snb7/igt@gem_eio@in-flight-suspend.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-snb6/igt@gem_eio@in-flight-suspend.html
    - shard-glk11:        NOTRUN -> [INCOMPLETE][16] ([i915#13390])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk11/igt@gem_eio@in-flight-suspend.html

  * igt@gem_eio@suspend:
    - shard-dg2:          [PASS][17] -> [ABORT][18] ([i915#15131])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-6/igt@gem_eio@suspend.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-10/igt@gem_eio@suspend.html

  * igt@gem_exec_balancer@parallel-dmabuf-import-out-fence:
    - shard-tglu-1:       NOTRUN -> [SKIP][19] ([i915#4525])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@gem_exec_balancer@parallel-dmabuf-import-out-fence.html

  * igt@gem_exec_balancer@parallel-ordering:
    - shard-rkl:          NOTRUN -> [SKIP][20] ([i915#4525]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_exec_balancer@parallel-ordering.html

  * igt@gem_exec_capture@capture-invisible@smem0:
    - shard-glk:          NOTRUN -> [SKIP][21] ([i915#6334]) +1 other test skip
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk5/igt@gem_exec_capture@capture-invisible@smem0.html

  * igt@gem_exec_capture@capture-recoverable:
    - shard-rkl:          NOTRUN -> [SKIP][22] ([i915#6344])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@gem_exec_capture@capture-recoverable.html

  * igt@gem_exec_fence@concurrent:
    - shard-dg2:          NOTRUN -> [SKIP][23] ([i915#4812])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_exec_fence@concurrent.html

  * igt@gem_exec_flush@basic-uc-set-default:
    - shard-dg2:          NOTRUN -> [SKIP][24] ([i915#3539])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_exec_flush@basic-uc-set-default.html

  * igt@gem_exec_reloc@basic-wc:
    - shard-rkl:          NOTRUN -> [SKIP][25] ([i915#3281]) +2 other tests skip
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_exec_reloc@basic-wc.html

  * igt@gem_exec_reloc@basic-write-wc-active:
    - shard-dg2:          NOTRUN -> [SKIP][26] ([i915#3281]) +2 other tests skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_exec_reloc@basic-write-wc-active.html

  * igt@gem_exec_schedule@preempt-queue-contexts-chain:
    - shard-dg2:          NOTRUN -> [SKIP][27] ([i915#4537] / [i915#4812])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_exec_schedule@preempt-queue-contexts-chain.html

  * igt@gem_exec_suspend@basic-s3-devices:
    - shard-dg1:          [PASS][28] -> [DMESG-WARN][29] ([i915#4423]) +4 other tests dmesg-warn
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-16/igt@gem_exec_suspend@basic-s3-devices.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-13/igt@gem_exec_suspend@basic-s3-devices.html

  * igt@gem_fence_thrash@bo-copy:
    - shard-dg2:          NOTRUN -> [SKIP][30] ([i915#4860])
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_fence_thrash@bo-copy.html

  * igt@gem_lmem_swapping@parallel-random-verify:
    - shard-rkl:          NOTRUN -> [SKIP][31] ([i915#4613]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@gem_lmem_swapping@parallel-random-verify.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][32] ([i915#4613]) +1 other test skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_lmem_swapping@random:
    - shard-glk:          NOTRUN -> [SKIP][33] ([i915#4613]) +2 other tests skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk2/igt@gem_lmem_swapping@random.html

  * igt@gem_lmem_swapping@smem-oom:
    - shard-tglu:         NOTRUN -> [SKIP][34] ([i915#4613]) +1 other test skip
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@gem_lmem_swapping@smem-oom.html

  * igt@gem_mmap_gtt@fault-concurrent-y:
    - shard-dg2:          NOTRUN -> [SKIP][35] ([i915#4077]) +5 other tests skip
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_mmap_gtt@fault-concurrent-y.html

  * igt@gem_mmap_wc@invalid-flags:
    - shard-dg2:          NOTRUN -> [SKIP][36] ([i915#4083]) +1 other test skip
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_mmap_wc@invalid-flags.html

  * igt@gem_partial_pwrite_pread@reads-uncached:
    - shard-rkl:          NOTRUN -> [SKIP][37] ([i915#3282]) +4 other tests skip
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_partial_pwrite_pread@reads-uncached.html

  * igt@gem_pread@display:
    - shard-dg2:          NOTRUN -> [SKIP][38] ([i915#3282])
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_pread@display.html

  * igt@gem_pread@exhaustion:
    - shard-tglu-1:       NOTRUN -> [WARN][39] ([i915#2658])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@gem_pread@exhaustion.html

  * igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted:
    - shard-rkl:          NOTRUN -> [SKIP][40] ([i915#4270])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@gem_pxp@dmabuf-shared-protected-dst-is-context-refcounted.html

  * igt@gem_pxp@fail-invalid-protected-context:
    - shard-dg2:          NOTRUN -> [SKIP][41] ([i915#4270])
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_pxp@fail-invalid-protected-context.html

  * igt@gem_pxp@hw-rejects-pxp-buffer:
    - shard-rkl:          NOTRUN -> [SKIP][42] ([i915#13717])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_pxp@hw-rejects-pxp-buffer.html

  * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:
    - shard-dg2:          NOTRUN -> [SKIP][43] ([i915#5190] / [i915#8428]) +1 other test skip
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled.html

  * igt@gem_softpin@noreloc-s3:
    - shard-rkl:          [PASS][44] -> [INCOMPLETE][45] ([i915#13809] / [i915#16226])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-2/igt@gem_softpin@noreloc-s3.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@gem_softpin@noreloc-s3.html

  * igt@gem_userptr_blits@coherency-unsync:
    - shard-rkl:          NOTRUN -> [SKIP][46] ([i915#3297]) +2 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_userptr_blits@coherency-unsync.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-tglu-1:       NOTRUN -> [SKIP][47] ([i915#3297]) +1 other test skip
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-glk:          NOTRUN -> [SKIP][48] ([i915#3323])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk3/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
    - shard-dg2:          NOTRUN -> [SKIP][49] ([i915#3297] / [i915#4880])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-dg2:          NOTRUN -> [SKIP][50] ([i915#2856])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@gen9_exec_parse@allowed-all.html

  * igt@gen9_exec_parse@allowed-single:
    - shard-glk:          NOTRUN -> [ABORT][51] ([i915#5566])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk3/igt@gen9_exec_parse@allowed-single.html

  * igt@gen9_exec_parse@bb-large:
    - shard-tglu-1:       NOTRUN -> [SKIP][52] ([i915#2527] / [i915#2856])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@gen9_exec_parse@bb-large.html

  * igt@gen9_exec_parse@shadow-peek:
    - shard-tglu:         NOTRUN -> [SKIP][53] ([i915#2527] / [i915#2856]) +1 other test skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@gen9_exec_parse@shadow-peek.html

  * igt@i915_module_load@reload-no-display:
    - shard-tglu-1:       NOTRUN -> [DMESG-WARN][54] ([i915#13029] / [i915#14545])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@i915_module_load@reload-no-display.html

  * igt@i915_pm_freq_api@freq-reset-multiple:
    - shard-tglu:         NOTRUN -> [SKIP][55] ([i915#8399]) +1 other test skip
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@i915_pm_freq_api@freq-reset-multiple.html

  * igt@i915_pm_freq_api@freq-suspend:
    - shard-tglu-1:       NOTRUN -> [SKIP][56] ([i915#8399])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@i915_pm_freq_api@freq-suspend.html

  * igt@i915_power@sanity:
    - shard-mtlp:         [PASS][57] -> [SKIP][58] ([i915#7984])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-mtlp-6/igt@i915_power@sanity.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-mtlp-6/igt@i915_power@sanity.html

  * igt@i915_query@test-query-geometry-subslices:
    - shard-rkl:          NOTRUN -> [SKIP][59] ([i915#5723])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@i915_query@test-query-geometry-subslices.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-glk:          NOTRUN -> [INCOMPLETE][60] ([i915#16182] / [i915#4817]) +1 other test incomplete
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk6/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@i915_suspend@forcewake:
    - shard-rkl:          [PASS][61] -> [INCOMPLETE][62] ([i915#4817])
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@i915_suspend@forcewake.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@i915_suspend@forcewake.html

  * igt@intel_hwmon@hwmon-read:
    - shard-tglu:         NOTRUN -> [SKIP][63] ([i915#7707])
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@intel_hwmon@hwmon-read.html

  * igt@kms_addfb_basic@invalid-smem-bo-on-discrete:
    - shard-rkl:          NOTRUN -> [SKIP][64] ([i915#12454] / [i915#12712])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_addfb_basic@invalid-smem-bo-on-discrete.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-snb:          NOTRUN -> [SKIP][65] ([i915#1769])
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-snb4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1:
    - shard-tglu:         [PASS][66] -> [FAIL][67] ([i915#15662]) +1 other test fail
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-tglu-2/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-4/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-1.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-90:
    - shard-dg2:          NOTRUN -> [SKIP][68] +4 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-8/igt@kms_big_fb@4-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-addfb-size-offset-overflow:
    - shard-tglu:         NOTRUN -> [SKIP][69] ([i915#5286]) +1 other test skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_big_fb@4-tiled-addfb-size-offset-overflow.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip:
    - shard-rkl:          NOTRUN -> [SKIP][70] ([i915#5286]) +3 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-tglu-1:       NOTRUN -> [SKIP][71] ([i915#5286]) +2 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-mtlp:         [PASS][72] -> [FAIL][73] ([i915#15733] / [i915#5138])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-mtlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-mtlp-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@linear-16bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][74] ([i915#3638]) +2 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_big_fb@linear-16bpp-rotate-90.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip:
    - shard-rkl:          NOTRUN -> [SKIP][75] ([i915#3828]) +1 other test skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-4/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-180-hflip.html

  * igt@kms_big_fb@y-tiled-16bpp-rotate-180:
    - shard-dg2:          NOTRUN -> [SKIP][76] ([i915#4538] / [i915#5190])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_big_fb@y-tiled-16bpp-rotate-180.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-1:
    - shard-glk11:        NOTRUN -> [SKIP][77] +91 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk11/igt@kms_ccs@bad-pixel-format-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-c-hdmi-a-2:
    - shard-glk10:        NOTRUN -> [SKIP][78] +77 other tests skip
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk10/igt@kms_ccs@bad-pixel-format-yf-tiled-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][79] ([i915#14544] / [i915#6095]) +3 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [SKIP][80] ([i915#6095]) +175 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-16/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-b-hdmi-a-4.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][81] ([i915#14098] / [i915#14544] / [i915#6095]) +1 other test skip
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs-cc@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][82] ([i915#10307] / [i915#6095]) +89 other tests skip
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-3.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][83] ([i915#12313])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_ccs@crc-primary-basic-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][84] ([i915#6095]) +44 other tests skip
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs-cc@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][85] ([i915#14098] / [i915#6095]) +38 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_ccs@crc-primary-suspend-4-tiled-dg2-rc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-dg2:          NOTRUN -> [SKIP][86] ([i915#12805])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [ABORT][87] ([i915#15132])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [INCOMPLETE][88] ([i915#15582] / [i915#16205]) +1 other test incomplete
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk8/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-b-dp-3:
    - shard-dg2:          NOTRUN -> [SKIP][89] ([i915#6095]) +3 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-10/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs@pipe-b-dp-3.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][90] ([i915#6095]) +61 other tests skip
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][91] ([i915#6095]) +29 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-rc-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [SKIP][92] +360 other tests skip
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk3/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-1.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-tglu-1:       NOTRUN -> [SKIP][93] ([i915#3742])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_cdclk@plane-scaling:
    - shard-tglu:         NOTRUN -> [SKIP][94] ([i915#3742])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_cdclk@plane-scaling.html

  * igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][95] ([i915#13783]) +3 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-6/igt@kms_cdclk@plane-scaling@pipe-c-hdmi-a-3.html

  * igt@kms_chamelium_frames@dp-crc-multiple:
    - shard-dg2:          NOTRUN -> [SKIP][96] ([i915#11151] / [i915#7828]) +1 other test skip
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_chamelium_frames@dp-crc-multiple.html

  * igt@kms_chamelium_frames@dp-crc-single:
    - shard-tglu-1:       NOTRUN -> [SKIP][97] ([i915#11151] / [i915#7828]) +3 other tests skip
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_chamelium_frames@dp-crc-single.html

  * igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats:
    - shard-rkl:          NOTRUN -> [SKIP][98] ([i915#11151] / [i915#7828]) +1 other test skip
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_chamelium_frames@hdmi-crc-nonplanar-formats.html

  * igt@kms_chamelium_hpd@dp-hpd-storm:
    - shard-tglu:         NOTRUN -> [SKIP][99] ([i915#11151] / [i915#7828]) +3 other tests skip
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_chamelium_hpd@dp-hpd-storm.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][100] ([i915#15865]) +1 other test skip
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@dp-mst-type-0-suspend-resume:
    - shard-tglu:         NOTRUN -> [SKIP][101] ([i915#15330])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_content_protection@dp-mst-type-0-suspend-resume.html

  * igt@kms_content_protection@legacy:
    - shard-dg2:          NOTRUN -> [SKIP][102] ([i915#15865])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_content_protection@legacy.html

  * igt@kms_content_protection@legacy-hdcp14:
    - shard-tglu:         NOTRUN -> [SKIP][103] ([i915#15865])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@kms_content_protection@legacy-hdcp14.html

  * igt@kms_content_protection@mei-interface:
    - shard-tglu-1:       NOTRUN -> [SKIP][104] ([i915#15865]) +1 other test skip
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_content_protection@mei-interface.html

  * igt@kms_cursor_crc@cursor-onscreen-256x85:
    - shard-tglu:         [PASS][105] -> [FAIL][106] ([i915#13566]) +1 other test fail
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-tglu-2/igt@kms_cursor_crc@cursor-onscreen-256x85.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-3/igt@kms_cursor_crc@cursor-onscreen-256x85.html

  * igt@kms_cursor_crc@cursor-random-128x42:
    - shard-rkl:          [PASS][107] -> [FAIL][108] ([i915#13566])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-3/igt@kms_cursor_crc@cursor-random-128x42.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_cursor_crc@cursor-random-128x42.html

  * igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [FAIL][109] ([i915#13566]) +3 other tests fail
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-random-512x170:
    - shard-rkl:          NOTRUN -> [SKIP][110] ([i915#13049]) +3 other tests skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_cursor_crc@cursor-random-512x170.html

  * igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [FAIL][111] ([i915#13566]) +1 other test fail
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@kms_cursor_crc@cursor-sliding-128x42@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic:
    - shard-dg2:          NOTRUN -> [SKIP][112] ([i915#13046] / [i915#5354]) +1 other test skip
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-8/igt@kms_cursor_legacy@2x-cursor-vs-flip-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - shard-rkl:          NOTRUN -> [SKIP][113] ([i915#4103]) +1 other test skip
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-rkl:          NOTRUN -> [SKIP][114] ([i915#9723])
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-tglu-1:       NOTRUN -> [SKIP][115] ([i915#13691])
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-rkl:          NOTRUN -> [SKIP][116] ([i915#3555] / [i915#3804])
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [SKIP][117] ([i915#3804])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html

  * igt@kms_dp_link_training@non-uhbr-sst:
    - shard-rkl:          NOTRUN -> [SKIP][118] ([i915#13749])
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-4/igt@kms_dp_link_training@non-uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-rkl:          NOTRUN -> [SKIP][119] ([i915#13707])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-rkl:          NOTRUN -> [SKIP][120] ([i915#3840])
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-rkl:          NOTRUN -> [SKIP][121] ([i915#3555] / [i915#3840])
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][122] ([i915#9878])
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk6/igt@kms_fbcon_fbt@fbc-suspend.html
    - shard-rkl:          [PASS][123] -> [ABORT][124] ([i915#15132])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-5/igt@kms_fbcon_fbt@fbc-suspend.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_feature_discovery@display-3x:
    - shard-dg2:          NOTRUN -> [SKIP][125] ([i915#16081])
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_feature_discovery@display-3x.html

  * igt@kms_feature_discovery@display-4x:
    - shard-tglu-1:       NOTRUN -> [SKIP][126] ([i915#16081])
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_feature_discovery@display-4x.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-rkl:          NOTRUN -> [SKIP][127] ([i915#9337])
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_feature_discovery@psr1:
    - shard-tglu:         NOTRUN -> [SKIP][128] ([i915#658])
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_feature_discovery@psr1.html

  * igt@kms_flip@2x-absolute-wf_vblank-interruptible:
    - shard-tglu-1:       NOTRUN -> [SKIP][129] ([i915#3637] / [i915#9934]) +2 other tests skip
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][130] ([i915#9934]) +5 other tests skip
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-dg2:          NOTRUN -> [SKIP][131] ([i915#9934]) +3 other tests skip
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@2x-plain-flip-interruptible:
    - shard-tglu:         NOTRUN -> [SKIP][132] ([i915#3637] / [i915#9934]) +5 other tests skip
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@kms_flip@2x-plain-flip-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][133] ([i915#15643]) +1 other test skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling:
    - shard-dg2:          NOTRUN -> [SKIP][134] ([i915#15643])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-dg2:          NOTRUN -> [SKIP][135] ([i915#15643] / [i915#5190])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-tglu:         NOTRUN -> [SKIP][136] ([i915#15643]) +1 other test skip
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling:
    - shard-rkl:          NOTRUN -> [SKIP][137] ([i915#15643])
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-upscaling.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][138] ([i915#15104] / [i915#15990])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-1p-offscreen-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-glk11:        NOTRUN -> [INCOMPLETE][139] ([i915#10056])
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk11/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-offscreen-pri-indfb-draw-blt:
    - shard-snb:          NOTRUN -> [SKIP][140] +88 other tests skip
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-snb4/igt@kms_frontbuffer_tracking@fbchdr-1p-offscreen-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-shrfb-plflip-blt:
    - shard-rkl:          NOTRUN -> [SKIP][141] ([i915#15989]) +19 other tests skip
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@fbchdr-rgb565-draw-mmap-cpu:
    - shard-dg2:          NOTRUN -> [SKIP][142] ([i915#15989]) +5 other tests skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_frontbuffer_tracking@fbchdr-rgb565-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc:
    - shard-rkl:          NOTRUN -> [SKIP][143] ([i915#1825]) +2 other tests skip
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][144] ([i915#15990] / [i915#8708]) +5 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt:
    - shard-dg2:          NOTRUN -> [SKIP][145] ([i915#15991] / [i915#5354]) +5 other tests skip
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-indfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render:
    - shard-tglu-1:       NOTRUN -> [SKIP][146] +52 other tests skip
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-pri-indfb-multidraw:
    - shard-dg2:          NOTRUN -> [SKIP][147] ([i915#15102]) +9 other tests skip
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-8/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-draw-render:
    - shard-tglu-1:       NOTRUN -> [SKIP][148] ([i915#15102]) +17 other tests skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-rte:
    - shard-rkl:          NOTRUN -> [SKIP][149] ([i915#15102]) +20 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsrhdr-1p-rte.html

  * igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-cur-indfb-draw-mmap-wc:
    - shard-rkl:          NOTRUN -> [SKIP][150] +54 other tests skip
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_frontbuffer_tracking@fbcpsrhdr-2p-scndscrn-cur-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@hdr-1p-offscreen-pri-shrfb-draw-mmap-gtt:
    - shard-tglu:         NOTRUN -> [SKIP][151] ([i915#15989]) +9 other tests skip
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_frontbuffer_tracking@hdr-1p-offscreen-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@hdr-1p-primscrn-pri-shrfb-draw-mmap-cpu:
    - shard-rkl:          [PASS][152] -> [SKIP][153] ([i915#15989]) +17 other tests skip
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-pri-shrfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@hdr-1p-primscrn-spr-indfb-draw-mmap-wc:
    - shard-dg2:          NOTRUN -> [SKIP][154] ([i915#15990]) +5 other tests skip
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_frontbuffer_tracking@hdr-1p-primscrn-spr-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-mmap-gtt:
    - shard-glk:          [PASS][155] -> [SKIP][156] +28 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-glk8/igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-mmap-gtt.html
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk2/igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-pwrite:
    - shard-tglu-1:       NOTRUN -> [SKIP][157] ([i915#15989]) +10 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_frontbuffer_tracking@hdr-rgb101010-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt:
    - shard-rkl:          NOTRUN -> [SKIP][158] ([i915#15102] / [i915#3023]) +11 other tests skip
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-spr-indfb-draw-render:
    - shard-dg2:          NOTRUN -> [SKIP][159] ([i915#15991]) +14 other tests skip
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_frontbuffer_tracking@psrhdr-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psrhdr-rgb565-draw-blt:
    - shard-tglu:         NOTRUN -> [SKIP][160] ([i915#15102]) +17 other tests skip
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_frontbuffer_tracking@psrhdr-rgb565-draw-blt.html

  * igt@kms_hdmi_inject@inject-4k:
    - shard-mtlp:         [PASS][161] -> [SKIP][162] ([i915#15725])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-mtlp-3/igt@kms_hdmi_inject@inject-4k.html
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-mtlp-1/igt@kms_hdmi_inject@inject-4k.html

  * igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-1-xrgb2101010:
    - shard-dg2:          NOTRUN -> [SKIP][163] ([i915#16012]) +1 other test skip
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-4/igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-1-xrgb2101010.html

  * igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-2-xrgb2101010:
    - shard-rkl:          NOTRUN -> [INCOMPLETE][164] ([i915#15436])
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-2-xrgb2101010.html

  * igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-3-xrgb16161616f:
    - shard-dg1:          NOTRUN -> [SKIP][165] ([i915#16012]) +5 other tests skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-12/igt@kms_hdr@bpc-switch-suspend@pipe-a-hdmi-a-3-xrgb16161616f.html

  * igt@kms_hdr@invalid-hdr:
    - shard-tglu-1:       NOTRUN -> [SKIP][166] ([i915#16012] / [i915#3555] / [i915#8228])
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_hdr@invalid-hdr.html

  * igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-1-xrgb16161616f:
    - shard-rkl:          NOTRUN -> [SKIP][167] ([i915#16012]) +1 other test skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-1-xrgb16161616f.html
    - shard-tglu-1:       NOTRUN -> [SKIP][168] ([i915#16012]) +1 other test skip
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_hdr@invalid-hdr@pipe-a-hdmi-a-1-xrgb16161616f.html

  * igt@kms_hdr@static-toggle-suspend@pipe-a-hdmi-a-3-xrgb16161616f:
    - shard-dg2:          NOTRUN -> [SKIP][169] ([i915#16011]) +1 other test skip
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-6/igt@kms_hdr@static-toggle-suspend@pipe-a-hdmi-a-3-xrgb16161616f.html

  * igt@kms_hdr@static-toggle@pipe-a-hdmi-a-1-xrgb16161616f:
    - shard-rkl:          NOTRUN -> [SKIP][170] ([i915#16011]) +3 other tests skip
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_hdr@static-toggle@pipe-a-hdmi-a-1-xrgb16161616f.html

  * igt@kms_hdr@static-toggle@pipe-a-hdmi-a-4-xrgb2101010:
    - shard-dg1:          NOTRUN -> [SKIP][171] ([i915#16011]) +5 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-16/igt@kms_hdr@static-toggle@pipe-a-hdmi-a-4-xrgb2101010.html

  * igt@kms_joiner@basic-big-joiner:
    - shard-tglu:         NOTRUN -> [SKIP][172] ([i915#15460])
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_joiner@basic-big-joiner.html

  * igt@kms_joiner@basic-force-big-joiner:
    - shard-rkl:          NOTRUN -> [SKIP][173] ([i915#15459])
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_joiner@basic-force-big-joiner.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][174] ([i915#15460])
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          NOTRUN -> [SKIP][175] ([i915#15815])
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-rkl:          NOTRUN -> [SKIP][176] ([i915#6301])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_panel_fitting@legacy:
    - shard-tglu:         NOTRUN -> [SKIP][177] ([i915#6301])
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_panel_fitting@legacy.html

  * igt@kms_pipe_stress@stress-xrgb8888-yftiled:
    - shard-rkl:          NOTRUN -> [SKIP][178] ([i915#14712])
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html

  * igt@kms_plane@pixel-format-4-tiled-modifier:
    - shard-tglu:         NOTRUN -> [SKIP][179] ([i915#15709])
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@kms_plane@pixel-format-4-tiled-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-ccs-modifier:
    - shard-rkl:          NOTRUN -> [SKIP][180] ([i915#15709]) +3 other tests skip
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_plane@pixel-format-y-tiled-ccs-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier:
    - shard-tglu-1:       NOTRUN -> [SKIP][181] ([i915#15709])
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier@pipe-a-plane-7:
    - shard-tglu-1:       NOTRUN -> [SKIP][182] ([i915#15608]) +1 other test skip
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-modifier@pipe-a-plane-7.html

  * igt@kms_plane@pixel-format-y-tiled-modifier@pipe-b-plane-7:
    - shard-tglu:         NOTRUN -> [SKIP][183] ([i915#15608]) +1 other test skip
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_plane@pixel-format-y-tiled-modifier@pipe-b-plane-7.html

  * igt@kms_plane@pixel-format-yf-tiled-modifier:
    - shard-dg2:          NOTRUN -> [SKIP][184] ([i915#15709])
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_plane@pixel-format-yf-tiled-modifier.html

  * igt@kms_plane_alpha_blend@alpha-basic:
    - shard-glk:          NOTRUN -> [FAIL][185] ([i915#12178])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk9/igt@kms_plane_alpha_blend@alpha-basic.html

  * igt@kms_plane_alpha_blend@alpha-basic@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][186] ([i915#7862]) +1 other test fail
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk9/igt@kms_plane_alpha_blend@alpha-basic@pipe-a-hdmi-a-1.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb:
    - shard-glk:          NOTRUN -> [FAIL][187] ([i915#10647] / [i915#12169])
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk3/igt@kms_plane_alpha_blend@alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][188] ([i915#10647]) +1 other test fail
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk3/igt@kms_plane_alpha_blend@alpha-opaque-fb@pipe-a-hdmi-a-1.html

  * igt@kms_plane_lowres@tiling-yf:
    - shard-rkl:          NOTRUN -> [SKIP][189] ([i915#3555]) +2 other tests skip
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_plane_lowres@tiling-yf.html

  * igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a:
    - shard-rkl:          NOTRUN -> [SKIP][190] ([i915#15329]) +3 other tests skip
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_plane_scaling@plane-downscale-factor-0-75-with-rotation@pipe-a.html

  * igt@kms_pm_backlight@bad-brightness:
    - shard-tglu:         NOTRUN -> [SKIP][191] ([i915#12343] / [i915#9812])
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_pm_backlight@bad-brightness.html

  * igt@kms_pm_backlight@basic-brightness:
    - shard-rkl:          NOTRUN -> [SKIP][192] ([i915#12343] / [i915#5354])
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@kms_pm_backlight@basic-brightness.html

  * igt@kms_pm_backlight@fade-with-dpms:
    - shard-tglu-1:       NOTRUN -> [SKIP][193] ([i915#12343] / [i915#9812])
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_pm_backlight@fade-with-dpms.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-tglu-1:       NOTRUN -> [SKIP][194] ([i915#3828])
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_pm_lpsp@screens-disabled:
    - shard-dg2:          NOTRUN -> [SKIP][195] ([i915#8430])
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_pm_lpsp@screens-disabled.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-tglu:         NOTRUN -> [SKIP][196] ([i915#15073]) +1 other test skip
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-rkl:          [PASS][197] -> [SKIP][198] ([i915#15073]) +1 other test skip
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-3/igt@kms_pm_rpm@modeset-non-lpsp.html
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-dg1:          [PASS][199] -> [SKIP][200] ([i915#15073]) +2 other tests skip
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-13/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-14/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_prime@d3hot:
    - shard-tglu-1:       NOTRUN -> [SKIP][201] ([i915#6524])
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_prime@d3hot.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf:
    - shard-snb:          NOTRUN -> [SKIP][202] ([i915#11520])
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-snb4/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area:
    - shard-dg2:          NOTRUN -> [SKIP][203] ([i915#11520]) +2 other tests skip
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf:
    - shard-glk10:        NOTRUN -> [SKIP][204] ([i915#11520]) +1 other test skip
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk10/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf:
    - shard-tglu:         NOTRUN -> [SKIP][205] ([i915#11520]) +3 other tests skip
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html
    - shard-glk11:        NOTRUN -> [SKIP][206] ([i915#11520])
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk11/igt@kms_psr2_sf@pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf:
    - shard-tglu-1:       NOTRUN -> [SKIP][207] ([i915#11520]) +3 other tests skip
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area:
    - shard-rkl:          NOTRUN -> [SKIP][208] ([i915#11520]) +4 other tests skip
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_psr2_sf@psr2-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area:
    - shard-glk:          NOTRUN -> [SKIP][209] ([i915#11520]) +7 other tests skip
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk5/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_su@frontbuffer-xrgb8888:
    - shard-tglu:         NOTRUN -> [SKIP][210] ([i915#9683])
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@kms_psr2_su@frontbuffer-xrgb8888.html

  * igt@kms_psr2_su@page_flip-p010:
    - shard-rkl:          NOTRUN -> [SKIP][211] ([i915#9683])
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_psr2_su@page_flip-p010.html

  * igt@kms_psr@fbc-psr-cursor-mmap-gtt:
    - shard-dg2:          NOTRUN -> [SKIP][212] ([i915#1072] / [i915#9732]) +8 other tests skip
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_psr@fbc-psr-cursor-mmap-gtt.html

  * igt@kms_psr@pr-cursor-plane-onoff:
    - shard-tglu-1:       NOTRUN -> [SKIP][213] ([i915#9732]) +11 other tests skip
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_psr@pr-cursor-plane-onoff.html

  * igt@kms_psr@pr-primary-page-flip:
    - shard-tglu:         NOTRUN -> [SKIP][214] ([i915#9732]) +8 other tests skip
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@kms_psr@pr-primary-page-flip.html

  * igt@kms_psr@psr-sprite-plane-onoff:
    - shard-rkl:          NOTRUN -> [SKIP][215] ([i915#1072] / [i915#9732]) +11 other tests skip
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_psr@psr-sprite-plane-onoff.html

  * igt@kms_rotation_crc@bad-tiling:
    - shard-dg2:          NOTRUN -> [SKIP][216] ([i915#12755] / [i915#15867])
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_rotation_crc@bad-tiling.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-180:
    - shard-tglu:         NOTRUN -> [SKIP][217] ([i915#5289])
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_rotation_crc@primary-4-tiled-reflect-x-180.html

  * igt@kms_rotation_crc@primary-y-tiled-reflect-x-180:
    - shard-dg2:          NOTRUN -> [SKIP][218] ([i915#5190]) +1 other test skip
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-8/igt@kms_rotation_crc@primary-y-tiled-reflect-x-180.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-dg2:          NOTRUN -> [SKIP][219] ([i915#3555]) +2 other tests skip
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-tglu-1:       NOTRUN -> [SKIP][220] ([i915#3555])
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-1/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@kms_setmode@invalid-clone-single-crtc:
    - shard-tglu:         NOTRUN -> [SKIP][221] ([i915#3555])
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-10/igt@kms_setmode@invalid-clone-single-crtc.html

  * igt@kms_vblank@ts-continuation-dpms-suspend:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][222] ([i915#12276]) +1 other test incomplete
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-glk10/igt@kms_vblank@ts-continuation-dpms-suspend.html

  * igt@kms_vrr@flip-basic-fastset:
    - shard-tglu:         NOTRUN -> [SKIP][223] ([i915#9906]) +1 other test skip
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@kms_vrr@flip-basic-fastset.html

  * igt@kms_vrr@flip-dpms:
    - shard-dg2:          NOTRUN -> [SKIP][224] ([i915#15243] / [i915#3555])
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@kms_vrr@flip-dpms.html

  * igt@perf@blocking@0-rcs0:
    - shard-tglu:         [PASS][225] -> [FAIL][226] ([i915#10538]) +1 other test fail
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-tglu-10/igt@perf@blocking@0-rcs0.html
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-9/igt@perf@blocking@0-rcs0.html

  * igt@perf_pmu@rc6-all-gts:
    - shard-rkl:          NOTRUN -> [SKIP][227] ([i915#8516])
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@perf_pmu@rc6-all-gts.html

  * igt@prime_vgem@basic-write:
    - shard-rkl:          NOTRUN -> [SKIP][228] ([i915#3291] / [i915#3708])
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@prime_vgem@basic-write.html

  * igt@prime_vgem@fence-write-hang:
    - shard-tglu:         NOTRUN -> [SKIP][229] +53 other tests skip
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-tglu-2/igt@prime_vgem@fence-write-hang.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all:
    - shard-rkl:          NOTRUN -> [SKIP][230] ([i915#9917])
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@sriov_basic@enable-vfs-bind-unbind-each-numvfs-all.html

  * igt@tools_test@sysfs_l3_parity:
    - shard-dg2:          NOTRUN -> [SKIP][231] ([i915#4818])
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-7/igt@tools_test@sysfs_l3_parity.html

  
#### Possible fixes ####

  * igt@gem_eio@suspend:
    - shard-rkl:          [ABORT][232] ([i915#15131]) -> [PASS][233]
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@gem_eio@suspend.html
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@gem_eio@suspend.html

  * igt@gem_workarounds@suspend-resume:
    - shard-rkl:          [ABORT][234] ([i915#15152]) -> [PASS][235]
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-1/igt@gem_workarounds@suspend-resume.html
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-3/igt@gem_workarounds@suspend-resume.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-rkl:          [INCOMPLETE][236] ([i915#13356]) -> [PASS][237]
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@i915_pm_rpm@system-suspend.html
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@i915_pm_rpm@system-suspend.html

  * igt@i915_pm_rps@reset:
    - shard-snb:          [TIMEOUT][238] ([i915#16162]) -> [PASS][239]
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-snb4/igt@i915_pm_rps@reset.html
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-snb4/igt@i915_pm_rps@reset.html

  * igt@kms_async_flips@async-flip-suspend-resume:
    - shard-rkl:          [INCOMPLETE][240] ([i915#12761]) -> [PASS][241]
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-3/igt@kms_async_flips@async-flip-suspend-resume.html
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-5/igt@kms_async_flips@async-flip-suspend-resume.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-0:
    - shard-dg1:          [DMESG-WARN][242] ([i915#4423]) -> [PASS][243]
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-15/igt@kms_big_fb@y-tiled-8bpp-rotate-0.html
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-15/igt@kms_big_fb@y-tiled-8bpp-rotate-0.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          [INCOMPLETE][244] ([i915#15582]) -> [PASS][245]
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-2.html
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-2:
    - shard-rkl:          [FAIL][246] ([i915#13566]) -> [PASS][247] +1 other test pass
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-4/igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-2.html
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-7/igt@kms_cursor_crc@cursor-onscreen-256x85@pipe-a-hdmi-a-2.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-valid-mode:
    - shard-rkl:          [ABORT][248] -> [PASS][249] +1 other test pass
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-valid-mode.html
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytilegen12rcccs-downscaling@pipe-a-valid-mode.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-rkl:          [INCOMPLETE][250] ([i915#10056]) -> [PASS][251]
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-draw-render:
    - shard-dg2:          [SKIP][252] ([i915#15989]) -> [PASS][253] +2 other tests pass
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-6/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-draw-render.html
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-10/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-onoff:
    - shard-rkl:          [SKIP][254] ([i915#15989]) -> [PASS][255] +7 other tests pass
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-onoff.html
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_frontbuffer_tracking@fbchdr-1p-primscrn-spr-indfb-onoff.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-dg2:          [SKIP][256] ([i915#15459]) -> [PASS][257]
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-10/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-dg1:          [SKIP][258] ([i915#15073]) -> [PASS][259]
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-19/igt@kms_pm_rpm@dpms-lpsp.html
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-15/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-rkl:          [SKIP][260] ([i915#15073]) -> [PASS][261] +1 other test pass
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-3/igt@kms_pm_rpm@modeset-lpsp.html
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-dg2:          [SKIP][262] ([i915#15073]) -> [PASS][263] +1 other test pass
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-4/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-6/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_vblank@ts-continuation-suspend:
    - shard-dg2:          [ABORT][264] ([i915#15132]) -> [PASS][265]
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-10/igt@kms_vblank@ts-continuation-suspend.html
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-8/igt@kms_vblank@ts-continuation-suspend.html

  * igt@perf_pmu@busy-double-start@vecs1:
    - shard-dg2:          [FAIL][266] ([i915#4349]) -> [PASS][267] +4 other tests pass
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-4/igt@perf_pmu@busy-double-start@vecs1.html
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-6/igt@perf_pmu@busy-double-start@vecs1.html

  
#### Warnings ####

  * igt@gem_ccs@block-copy-compressed:
    - shard-rkl:          [SKIP][268] ([i915#14544] / [i915#3555] / [i915#9323]) -> [SKIP][269] ([i915#3555] / [i915#9323])
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_ccs@block-copy-compressed.html
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@gem_ccs@block-copy-compressed.html

  * igt@gem_ccs@large-ctrl-surf-copy:
    - shard-rkl:          [SKIP][270] ([i915#13008]) -> [SKIP][271] ([i915#13008] / [i915#14544])
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@gem_ccs@large-ctrl-surf-copy.html
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@gem_ccs@large-ctrl-surf-copy.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-rkl:          [SKIP][272] ([i915#14544] / [i915#7697]) -> [SKIP][273] ([i915#7697])
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_close_race@multigpu-basic-threads.html
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_exec_balancer@parallel:
    - shard-rkl:          [SKIP][274] ([i915#4525]) -> [SKIP][275] ([i915#14544] / [i915#4525])
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-2/igt@gem_exec_balancer@parallel.html
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_balancer@parallel-out-fence:
    - shard-rkl:          [SKIP][276] ([i915#14544] / [i915#4525]) -> [SKIP][277] ([i915#4525]) +1 other test skip
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_exec_balancer@parallel-out-fence.html
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@gem_exec_balancer@parallel-out-fence.html

  * igt@gem_exec_reloc@basic-cpu-noreloc:
    - shard-rkl:          [SKIP][278] ([i915#14544] / [i915#3281]) -> [SKIP][279] ([i915#3281]) +6 other tests skip
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_exec_reloc@basic-cpu-noreloc.html
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_exec_reloc@basic-cpu-noreloc.html

  * igt@gem_exec_reloc@basic-gtt-wc-noreloc:
    - shard-rkl:          [SKIP][280] ([i915#3281]) -> [SKIP][281] ([i915#14544] / [i915#3281]) +2 other tests skip
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@gem_exec_reloc@basic-gtt-wc-noreloc.html

  * igt@gem_lmem_evict@dontneed-evict-race:
    - shard-rkl:          [SKIP][282] ([i915#4613] / [i915#7582]) -> [SKIP][283] ([i915#14544] / [i915#4613] / [i915#7582])
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-2/igt@gem_lmem_evict@dontneed-evict-race.html
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@gem_lmem_evict@dontneed-evict-race.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-rkl:          [SKIP][284] ([i915#4613]) -> [SKIP][285] ([i915#14544] / [i915#4613])
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@gem_lmem_swapping@parallel-random-verify-ccs.html
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_lmem_swapping@verify:
    - shard-rkl:          [SKIP][286] ([i915#14544] / [i915#4613]) -> [SKIP][287] ([i915#4613])
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_lmem_swapping@verify.html
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_lmem_swapping@verify.html

  * igt@gem_pread@snoop:
    - shard-rkl:          [SKIP][288] ([i915#14544] / [i915#3282]) -> [SKIP][289] ([i915#3282]) +3 other tests skip
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_pread@snoop.html
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@gem_pread@snoop.html

  * igt@gem_pwrite@basic-random:
    - shard-rkl:          [SKIP][290] ([i915#3282]) -> [SKIP][291] ([i915#14544] / [i915#3282]) +2 other tests skip
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@gem_pwrite@basic-random.html
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@gem_pwrite@basic-random.html

  * igt@gem_set_tiling_vs_blt@tiled-to-tiled:
    - shard-rkl:          [SKIP][292] ([i915#8411]) -> [SKIP][293] ([i915#14544] / [i915#8411])
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@gem_set_tiling_vs_blt@tiled-to-tiled.html

  * igt@gem_set_tiling_vs_blt@untiled-to-tiled:
    - shard-rkl:          [SKIP][294] ([i915#14544] / [i915#8411]) -> [SKIP][295] ([i915#8411])
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_set_tiling_vs_blt@untiled-to-tiled.html

  * igt@gem_userptr_blits@create-destroy-unsync:
    - shard-rkl:          [SKIP][296] ([i915#14544] / [i915#3297]) -> [SKIP][297] ([i915#3297]) +2 other tests skip
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@gem_userptr_blits@create-destroy-unsync.html
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@gem_userptr_blits@create-destroy-unsync.html

  * igt@gen9_exec_parse@batch-zero-length:
    - shard-rkl:          [SKIP][298] ([i915#2527]) -> [SKIP][299] ([i915#14544] / [i915#2527])
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-2/igt@gen9_exec_parse@batch-zero-length.html
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@gen9_exec_parse@batch-zero-length.html

  * igt@i915_pm_freq_api@freq-suspend:
    - shard-rkl:          [SKIP][300] ([i915#14544] / [i915#8399]) -> [SKIP][301] ([i915#8399])
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@i915_pm_freq_api@freq-suspend.html
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@i915_pm_freq_api@freq-suspend.html

  * igt@i915_query@query-topology-unsupported:
    - shard-rkl:          [SKIP][302] ([i915#16079]) -> [SKIP][303] ([i915#14544] / [i915#16079])
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@i915_query@query-topology-unsupported.html
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@i915_query@query-topology-unsupported.html

  * igt@kms_atomic@plane-primary-overlay-mutable-zpos:
    - shard-rkl:          [SKIP][304] ([i915#14544] / [i915#9531]) -> [SKIP][305] ([i915#9531])
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-rkl:          [SKIP][306] ([i915#14544] / [i915#5286]) -> [SKIP][307] ([i915#5286]) +2 other tests skip
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-rkl:          [SKIP][308] ([i915#5286]) -> [SKIP][309] ([i915#14544] / [i915#5286])
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_big_fb@y-tiled-8bpp-rotate-90:
    - shard-rkl:          [SKIP][310] ([i915#14544] / [i915#3638]) -> [SKIP][311] ([i915#3638])
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_big_fb@y-tiled-8bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
    - shard-rkl:          [SKIP][312] -> [SKIP][313] ([i915#14544]) +24 other tests skip
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-2/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs:
    - shard-rkl:          [SKIP][314] ([i915#14098] / [i915#14544] / [i915#6095]) -> [SKIP][315] ([i915#14098] / [i915#6095]) +7 other tests skip
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs.html
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2:
    - shard-rkl:          [SKIP][316] ([i915#14544] / [i915#6095]) -> [SKIP][317] ([i915#6095]) +3 other tests skip
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_ccs@bad-rotation-90-4-tiled-mtl-rc-ccs@pipe-b-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc:
    - shard-rkl:          [SKIP][318] ([i915#14098] / [i915#6095]) -> [SKIP][319] ([i915#14098] / [i915#14544] / [i915#6095]) +1 other test skip
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc.html
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs:
    - shard-rkl:          [SKIP][320] ([i915#12313] / [i915#14544]) -> [SKIP][321] ([i915#12313])
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs:
    - shard-rkl:          [INCOMPLETE][322] ([i915#15582]) -> [ABORT][323] ([i915#15132])
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs.html
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs.html

  * igt@kms_cdclk@mode-transition-all-outputs:
    - shard-rkl:          [SKIP][324] ([i915#3742]) -> [SKIP][325] ([i915#14544] / [i915#3742])
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_cdclk@mode-transition-all-outputs.html
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_cdclk@mode-transition-all-outputs.html

  * igt@kms_chamelium_frames@dp-crc-single:
    - shard-rkl:          [SKIP][326] ([i915#11151] / [i915#7828]) -> [SKIP][327] ([i915#11151] / [i915#14544] / [i915#7828])
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_chamelium_frames@dp-crc-single.html
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_chamelium_frames@dp-crc-single.html

  * igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode:
    - shard-rkl:          [SKIP][328] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][329] ([i915#11151] / [i915#7828]) +5 other tests skip
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_chamelium_hpd@hdmi-hpd-with-enabled-mode.html

  * igt@kms_content_protection@mei-interface:
    - shard-rkl:          [SKIP][330] ([i915#15865]) -> [SKIP][331] ([i915#14544] / [i915#15865])
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_content_protection@mei-interface.html
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@type1:
    - shard-rkl:          [SKIP][332] ([i915#14544] / [i915#15865]) -> [SKIP][333] ([i915#15865])
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_content_protection@type1.html
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_content_protection@type1.html

  * igt@kms_display_modes@extended-mode-basic:
    - shard-rkl:          [SKIP][334] ([i915#13691]) -> [SKIP][335] ([i915#13691] / [i915#14544])
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_display_modes@extended-mode-basic.html
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_display_modes@extended-mode-basic.html

  * igt@kms_dsc@dsc-basic:
    - shard-rkl:          [SKIP][336] ([i915#14544] / [i915#3555] / [i915#3840]) -> [SKIP][337] ([i915#3555] / [i915#3840])
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_dsc@dsc-basic.html
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_dsc@dsc-basic.html

  * igt@kms_feature_discovery@display-4x:
    - shard-rkl:          [SKIP][338] ([i915#14544] / [i915#16081]) -> [SKIP][339] ([i915#16081])
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_feature_discovery@display-4x.html
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_feature_discovery@display-4x.html

  * igt@kms_flip@2x-absolute-wf_vblank-interruptible:
    - shard-rkl:          [SKIP][340] ([i915#9934]) -> [SKIP][341] ([i915#14544] / [i915#9934]) +1 other test skip
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
    - shard-rkl:          [SKIP][342] ([i915#14544] / [i915#9934]) -> [SKIP][343] ([i915#9934]) +2 other tests skip
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling:
    - shard-rkl:          [SKIP][344] ([i915#15643]) -> [SKIP][345] ([i915#14544] / [i915#15643]) +2 other tests skip
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-upscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling:
    - shard-rkl:          [SKIP][346] ([i915#14544] / [i915#15643]) -> [SKIP][347] ([i915#15643])
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_flip_scaled_crc@flip-32bpp-yftileccs-to-64bpp-yftile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-dg1:          [SKIP][348] ([i915#15643] / [i915#4423]) -> [SKIP][349] ([i915#15643])
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-16/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-13/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-rkl:          [SKIP][350] ([i915#14544] / [i915#1825]) -> [SKIP][351] ([i915#1825]) +4 other tests skip
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-8/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg1:          [SKIP][352] ([i915#15990] / [i915#4423] / [i915#8708]) -> [SKIP][353] ([i915#15990] / [i915#8708])
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-18/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-12/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-cur-indfb-onoff:
    - shard-rkl:          [SKIP][354] ([i915#14544]) -> [SKIP][355] +41 other tests skip
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-cur-indfb-onoff.html
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_frontbuffer_tracking@fbchdr-2p-primscrn-cur-indfb-onoff.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu:
    - shard-rkl:          [SKIP][356] ([i915#15102] / [i915#3023]) -> [SKIP][357] ([i915#14544] / [i915#15102] / [i915#3023]) +3 other tests skip
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu.html
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite:
    - shard-dg2:          [SKIP][358] ([i915#10433] / [i915#15102]) -> [SKIP][359] ([i915#15102]) +4 other tests skip
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][360] ([i915#1825]) -> [SKIP][361] ([i915#14544] / [i915#1825]) +4 other tests skip
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt.html
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt:
    - shard-dg2:          [SKIP][362] ([i915#15102]) -> [SKIP][363] ([i915#10433] / [i915#15102]) +1 other test skip
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg2-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-pwrite:
    - shard-dg1:          [SKIP][364] -> [SKIP][365] ([i915#4423])
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-12/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-pwrite.html
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-19/igt@kms_frontbuffer_tracking@psr-2p-primscrn-spr-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-rgb565-draw-render:
    - shard-rkl:          [SKIP][366] ([i915#14544] / [i915#15102] / [i915#3023]) -> [SKIP][367] ([i915#15102] / [i915#3023]) +7 other tests skip
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html

  * igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-cur-indfb-draw-mmap-gtt:
    - shard-rkl:          [SKIP][368] ([i915#14544] / [i915#15102]) -> [SKIP][369] ([i915#15102]) +13 other tests skip
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-cur-indfb-draw-mmap-gtt.html
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-cur-indfb-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-spr-indfb-move:
    - shard-rkl:          [SKIP][370] ([i915#15102]) -> [SKIP][371] ([i915#14544] / [i915#15102]) +5 other tests skip
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-spr-indfb-move.html
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_frontbuffer_tracking@psrhdr-1p-primscrn-spr-indfb-move.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-rkl:          [SKIP][372] ([i915#16012] / [i915#3555] / [i915#8228]) -> [INCOMPLETE][373] ([i915#15436])
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_hdr@bpc-switch-suspend.html
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_hdr@invalid-hdr:
    - shard-rkl:          [SKIP][374] ([i915#14544] / [i915#3555] / [i915#8228]) -> [SKIP][375] ([i915#16012] / [i915#3555] / [i915#8228])
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_hdr@invalid-hdr.html
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_hdr@invalid-hdr.html

  * igt@kms_joiner@basic-ultra-joiner:
    - shard-rkl:          [SKIP][376] ([i915#15458]) -> [SKIP][377] ([i915#14544] / [i915#15458])
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-2/igt@kms_joiner@basic-ultra-joiner.html
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_joiner@basic-ultra-joiner.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-rkl:          [SKIP][378] ([i915#15460]) -> [SKIP][379] ([i915#14544] / [i915#15460])
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_joiner@invalid-modeset-big-joiner.html
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-dg1:          [SKIP][380] ([i915#4423] / [i915#6301]) -> [SKIP][381] ([i915#6301])
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-13/igt@kms_panel_fitting@atomic-fastset.html
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-12/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping:
    - shard-rkl:          [SKIP][382] ([i915#15709]) -> [SKIP][383] ([i915#14544] / [i915#15709])
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping.html
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier:
    - shard-rkl:          [SKIP][384] ([i915#14544] / [i915#15709]) -> [SKIP][385] ([i915#15709]) +1 other test skip
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_plane@pixel-format-y-tiled-gen12-mc-ccs-modifier.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-dg1:          [SKIP][386] ([i915#13958] / [i915#4423]) -> [SKIP][387] ([i915#13958])
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-dg1-12/igt@kms_plane_multiple@2x-tiling-x.html
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-dg1-18/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_plane_multiple@tiling-4:
    - shard-rkl:          [SKIP][388] ([i915#14259]) -> [SKIP][389] ([i915#14259] / [i915#14544])
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-2/igt@kms_plane_multiple@tiling-4.html
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_plane_multiple@tiling-4.html

  * igt@kms_pm_dc@dc5-retention-flops:
    - shard-rkl:          [SKIP][390] ([i915#14544] / [i915#3828]) -> [SKIP][391] ([i915#3828])
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_pm_dc@dc5-retention-flops.html
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_pm_dc@dc5-retention-flops.html

  * igt@kms_prime@basic-crc-hybrid:
    - shard-rkl:          [SKIP][392] ([i915#6524]) -> [SKIP][393] ([i915#14544] / [i915#6524])
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_prime@basic-crc-hybrid.html
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_prime@basic-crc-hybrid.html

  * igt@kms_prime@d3hot:
    - shard-rkl:          [SKIP][394] ([i915#14544] / [i915#6524]) -> [SKIP][395] ([i915#6524])
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_prime@d3hot.html
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_prime@d3hot.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf:
    - shard-rkl:          [SKIP][396] ([i915#11520] / [i915#14544]) -> [SKIP][397] ([i915#11520]) +2 other tests skip
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf.html
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area:
    - shard-rkl:          [SKIP][398] ([i915#11520]) -> [SKIP][399] ([i915#11520] / [i915#14544]) +1 other test skip
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_su@page_flip-nv12:
    - shard-rkl:          [SKIP][400] ([i915#14544] / [i915#9683]) -> [SKIP][401] ([i915#9683])
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_psr2_su@page_flip-nv12.html
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@kms_psr2_su@page_flip-nv12.html

  * igt@kms_psr@pr-cursor-plane-onoff:
    - shard-rkl:          [SKIP][402] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][403] ([i915#1072] / [i915#9732]) +10 other tests skip
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_psr@pr-cursor-plane-onoff.html
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_psr@pr-cursor-plane-onoff.html

  * igt@kms_psr@psr2-primary-mmap-gtt:
    - shard-rkl:          [SKIP][404] ([i915#1072] / [i915#9732]) -> [SKIP][405] ([i915#1072] / [i915#14544] / [i915#9732]) +5 other tests skip
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@kms_psr@psr2-primary-mmap-gtt.html
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@kms_psr@psr2-primary-mmap-gtt.html

  * igt@kms_setmode@clone-exclusive-crtc:
    - shard-rkl:          [SKIP][406] ([i915#14544] / [i915#3555]) -> [SKIP][407] ([i915#3555]) +1 other test skip
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@kms_setmode@clone-exclusive-crtc.html
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-2/igt@kms_setmode@clone-exclusive-crtc.html

  * igt@perf@mi-rpc:
    - shard-rkl:          [SKIP][408] ([i915#14544] / [i915#2434]) -> [SKIP][409] ([i915#2434])
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-6/igt@perf@mi-rpc.html
   [409]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-1/igt@perf@mi-rpc.html

  * igt@perf@per-context-mode-unprivileged:
    - shard-rkl:          [SKIP][410] ([i915#2435]) -> [SKIP][411] ([i915#14544] / [i915#2435])
   [410]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@perf@per-context-mode-unprivileged.html
   [411]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@perf@per-context-mode-unprivileged.html

  * igt@sriov_basic@bind-unbind-vf:
    - shard-rkl:          [SKIP][412] ([i915#9917]) -> [SKIP][413] ([i915#14544] / [i915#9917])
   [412]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18556/shard-rkl-8/igt@sriov_basic@bind-unbind-vf.html
   [413]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/shard-rkl-6/igt@sriov_basic@bind-unbind-vf.html

  
  [i915#10056]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10056
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10538
  [i915#10647]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10647
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#1099]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1099
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#12169]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12169
  [i915#12178]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12178
  [i915#12276]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12276
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
  [i915#12454]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12454
  [i915#12712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12712
  [i915#12755]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12755
  [i915#12761]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12761
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#13008]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13008
  [i915#13029]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13029
  [i915#13046]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13046
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#13390]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13390
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13691]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13691
  [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
  [i915#13717]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13717
  [i915#13749]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13749
  [i915#13783]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13783
  [i915#13809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13809
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14259]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14259
  [i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
  [i915#14545]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14545
  [i915#14712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14712
  [i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
  [i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
  [i915#15104]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15104
  [i915#15131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15131
  [i915#15132]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15132
  [i915#15152]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15152
  [i915#15243]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15243
  [i915#15329]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15329
  [i915#15330]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15330
  [i915#15436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15436
  [i915#15458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15458
  [i915#15459]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15459
  [i915#15460]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15460
  [i915#15582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15582
  [i915#15608]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15608
  [i915#15643]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15643
  [i915#15662]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15662
  [i915#15709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15709
  [i915#15725]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15725
  [i915#15733]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15733
  [i915#15740]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15740
  [i915#15815]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15815
  [i915#15865]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15865
  [i915#15867]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15867
  [i915#15931]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15931
  [i915#15989]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15989
  [i915#15990]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15990
  [i915#15991]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15991
  [i915#16011]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16011
  [i915#16012]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16012
  [i915#16079]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16079
  [i915#16081]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16081
  [i915#16162]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16162
  [i915#16182]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16182
  [i915#16205]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16205
  [i915#16226]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/16226
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#2434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2434
  [i915#2435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2435
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
  [i915#3539]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3539
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4077]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4077
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4270]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4270
  [i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4537]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4537
  [i915#4538]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4538
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4812
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4818]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4818
  [i915#4860]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4860
  [i915#4880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4880
  [i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
  [i915#5190]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5190
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5354]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5354
  [i915#5566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5566
  [i915#5723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5723
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
  [i915#6344]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6344
  [i915#6524]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
  [i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7862]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7862
  [i915#7984]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7984
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
  [i915#8516]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8516
  [i915#8555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8555
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
  [i915#9531]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9531
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9812]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9812
  [i915#9878]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9878
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9917]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9917
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_18556 -> Patchwork_163939v4

  CI-20190529: 20190529
  CI_DRM_18556: 1e5fbf0d628cd02dced6cfb1ebe39717f121fb4c @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8937: 8937
  Patchwork_163939v4: 1e5fbf0d628cd02dced6cfb1ebe39717f121fb4c @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_163939v4/index.html

[-- Attachment #2: Type: text/html, Size: 142191 bytes --]

Re: [PATCH v4 07/13] drm/i915/display: Add DC3CO eligibility computation

[Jani Nikula]

On Wed, 27 May 2026, Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> wrote:
> Compute DC3CO eligibility during atomic_check based on
> pipe/port constraints and runtime triggers and store
> result in display->power.dc3co.

Atomic check should not change persistent state. It's almost always a
mistake. (I guess sometimes can't be avoided.)

> When DC3CO is allowed, request DC_STATE_EN_UPTO_DC3CO and
> reduce the DC entry delay. Otherwise, retain the existing
> delay and set default DC_STATE_EN_UPTO_DC6.
>
> Changes in v2:
> - Move dc3co state from intel_atomic_state to display->power (Uma Shankar)
> - Use #define bitmasks instead of enum for DC3CO triggers (Jani Nikula)
>
> Changes in v3:
> - Fix trigger always returning zero in intel_dc3co_compute_state().
>
> Changes in v4:
> - Call intel_display_power_set_target_dc_state() only when DC3CO is
>   supported.
> - For Panel replay DC3CO trigger, add check for as_sdp_supported flag
> - Add 1:1 mapping check to intel_dc3co_port_pipe_compatible for
>   display version 35.(Uma Shankar,Animesh Manna)
> - Add guard for intel_dc3co_compute_state()
>
> BSpec: 75253
> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 102 +++++++++++++++++-
>  .../gpu/drm/i915/display/intel_display_core.h |   3 +-
>  .../drm/i915/display/intel_display_power.c    |  30 ++++++
>  .../drm/i915/display/intel_display_power.h    |  22 ++++
>  4 files changed, 151 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 757a78c75bbf..375ffb329022 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5874,6 +5874,74 @@ static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
>  	return false;
>  }
>  
> +static bool intel_dc3co_port_pipe_compatible(struct intel_dp *intel_dp,
> +					     const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> +	enum port port = dig_port->base.port;
> +	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
> +
> +	/* Need to follow 1:1 mapping because of CMTG restriction*/
> +	if (DISPLAY_VER(to_intel_display(crtc_state)) == 35)
> +		return num_pipes == 1 &&
> +		       ((pipe == PIPE_A && port == PORT_A) ||
> +			(pipe == PIPE_B && port == PORT_B));
> +	else
> +		return num_pipes == 1 && pipe <= PIPE_B && port <= PORT_B;
> +}
> +
> +static void intel_dc3co_compute_state(struct intel_atomic_state *state)
> +{
> +	struct intel_display *display = to_intel_display(state);
> +	struct intel_crtc *crtc;
> +	struct intel_crtc_state *crtc_state;
> +	struct intel_encoder *encoder;
> +	struct intel_dp *intel_dp;
> +	u8 active_pipes = 0;
> +	enum pipe pipe;
> +	u32 trigger = DC3CO_TRIGGER_NONE;
> +
> +	if (!HAS_DC3CO(display))
> +		return;
> +
> +	for_each_intel_crtc(display->drm, crtc)
> +		active_pipes |= crtc->active ? BIT(crtc->pipe) : 0;
> +
> +	active_pipes = intel_calc_active_pipes(state, active_pipes);
> +
> +	if (hweight8(active_pipes) != 1)
> +		goto done;
> +
> +	pipe = ffs(active_pipes) - 1;
> +	crtc = intel_crtc_for_pipe(display, pipe);
> +
> +	crtc_state = to_intel_crtc_state(crtc->base.state);
> +
> +	for_each_intel_encoder_mask(display->drm, encoder,
> +				    crtc_state->uapi.encoder_mask) {
> +		if (encoder->type != INTEL_OUTPUT_EDP)
> +			goto done;
> +
> +		intel_dp = enc_to_intel_dp(encoder);
> +
> +		if (!intel_dc3co_port_pipe_compatible(intel_dp, crtc_state))
> +			goto done;
> +	}
> +
> +	if (crtc_state->has_lobf)
> +		trigger |= DC3CO_TRIGGER_LOBF;
> +	if (crtc_state->has_panel_replay && intel_dp->as_sdp_supported)
> +		trigger |= DC3CO_TRIGGER_PANEL_REPLAY;
> +	if (crtc_state->has_sel_update)
> +		trigger |= DC3CO_TRIGGER_PSR2;
> +
> +done:
> +	intel_display_power_dc3co_update(display, !!trigger, trigger);

Are two parameters necessary?

> +	drm_dbg_kms(display->drm, "DC3CO allowed=%d trigger=0x%x\n",
> +		    !!trigger, trigger);
> +}

None of the above stuff belongs in intel_display.c. The file's too big
as it is. Probably intel_display_power.c.

> +
>  static int intel_atomic_check_joiner(struct intel_atomic_state *state,
>  				     struct intel_crtc *primary_crtc)
>  {
> @@ -6570,6 +6638,9 @@ int intel_atomic_check(struct drm_device *dev,
>  				      "modeset" : "fastset");
>  	}
>  
> +	if (intel_display_power_dc3co_supported(display))
> +		intel_dc3co_compute_state(state);
> +

Smells like intel_display_power_atomic_check(), maybe, without the if
statement here.

>  	return 0;
>  
>   fail:
> @@ -7421,6 +7492,12 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
>  	struct ref_tracker *wakeref = NULL;
>  	int i;
> +	u32 target_dc_state;
> +	/*
> +	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
> +	 * toggling overhead at and above 60 FPS.
> +	 */
> +	int power_async_delay = 17;
>  
>  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
>  		intel_atomic_dsb_prepare(state, crtc);
> @@ -7627,11 +7704,26 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  		 */
>  		intel_uncore_arm_unclaimed_mmio_detection(uncore);
>  	}
> -	/*
> -	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
> -	 * toggling overhead at and above 60 FPS.
> -	 */
> -	intel_display_power_put_async_delay(display, POWER_DOMAIN_DC_OFF, wakeref, 17);
> +
> +	if (intel_display_power_dc3co_supported(display)) {
> +		if (intel_display_power_dc3co_allowed(display)) {
> +			/*
> +			 * Use minimal re-enable delay to allow DC3CO entry on
> +			 * the next idle frame, unlike the 17ms guard needed to
> +			 * prevent DC5/DC6 toggling overhead at 60+ FPS.
> +			 */
> +			power_async_delay = 1;
> +			target_dc_state = DC_STATE_EN_UPTO_DC3CO;
> +		} else {
> +			target_dc_state = DC_STATE_EN_UPTO_DC6;
> +		}
> +
> +		intel_display_power_set_target_dc_state(display, target_dc_state);
> +	}
> +

This is also way too detailed for intel_atomic_commit_tail(). This is
the highest level of modeset functions. See the code around here,
there's nothing as detailed.

> +	intel_display_power_put_async_delay(display,
> +					    POWER_DOMAIN_DC_OFF, wakeref, power_async_delay);

Maybe need to consider intel_display_power_put_commit_tail() or
something along those lines to hide all of the delay stuff there.


> +
>  	intel_display_rpm_put(display, state->wakeref);
>  
>  	/*
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 3dc5ac75a98b..e24accf473d7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -537,7 +537,8 @@ struct intel_display {
>  
>  	struct {
>  		struct i915_power_domains domains;
> -
> +		/* DC3CO eligibility state */
> +		struct intel_dc3co_state dc3co;
>  		/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
>  		u32 chv_phy_control;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 4b91747b38f1..b0f40e4233c8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -366,6 +366,35 @@ bool intel_display_power_dc3co_supported(struct intel_display *display)
>  	return (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) == DC_STATE_EN_UPTO_DC3CO;
>  }
>  
> +void intel_display_power_dc3co_update(struct intel_display *display,
> +				      bool allowed, u32 trigger)
> +{
> +	struct intel_dc3co_state *dc3co = &display->power.dc3co;
> +
> +	if (!HAS_DC3CO(display))
> +		return;
> +
> +	mutex_lock(&dc3co->lock);
> +	dc3co->allowed = allowed;

Can this always be derived from dc3co->trigger?

> +	dc3co->trigger = trigger;
> +	mutex_unlock(&dc3co->lock);
> +}
> +
> +bool intel_display_power_dc3co_allowed(struct intel_display *display)
> +{
> +	struct intel_dc3co_state *dc3co = &display->power.dc3co;
> +	bool allowed;
> +
> +	if (!HAS_DC3CO(display))
> +		return false;
> +
> +	mutex_lock(&dc3co->lock);
> +	allowed = dc3co->allowed;
> +	mutex_unlock(&dc3co->lock);
> +
> +	return allowed;
> +}
> +
>  static void __async_put_domains_mask(struct i915_power_domains *power_domains,
>  				     struct intel_power_domain_mask *mask)
>  {
> @@ -1045,6 +1074,7 @@ int intel_power_domains_init(struct intel_display *display)
>  		sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
>  
>  	mutex_init(&power_domains->lock);
> +	mutex_init(&display->power.dc3co.lock);
>  
>  	INIT_DELAYED_WORK(&power_domains->async_put_work,
>  			  intel_display_power_put_async_work);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 05880e9da89f..0b1a06f88ae5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -131,6 +131,25 @@ struct intel_power_domain_mask {
>  	DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);
>  };
>  
> +/*
> + * DC3CO enabling triggers (bitmask).
> + * DC3CO may be enabled when at least one of these triggers is active.
> + * Additional constraints may still apply.
> + */
> +#define DC3CO_TRIGGER_NONE		(0)
> +#define DC3CO_TRIGGER_PSR2		BIT(0)
> +#define DC3CO_TRIGGER_LOBF		BIT(1)
> +#define DC3CO_TRIGGER_PANEL_REPLAY	BIT(2)
> +#define DC3CO_TRIGGER_ALL		(DC3CO_TRIGGER_PSR2 | \
> +					 DC3CO_TRIGGER_LOBF | \
> +					 DC3CO_TRIGGER_PANEL_REPLAY)
> +
> +struct intel_dc3co_state {
> +	struct mutex lock; /* Protects allowed and trigger fields */
> +	bool allowed; /* DC3CO eligibility result */
> +	u32 trigger; /* Bitmask of active DC3CO triggers */
> +};
> +
>  struct i915_power_domains {
>  	/*
>  	 * Power wells needed for initialization at driver init and suspend
> @@ -187,6 +206,9 @@ void intel_display_power_set_target_dc_state(struct intel_display *display,
>  					     u32 state);
>  u32 intel_display_power_get_current_dc_state(struct intel_display *display);
>  bool intel_display_power_dc3co_supported(struct intel_display *display);
> +void intel_display_power_dc3co_update(struct intel_display *display,
> +				      bool allowed, u32 trigger);
> +bool intel_display_power_dc3co_allowed(struct intel_display *display);
>  
>  bool intel_display_power_is_enabled(struct intel_display *display,
>  				    enum intel_display_power_domain domain);

-- 
Jani Nikula, Intel

Re: [PATCH v4 05/13] drm/i915/display: Add DC3CO support check

[Jani Nikula]

On Wed, 27 May 2026, Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> wrote:
> Add intel_display_power_dc3co_supported() helper to query DC3CO
> support from allowed_dc_mask.
>
> Changes in v2:
> - Squash "Add helper to check DC3CO support" patch into this patch
>
> Changes in v4:
> - Remove introduced dc state validation,as it may break
>   fall back mechanism (sashiko)
>
> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
>  drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
>  2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index c70971ffd9f0..4b91747b38f1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -302,6 +302,7 @@ void intel_display_power_set_target_dc_state(struct intel_display *display,
>  	struct i915_power_domains *power_domains = &display->power.domains;
>  
>  	mutex_lock(&power_domains->lock);
> +

Superfluous.

>  	power_well = lookup_power_well(display, SKL_DISP_DC_OFF);
>  
>  	if (drm_WARN_ON(display->drm, !power_well))
> @@ -358,6 +359,13 @@ u32 intel_display_power_get_current_dc_state(struct intel_display *display)
>  	return current_dc_state;
>  }
>  
> +bool intel_display_power_dc3co_supported(struct intel_display *display)

This should probably be static. See my other replies in the thread.

> +{
> +	struct i915_power_domains *power_domains = &display->power.domains;
> +
> +	return (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) == DC_STATE_EN_UPTO_DC3CO;
> +}
> +
>  static void __async_put_domains_mask(struct i915_power_domains *power_domains,
>  				     struct intel_power_domain_mask *mask)
>  {
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index d616d5d09cbe..05880e9da89f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -186,6 +186,7 @@ void intel_display_power_resume(struct intel_display *display);
>  void intel_display_power_set_target_dc_state(struct intel_display *display,
>  					     u32 state);
>  u32 intel_display_power_get_current_dc_state(struct intel_display *display);
> +bool intel_display_power_dc3co_supported(struct intel_display *display);
>  
>  bool intel_display_power_is_enabled(struct intel_display *display,
>  				    enum intel_display_power_domain domain);

-- 
Jani Nikula, Intel

Re: [PATCH v4 07/13] drm/i915/display: Add DC3CO eligibility computation

[Jani Nikula]

On Wed, 27 May 2026, Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> wrote:
> Compute DC3CO eligibility during atomic_check based on
> pipe/port constraints and runtime triggers and store
> result in display->power.dc3co.
>
> When DC3CO is allowed, request DC_STATE_EN_UPTO_DC3CO and
> reduce the DC entry delay. Otherwise, retain the existing
> delay and set default DC_STATE_EN_UPTO_DC6.
>
> Changes in v2:
> - Move dc3co state from intel_atomic_state to display->power (Uma Shankar)
> - Use #define bitmasks instead of enum for DC3CO triggers (Jani Nikula)
>
> Changes in v3:
> - Fix trigger always returning zero in intel_dc3co_compute_state().
>
> Changes in v4:
> - Call intel_display_power_set_target_dc_state() only when DC3CO is
>   supported.
> - For Panel replay DC3CO trigger, add check for as_sdp_supported flag
> - Add 1:1 mapping check to intel_dc3co_port_pipe_compatible for
>   display version 35.(Uma Shankar,Animesh Manna)
> - Add guard for intel_dc3co_compute_state()
>
> BSpec: 75253
> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  | 102 +++++++++++++++++-
>  .../gpu/drm/i915/display/intel_display_core.h |   3 +-
>  .../drm/i915/display/intel_display_power.c    |  30 ++++++
>  .../drm/i915/display/intel_display_power.h    |  22 ++++
>  4 files changed, 151 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 757a78c75bbf..375ffb329022 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5874,6 +5874,74 @@ static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
>  	return false;
>  }
>  
> +static bool intel_dc3co_port_pipe_compatible(struct intel_dp *intel_dp,
> +					     const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
> +	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
> +	enum port port = dig_port->base.port;
> +	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
> +
> +	/* Need to follow 1:1 mapping because of CMTG restriction*/
> +	if (DISPLAY_VER(to_intel_display(crtc_state)) == 35)
> +		return num_pipes == 1 &&
> +		       ((pipe == PIPE_A && port == PORT_A) ||
> +			(pipe == PIPE_B && port == PORT_B));
> +	else
> +		return num_pipes == 1 && pipe <= PIPE_B && port <= PORT_B;
> +}
> +
> +static void intel_dc3co_compute_state(struct intel_atomic_state *state)
> +{
> +	struct intel_display *display = to_intel_display(state);
> +	struct intel_crtc *crtc;
> +	struct intel_crtc_state *crtc_state;
> +	struct intel_encoder *encoder;
> +	struct intel_dp *intel_dp;
> +	u8 active_pipes = 0;
> +	enum pipe pipe;
> +	u32 trigger = DC3CO_TRIGGER_NONE;
> +
> +	if (!HAS_DC3CO(display))
> +		return;
> +
> +	for_each_intel_crtc(display->drm, crtc)
> +		active_pipes |= crtc->active ? BIT(crtc->pipe) : 0;
> +
> +	active_pipes = intel_calc_active_pipes(state, active_pipes);
> +
> +	if (hweight8(active_pipes) != 1)
> +		goto done;
> +
> +	pipe = ffs(active_pipes) - 1;
> +	crtc = intel_crtc_for_pipe(display, pipe);
> +
> +	crtc_state = to_intel_crtc_state(crtc->base.state);
> +
> +	for_each_intel_encoder_mask(display->drm, encoder,
> +				    crtc_state->uapi.encoder_mask) {
> +		if (encoder->type != INTEL_OUTPUT_EDP)
> +			goto done;
> +
> +		intel_dp = enc_to_intel_dp(encoder);
> +
> +		if (!intel_dc3co_port_pipe_compatible(intel_dp, crtc_state))
> +			goto done;
> +	}
> +
> +	if (crtc_state->has_lobf)
> +		trigger |= DC3CO_TRIGGER_LOBF;
> +	if (crtc_state->has_panel_replay && intel_dp->as_sdp_supported)
> +		trigger |= DC3CO_TRIGGER_PANEL_REPLAY;
> +	if (crtc_state->has_sel_update)
> +		trigger |= DC3CO_TRIGGER_PSR2;
> +
> +done:
> +	intel_display_power_dc3co_update(display, !!trigger, trigger);
> +	drm_dbg_kms(display->drm, "DC3CO allowed=%d trigger=0x%x\n",
> +		    !!trigger, trigger);
> +}
> +
>  static int intel_atomic_check_joiner(struct intel_atomic_state *state,
>  				     struct intel_crtc *primary_crtc)
>  {
> @@ -6570,6 +6638,9 @@ int intel_atomic_check(struct drm_device *dev,
>  				      "modeset" : "fastset");
>  	}
>  
> +	if (intel_display_power_dc3co_supported(display))
> +		intel_dc3co_compute_state(state);
> +
>  	return 0;
>  
>   fail:
> @@ -7421,6 +7492,12 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
>  	struct ref_tracker *wakeref = NULL;
>  	int i;
> +	u32 target_dc_state;
> +	/*
> +	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
> +	 * toggling overhead at and above 60 FPS.
> +	 */
> +	int power_async_delay = 17;
>  
>  	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
>  		intel_atomic_dsb_prepare(state, crtc);
> @@ -7627,11 +7704,26 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  		 */
>  		intel_uncore_arm_unclaimed_mmio_detection(uncore);
>  	}
> -	/*
> -	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
> -	 * toggling overhead at and above 60 FPS.
> -	 */
> -	intel_display_power_put_async_delay(display, POWER_DOMAIN_DC_OFF, wakeref, 17);
> +
> +	if (intel_display_power_dc3co_supported(display)) {
> +		if (intel_display_power_dc3co_allowed(display)) {
> +			/*
> +			 * Use minimal re-enable delay to allow DC3CO entry on
> +			 * the next idle frame, unlike the 17ms guard needed to
> +			 * prevent DC5/DC6 toggling overhead at 60+ FPS.
> +			 */
> +			power_async_delay = 1;
> +			target_dc_state = DC_STATE_EN_UPTO_DC3CO;
> +		} else {
> +			target_dc_state = DC_STATE_EN_UPTO_DC6;
> +		}
> +
> +		intel_display_power_set_target_dc_state(display, target_dc_state);
> +	}
> +
> +	intel_display_power_put_async_delay(display,
> +					    POWER_DOMAIN_DC_OFF, wakeref, power_async_delay);
> +
>  	intel_display_rpm_put(display, state->wakeref);
>  
>  	/*
> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
> index 3dc5ac75a98b..e24accf473d7 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
> @@ -537,7 +537,8 @@ struct intel_display {
>  
>  	struct {
>  		struct i915_power_domains domains;
> -
> +		/* DC3CO eligibility state */
> +		struct intel_dc3co_state dc3co;
>  		/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
>  		u32 chv_phy_control;
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 4b91747b38f1..b0f40e4233c8 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -366,6 +366,35 @@ bool intel_display_power_dc3co_supported(struct intel_display *display)
>  	return (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) == DC_STATE_EN_UPTO_DC3CO;
>  }
>  
> +void intel_display_power_dc3co_update(struct intel_display *display,
> +				      bool allowed, u32 trigger)
> +{
> +	struct intel_dc3co_state *dc3co = &display->power.dc3co;
> +
> +	if (!HAS_DC3CO(display))
> +		return;
> +
> +	mutex_lock(&dc3co->lock);
> +	dc3co->allowed = allowed;
> +	dc3co->trigger = trigger;
> +	mutex_unlock(&dc3co->lock);
> +}
> +
> +bool intel_display_power_dc3co_allowed(struct intel_display *display)
> +{
> +	struct intel_dc3co_state *dc3co = &display->power.dc3co;
> +	bool allowed;
> +
> +	if (!HAS_DC3CO(display))
> +		return false;
> +
> +	mutex_lock(&dc3co->lock);
> +	allowed = dc3co->allowed;
> +	mutex_unlock(&dc3co->lock);
> +
> +	return allowed;
> +}

There are a number of places that check for allowed() &&
supported(). This shouldn't have to be the case. allowed() should never
return true if !supported().

> +
>  static void __async_put_domains_mask(struct i915_power_domains *power_domains,
>  				     struct intel_power_domain_mask *mask)
>  {
> @@ -1045,6 +1074,7 @@ int intel_power_domains_init(struct intel_display *display)
>  		sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
>  
>  	mutex_init(&power_domains->lock);
> +	mutex_init(&display->power.dc3co.lock);
>  
>  	INIT_DELAYED_WORK(&power_domains->async_put_work,
>  			  intel_display_power_put_async_work);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
> index 05880e9da89f..0b1a06f88ae5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -131,6 +131,25 @@ struct intel_power_domain_mask {
>  	DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);
>  };
>  
> +/*
> + * DC3CO enabling triggers (bitmask).
> + * DC3CO may be enabled when at least one of these triggers is active.
> + * Additional constraints may still apply.
> + */
> +#define DC3CO_TRIGGER_NONE		(0)
> +#define DC3CO_TRIGGER_PSR2		BIT(0)
> +#define DC3CO_TRIGGER_LOBF		BIT(1)
> +#define DC3CO_TRIGGER_PANEL_REPLAY	BIT(2)
> +#define DC3CO_TRIGGER_ALL		(DC3CO_TRIGGER_PSR2 | \
> +					 DC3CO_TRIGGER_LOBF | \
> +					 DC3CO_TRIGGER_PANEL_REPLAY)
> +
> +struct intel_dc3co_state {
> +	struct mutex lock; /* Protects allowed and trigger fields */
> +	bool allowed; /* DC3CO eligibility result */
> +	u32 trigger; /* Bitmask of active DC3CO triggers */
> +};
> +
>  struct i915_power_domains {
>  	/*
>  	 * Power wells needed for initialization at driver init and suspend
> @@ -187,6 +206,9 @@ void intel_display_power_set_target_dc_state(struct intel_display *display,
>  					     u32 state);
>  u32 intel_display_power_get_current_dc_state(struct intel_display *display);
>  bool intel_display_power_dc3co_supported(struct intel_display *display);
> +void intel_display_power_dc3co_update(struct intel_display *display,
> +				      bool allowed, u32 trigger);
> +bool intel_display_power_dc3co_allowed(struct intel_display *display);
>  
>  bool intel_display_power_is_enabled(struct intel_display *display,
>  				    enum intel_display_power_domain domain);

-- 
Jani Nikula, Intel

Re: [PATCH v4 08/13] drm/i915/display: Store DC3CO eligibility in PSR state

[Jani Nikula]

On Wed, 27 May 2026, Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> wrote:
> Store DC3CO eligibility in intel_dp->psr during
> intel_psr_post_plane_update() so PSR configuration
> can take DC3CO into account.
>
> This will be used to control PSR2 parameters such as idle frames.
>
> Changes in v2:
> - Use intel_display_power_dc3co_allowed(display) instead
>   of intel_dc3co_allowed(state)
>
> Changes in v4:
> - Update psr.dc3co_eligible before
>   intel_psr_enable_locked() call (sashiko)
>
> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_types.h | 2 ++
>  drivers/gpu/drm/i915/display/intel_psr.c           | 7 +++++++
>  2 files changed, 9 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 1cfc585530dc..c21f5d1e2003 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1770,6 +1770,8 @@ struct intel_psr {
>  	ktime_t last_exit;
>  	bool sink_not_reliable;
>  	bool irq_aux_error;
> +	/* DC3CO eligibility used to control PSR configuration */
> +	bool dc3co_eligible;
>  	u16 su_w_granularity;
>  	u16 su_y_granularity;
>  	bool source_panel_replay_support;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 730ca7af7873..d4b294beecef 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2300,6 +2300,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>  	intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
>  	intel_dp->psr.active_non_psr_pipes = 0;
>  	intel_dp->psr.pkg_c_latency_used = 0;
> +	intel_dp->psr.dc3co_eligible = false;
>  }
>  
>  /**
> @@ -3090,10 +3091,14 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
>  	const struct intel_crtc_state *crtc_state =
>  		intel_atomic_get_new_crtc_state(state, crtc);
>  	struct intel_encoder *encoder;
> +	bool dc3co_eligible;
>  
>  	if (!crtc_state->has_psr)
>  		return;
>  
> +	dc3co_eligible = intel_display_power_dc3co_allowed(display) &&
> +			      intel_display_power_dc3co_supported(display);

Maybe just "allowed"? Eligible sounds fancy, and makes you wonder what's
the difference with allowed.

And allowed() should never return true if !supported(), i.e. allowed()
&& supported() shouldn't have to be required here.

BR,
Jani.


> +
>  	verify_panel_replay_dsc_state(crtc_state);
>  
>  	for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
> @@ -3121,6 +3126,8 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
>  			keep_disabled = true;
>  		}
>  
> +		intel_dp->psr.dc3co_eligible = dc3co_eligible;
> +
>  		if (!psr->enabled && !keep_disabled)
>  			intel_psr_enable_locked(intel_dp, crtc_state);
>  		else if (psr->enabled && !crtc_state->wm_level_disabled)

-- 
Jani Nikula, Intel

Re: [PATCH v4 05/13] drm/i915/display: Add DC3CO support check

[Dibin Moolakadan Subrahmanian]

On 27-05-2026 17:56, Jani Nikula wrote:
> On Wed, 27 May 2026, Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> wrote:
>> Add intel_display_power_dc3co_supported() helper to query DC3CO
>> support from allowed_dc_mask.
>>
>> Changes in v2:
>> - Squash "Add helper to check DC3CO support" patch into this patch
>>
>> Changes in v4:
>> - Remove introduced dc state validation,as it may break
>>    fall back mechanism (sashiko)
>>
>> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display_power.c | 8 ++++++++
>>   drivers/gpu/drm/i915/display/intel_display_power.h | 1 +
>>   2 files changed, 9 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index c70971ffd9f0..4b91747b38f1 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -302,6 +302,7 @@ void intel_display_power_set_target_dc_state(struct intel_display *display,
>>   	struct i915_power_domains *power_domains = &display->power.domains;
>>   
>>   	mutex_lock(&power_domains->lock);
>> +
> Superfluous.

Thanks for the review.
My bad, will fix it in next revision.

>
>>   	power_well = lookup_power_well(display, SKL_DISP_DC_OFF);
>>   
>>   	if (drm_WARN_ON(display->drm, !power_well))
>> @@ -358,6 +359,13 @@ u32 intel_display_power_get_current_dc_state(struct intel_display *display)
>>   	return current_dc_state;
>>   }
>>   
>> +bool intel_display_power_dc3co_supported(struct intel_display *display)
> This should probably be static. See my other replies in the thread.

Will check the other replies.

>
>> +{
>> +	struct i915_power_domains *power_domains = &display->power.domains;
>> +
>> +	return (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) == DC_STATE_EN_UPTO_DC3CO;
>> +}
>> +
>>   static void __async_put_domains_mask(struct i915_power_domains *power_domains,
>>   				     struct intel_power_domain_mask *mask)
>>   {
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
>> index d616d5d09cbe..05880e9da89f 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
>> @@ -186,6 +186,7 @@ void intel_display_power_resume(struct intel_display *display);
>>   void intel_display_power_set_target_dc_state(struct intel_display *display,
>>   					     u32 state);
>>   u32 intel_display_power_get_current_dc_state(struct intel_display *display);
>> +bool intel_display_power_dc3co_supported(struct intel_display *display);
>>   
>>   bool intel_display_power_is_enabled(struct intel_display *display,
>>   				    enum intel_display_power_domain domain);

Re: [PATCH v4 07/13] drm/i915/display: Add DC3CO eligibility computation

[Dibin Moolakadan Subrahmanian]

On 27-05-2026 17:58, Jani Nikula wrote:
> On Wed, 27 May 2026, Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> wrote:
>> Compute DC3CO eligibility during atomic_check based on
>> pipe/port constraints and runtime triggers and store
>> result in display->power.dc3co.
>>
>> When DC3CO is allowed, request DC_STATE_EN_UPTO_DC3CO and
>> reduce the DC entry delay. Otherwise, retain the existing
>> delay and set default DC_STATE_EN_UPTO_DC6.
>>
>> Changes in v2:
>> - Move dc3co state from intel_atomic_state to display->power (Uma Shankar)
>> - Use #define bitmasks instead of enum for DC3CO triggers (Jani Nikula)
>>
>> Changes in v3:
>> - Fix trigger always returning zero in intel_dc3co_compute_state().
>>
>> Changes in v4:
>> - Call intel_display_power_set_target_dc_state() only when DC3CO is
>>    supported.
>> - For Panel replay DC3CO trigger, add check for as_sdp_supported flag
>> - Add 1:1 mapping check to intel_dc3co_port_pipe_compatible for
>>    display version 35.(Uma Shankar,Animesh Manna)
>> - Add guard for intel_dc3co_compute_state()
>>
>> BSpec: 75253
>> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c  | 102 +++++++++++++++++-
>>   .../gpu/drm/i915/display/intel_display_core.h |   3 +-
>>   .../drm/i915/display/intel_display_power.c    |  30 ++++++
>>   .../drm/i915/display/intel_display_power.h    |  22 ++++
>>   4 files changed, 151 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 757a78c75bbf..375ffb329022 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -5874,6 +5874,74 @@ static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
>>   	return false;
>>   }
>>   
>> +static bool intel_dc3co_port_pipe_compatible(struct intel_dp *intel_dp,
>> +					     const struct intel_crtc_state *crtc_state)
>> +{
>> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> +	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
>> +	enum port port = dig_port->base.port;
>> +	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
>> +
>> +	/* Need to follow 1:1 mapping because of CMTG restriction*/
>> +	if (DISPLAY_VER(to_intel_display(crtc_state)) == 35)
>> +		return num_pipes == 1 &&
>> +		       ((pipe == PIPE_A && port == PORT_A) ||
>> +			(pipe == PIPE_B && port == PORT_B));
>> +	else
>> +		return num_pipes == 1 && pipe <= PIPE_B && port <= PORT_B;
>> +}
>> +
>> +static void intel_dc3co_compute_state(struct intel_atomic_state *state)
>> +{
>> +	struct intel_display *display = to_intel_display(state);
>> +	struct intel_crtc *crtc;
>> +	struct intel_crtc_state *crtc_state;
>> +	struct intel_encoder *encoder;
>> +	struct intel_dp *intel_dp;
>> +	u8 active_pipes = 0;
>> +	enum pipe pipe;
>> +	u32 trigger = DC3CO_TRIGGER_NONE;
>> +
>> +	if (!HAS_DC3CO(display))
>> +		return;
>> +
>> +	for_each_intel_crtc(display->drm, crtc)
>> +		active_pipes |= crtc->active ? BIT(crtc->pipe) : 0;
>> +
>> +	active_pipes = intel_calc_active_pipes(state, active_pipes);
>> +
>> +	if (hweight8(active_pipes) != 1)
>> +		goto done;
>> +
>> +	pipe = ffs(active_pipes) - 1;
>> +	crtc = intel_crtc_for_pipe(display, pipe);
>> +
>> +	crtc_state = to_intel_crtc_state(crtc->base.state);
>> +
>> +	for_each_intel_encoder_mask(display->drm, encoder,
>> +				    crtc_state->uapi.encoder_mask) {
>> +		if (encoder->type != INTEL_OUTPUT_EDP)
>> +			goto done;
>> +
>> +		intel_dp = enc_to_intel_dp(encoder);
>> +
>> +		if (!intel_dc3co_port_pipe_compatible(intel_dp, crtc_state))
>> +			goto done;
>> +	}
>> +
>> +	if (crtc_state->has_lobf)
>> +		trigger |= DC3CO_TRIGGER_LOBF;
>> +	if (crtc_state->has_panel_replay && intel_dp->as_sdp_supported)
>> +		trigger |= DC3CO_TRIGGER_PANEL_REPLAY;
>> +	if (crtc_state->has_sel_update)
>> +		trigger |= DC3CO_TRIGGER_PSR2;
>> +
>> +done:
>> +	intel_display_power_dc3co_update(display, !!trigger, trigger);
>> +	drm_dbg_kms(display->drm, "DC3CO allowed=%d trigger=0x%x\n",
>> +		    !!trigger, trigger);
>> +}
>> +
>>   static int intel_atomic_check_joiner(struct intel_atomic_state *state,
>>   				     struct intel_crtc *primary_crtc)
>>   {
>> @@ -6570,6 +6638,9 @@ int intel_atomic_check(struct drm_device *dev,
>>   				      "modeset" : "fastset");
>>   	}
>>   
>> +	if (intel_display_power_dc3co_supported(display))
>> +		intel_dc3co_compute_state(state);
>> +
>>   	return 0;
>>   
>>    fail:
>> @@ -7421,6 +7492,12 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>   	struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
>>   	struct ref_tracker *wakeref = NULL;
>>   	int i;
>> +	u32 target_dc_state;
>> +	/*
>> +	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
>> +	 * toggling overhead at and above 60 FPS.
>> +	 */
>> +	int power_async_delay = 17;
>>   
>>   	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
>>   		intel_atomic_dsb_prepare(state, crtc);
>> @@ -7627,11 +7704,26 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>   		 */
>>   		intel_uncore_arm_unclaimed_mmio_detection(uncore);
>>   	}
>> -	/*
>> -	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
>> -	 * toggling overhead at and above 60 FPS.
>> -	 */
>> -	intel_display_power_put_async_delay(display, POWER_DOMAIN_DC_OFF, wakeref, 17);
>> +
>> +	if (intel_display_power_dc3co_supported(display)) {
>> +		if (intel_display_power_dc3co_allowed(display)) {
>> +			/*
>> +			 * Use minimal re-enable delay to allow DC3CO entry on
>> +			 * the next idle frame, unlike the 17ms guard needed to
>> +			 * prevent DC5/DC6 toggling overhead at 60+ FPS.
>> +			 */
>> +			power_async_delay = 1;
>> +			target_dc_state = DC_STATE_EN_UPTO_DC3CO;
>> +		} else {
>> +			target_dc_state = DC_STATE_EN_UPTO_DC6;
>> +		}
>> +
>> +		intel_display_power_set_target_dc_state(display, target_dc_state);
>> +	}
>> +
>> +	intel_display_power_put_async_delay(display,
>> +					    POWER_DOMAIN_DC_OFF, wakeref, power_async_delay);
>> +
>>   	intel_display_rpm_put(display, state->wakeref);
>>   
>>   	/*
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index 3dc5ac75a98b..e24accf473d7 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -537,7 +537,8 @@ struct intel_display {
>>   
>>   	struct {
>>   		struct i915_power_domains domains;
>> -
>> +		/* DC3CO eligibility state */
>> +		struct intel_dc3co_state dc3co;
>>   		/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
>>   		u32 chv_phy_control;
>>   
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index 4b91747b38f1..b0f40e4233c8 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -366,6 +366,35 @@ bool intel_display_power_dc3co_supported(struct intel_display *display)
>>   	return (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) == DC_STATE_EN_UPTO_DC3CO;
>>   }
>>   
>> +void intel_display_power_dc3co_update(struct intel_display *display,
>> +				      bool allowed, u32 trigger)
>> +{
>> +	struct intel_dc3co_state *dc3co = &display->power.dc3co;
>> +
>> +	if (!HAS_DC3CO(display))
>> +		return;
>> +
>> +	mutex_lock(&dc3co->lock);
>> +	dc3co->allowed = allowed;
>> +	dc3co->trigger = trigger;
>> +	mutex_unlock(&dc3co->lock);
>> +}
>> +
>> +bool intel_display_power_dc3co_allowed(struct intel_display *display)
>> +{
>> +	struct intel_dc3co_state *dc3co = &display->power.dc3co;
>> +	bool allowed;
>> +
>> +	if (!HAS_DC3CO(display))
>> +		return false;
>> +
>> +	mutex_lock(&dc3co->lock);
>> +	allowed = dc3co->allowed;
>> +	mutex_unlock(&dc3co->lock);
>> +
>> +	return allowed;
>> +}
> There are a number of places that check for allowed() &&
> supported(). This shouldn't have to be the case. allowed() should never
> return true if !supported().

Agreed. I will add the supported()
check inside intel_display_power_dc3co_allowed() and clean up the redundant checks

>
>> +
>>   static void __async_put_domains_mask(struct i915_power_domains *power_domains,
>>   				     struct intel_power_domain_mask *mask)
>>   {
>> @@ -1045,6 +1074,7 @@ int intel_power_domains_init(struct intel_display *display)
>>   		sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
>>   
>>   	mutex_init(&power_domains->lock);
>> +	mutex_init(&display->power.dc3co.lock);
>>   
>>   	INIT_DELAYED_WORK(&power_domains->async_put_work,
>>   			  intel_display_power_put_async_work);
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
>> index 05880e9da89f..0b1a06f88ae5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
>> @@ -131,6 +131,25 @@ struct intel_power_domain_mask {
>>   	DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);
>>   };
>>   
>> +/*
>> + * DC3CO enabling triggers (bitmask).
>> + * DC3CO may be enabled when at least one of these triggers is active.
>> + * Additional constraints may still apply.
>> + */
>> +#define DC3CO_TRIGGER_NONE		(0)
>> +#define DC3CO_TRIGGER_PSR2		BIT(0)
>> +#define DC3CO_TRIGGER_LOBF		BIT(1)
>> +#define DC3CO_TRIGGER_PANEL_REPLAY	BIT(2)
>> +#define DC3CO_TRIGGER_ALL		(DC3CO_TRIGGER_PSR2 | \
>> +					 DC3CO_TRIGGER_LOBF | \
>> +					 DC3CO_TRIGGER_PANEL_REPLAY)
>> +
>> +struct intel_dc3co_state {
>> +	struct mutex lock; /* Protects allowed and trigger fields */
>> +	bool allowed; /* DC3CO eligibility result */
>> +	u32 trigger; /* Bitmask of active DC3CO triggers */
>> +};
>> +
>>   struct i915_power_domains {
>>   	/*
>>   	 * Power wells needed for initialization at driver init and suspend
>> @@ -187,6 +206,9 @@ void intel_display_power_set_target_dc_state(struct intel_display *display,
>>   					     u32 state);
>>   u32 intel_display_power_get_current_dc_state(struct intel_display *display);
>>   bool intel_display_power_dc3co_supported(struct intel_display *display);
>> +void intel_display_power_dc3co_update(struct intel_display *display,
>> +				      bool allowed, u32 trigger);
>> +bool intel_display_power_dc3co_allowed(struct intel_display *display);
>>   
>>   bool intel_display_power_is_enabled(struct intel_display *display,
>>   				    enum intel_display_power_domain domain);

Re: [PATCH v4 07/13] drm/i915/display: Add DC3CO eligibility computation

[Dibin Moolakadan Subrahmanian]

On 27-05-2026 17:54, Jani Nikula wrote:
> On Wed, 27 May 2026, Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> wrote:
>> Compute DC3CO eligibility during atomic_check based on
>> pipe/port constraints and runtime triggers and store
>> result in display->power.dc3co.
> Atomic check should not change persistent state. It's almost always a
> mistake. (I guess sometimes can't be avoided.)

Agreed. atomic_check should avoid modifying persistent state.
Any thoughts on moving function call to intel_atomic_commit_tail()?

>> When DC3CO is allowed, request DC_STATE_EN_UPTO_DC3CO and
>> reduce the DC entry delay. Otherwise, retain the existing
>> delay and set default DC_STATE_EN_UPTO_DC6.
>>
>> Changes in v2:
>> - Move dc3co state from intel_atomic_state to display->power (Uma Shankar)
>> - Use #define bitmasks instead of enum for DC3CO triggers (Jani Nikula)
>>
>> Changes in v3:
>> - Fix trigger always returning zero in intel_dc3co_compute_state().
>>
>> Changes in v4:
>> - Call intel_display_power_set_target_dc_state() only when DC3CO is
>>    supported.
>> - For Panel replay DC3CO trigger, add check for as_sdp_supported flag
>> - Add 1:1 mapping check to intel_dc3co_port_pipe_compatible for
>>    display version 35.(Uma Shankar,Animesh Manna)
>> - Add guard for intel_dc3co_compute_state()
>>
>> BSpec: 75253
>> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display.c  | 102 +++++++++++++++++-
>>   .../gpu/drm/i915/display/intel_display_core.h |   3 +-
>>   .../drm/i915/display/intel_display_power.c    |  30 ++++++
>>   .../drm/i915/display/intel_display_power.h    |  22 ++++
>>   4 files changed, 151 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index 757a78c75bbf..375ffb329022 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -5874,6 +5874,74 @@ static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
>>   	return false;
>>   }
>>   
>> +static bool intel_dc3co_port_pipe_compatible(struct intel_dp *intel_dp,
>> +					     const struct intel_crtc_state *crtc_state)
>> +{
>> +	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
>> +	enum pipe pipe = to_intel_crtc(crtc_state->uapi.crtc)->pipe;
>> +	enum port port = dig_port->base.port;
>> +	int num_pipes = intel_crtc_num_joined_pipes(crtc_state);
>> +
>> +	/* Need to follow 1:1 mapping because of CMTG restriction*/
>> +	if (DISPLAY_VER(to_intel_display(crtc_state)) == 35)
>> +		return num_pipes == 1 &&
>> +		       ((pipe == PIPE_A && port == PORT_A) ||
>> +			(pipe == PIPE_B && port == PORT_B));
>> +	else
>> +		return num_pipes == 1 && pipe <= PIPE_B && port <= PORT_B;
>> +}
>> +
>> +static void intel_dc3co_compute_state(struct intel_atomic_state *state)
>> +{
>> +	struct intel_display *display = to_intel_display(state);
>> +	struct intel_crtc *crtc;
>> +	struct intel_crtc_state *crtc_state;
>> +	struct intel_encoder *encoder;
>> +	struct intel_dp *intel_dp;
>> +	u8 active_pipes = 0;
>> +	enum pipe pipe;
>> +	u32 trigger = DC3CO_TRIGGER_NONE;
>> +
>> +	if (!HAS_DC3CO(display))
>> +		return;
>> +
>> +	for_each_intel_crtc(display->drm, crtc)
>> +		active_pipes |= crtc->active ? BIT(crtc->pipe) : 0;
>> +
>> +	active_pipes = intel_calc_active_pipes(state, active_pipes);
>> +
>> +	if (hweight8(active_pipes) != 1)
>> +		goto done;
>> +
>> +	pipe = ffs(active_pipes) - 1;
>> +	crtc = intel_crtc_for_pipe(display, pipe);
>> +
>> +	crtc_state = to_intel_crtc_state(crtc->base.state);
>> +
>> +	for_each_intel_encoder_mask(display->drm, encoder,
>> +				    crtc_state->uapi.encoder_mask) {
>> +		if (encoder->type != INTEL_OUTPUT_EDP)
>> +			goto done;
>> +
>> +		intel_dp = enc_to_intel_dp(encoder);
>> +
>> +		if (!intel_dc3co_port_pipe_compatible(intel_dp, crtc_state))
>> +			goto done;
>> +	}
>> +
>> +	if (crtc_state->has_lobf)
>> +		trigger |= DC3CO_TRIGGER_LOBF;
>> +	if (crtc_state->has_panel_replay && intel_dp->as_sdp_supported)
>> +		trigger |= DC3CO_TRIGGER_PANEL_REPLAY;
>> +	if (crtc_state->has_sel_update)
>> +		trigger |= DC3CO_TRIGGER_PSR2;
>> +
>> +done:
>> +	intel_display_power_dc3co_update(display, !!trigger, trigger);
> Are two parameters necessary?

I kept them separate to map arguments directly to
allowed and trigger fields in struct intel_dc3co_state.
If you prefer I can move this logic to intel_display_power_dc3co_update()
and take only trigger as argument and derive allowed in intel_display_power_dc3co_update.

>
>> +	drm_dbg_kms(display->drm, "DC3CO allowed=%d trigger=0x%x\n",
>> +		    !!trigger, trigger);
>> +}
> None of the above stuff belongs in intel_display.c. The file's too big
> as it is. Probably intel_display_power.c.

I checked moving this to intel_display_power.c,
but intel_display_power.c doesn't have any existing functions that
rely on intel_atomic_state and CRTC states.
To avoid bloating intel_display.c, would it make sense to introduce a new file?
Like intel_dc3co.c to house DC3CO only, or intel_display_dynamic_power.c
to accommodate any future dynamic states.

>
>> +
>>   static int intel_atomic_check_joiner(struct intel_atomic_state *state,
>>   				     struct intel_crtc *primary_crtc)
>>   {
>> @@ -6570,6 +6638,9 @@ int intel_atomic_check(struct drm_device *dev,
>>   				      "modeset" : "fastset");
>>   	}
>>   
>> +	if (intel_display_power_dc3co_supported(display))
>> +		intel_dc3co_compute_state(state);
>> +
> Smells like intel_display_power_atomic_check(), maybe, without the if
> statement here.
>
>>   	return 0;
>>   
>>    fail:
>> @@ -7421,6 +7492,12 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>   	struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
>>   	struct ref_tracker *wakeref = NULL;
>>   	int i;
>> +	u32 target_dc_state;
>> +	/*
>> +	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
>> +	 * toggling overhead at and above 60 FPS.
>> +	 */
>> +	int power_async_delay = 17;
>>   
>>   	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
>>   		intel_atomic_dsb_prepare(state, crtc);
>> @@ -7627,11 +7704,26 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>   		 */
>>   		intel_uncore_arm_unclaimed_mmio_detection(uncore);
>>   	}
>> -	/*
>> -	 * Delay re-enabling DC states by 17 ms to avoid the off->on->off
>> -	 * toggling overhead at and above 60 FPS.
>> -	 */
>> -	intel_display_power_put_async_delay(display, POWER_DOMAIN_DC_OFF, wakeref, 17);
>> +
>> +	if (intel_display_power_dc3co_supported(display)) {
>> +		if (intel_display_power_dc3co_allowed(display)) {
>> +			/*
>> +			 * Use minimal re-enable delay to allow DC3CO entry on
>> +			 * the next idle frame, unlike the 17ms guard needed to
>> +			 * prevent DC5/DC6 toggling overhead at 60+ FPS.
>> +			 */
>> +			power_async_delay = 1;
>> +			target_dc_state = DC_STATE_EN_UPTO_DC3CO;
>> +		} else {
>> +			target_dc_state = DC_STATE_EN_UPTO_DC6;
>> +		}
>> +
>> +		intel_display_power_set_target_dc_state(display, target_dc_state);
>> +	}
>> +
> This is also way too detailed for intel_atomic_commit_tail(). This is
> the highest level of modeset functions. See the code around here,
> there's nothing as detailed.

Agreed. I will wrap this logic into a helper function
to keep intel_atomic_commit_tail() clean.

>
>> +	intel_display_power_put_async_delay(display,
>> +					    POWER_DOMAIN_DC_OFF, wakeref, power_async_delay);
> Maybe need to consider intel_display_power_put_commit_tail() or
> something along those lines to hide all of the delay stuff there.

I will add delay logic to a new helper mentioned above.

>
>> +
>>   	intel_display_rpm_put(display, state->wakeref);
>>   
>>   	/*
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_core.h b/drivers/gpu/drm/i915/display/intel_display_core.h
>> index 3dc5ac75a98b..e24accf473d7 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_core.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_core.h
>> @@ -537,7 +537,8 @@ struct intel_display {
>>   
>>   	struct {
>>   		struct i915_power_domains domains;
>> -
>> +		/* DC3CO eligibility state */
>> +		struct intel_dc3co_state dc3co;
>>   		/* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
>>   		u32 chv_phy_control;
>>   
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index 4b91747b38f1..b0f40e4233c8 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -366,6 +366,35 @@ bool intel_display_power_dc3co_supported(struct intel_display *display)
>>   	return (power_domains->allowed_dc_mask & DC_STATE_EN_UPTO_DC3CO) == DC_STATE_EN_UPTO_DC3CO;
>>   }
>>   
>> +void intel_display_power_dc3co_update(struct intel_display *display,
>> +				      bool allowed, u32 trigger)
>> +{
>> +	struct intel_dc3co_state *dc3co = &display->power.dc3co;
>> +
>> +	if (!HAS_DC3CO(display))
>> +		return;
>> +
>> +	mutex_lock(&dc3co->lock);
>> +	dc3co->allowed = allowed;
> Can this always be derived from dc3co->trigger?

Yes, I will update this based on the comment at the call site.

>
>> +	dc3co->trigger = trigger;
>> +	mutex_unlock(&dc3co->lock);
>> +}
>> +
>> +bool intel_display_power_dc3co_allowed(struct intel_display *display)
>> +{
>> +	struct intel_dc3co_state *dc3co = &display->power.dc3co;
>> +	bool allowed;
>> +
>> +	if (!HAS_DC3CO(display))
>> +		return false;
>> +
>> +	mutex_lock(&dc3co->lock);
>> +	allowed = dc3co->allowed;
>> +	mutex_unlock(&dc3co->lock);
>> +
>> +	return allowed;
>> +}
>> +
>>   static void __async_put_domains_mask(struct i915_power_domains *power_domains,
>>   				     struct intel_power_domain_mask *mask)
>>   {
>> @@ -1045,6 +1074,7 @@ int intel_power_domains_init(struct intel_display *display)
>>   		sanitize_target_dc_state(display, DC_STATE_EN_UPTO_DC6);
>>   
>>   	mutex_init(&power_domains->lock);
>> +	mutex_init(&display->power.dc3co.lock);
>>   
>>   	INIT_DELAYED_WORK(&power_domains->async_put_work,
>>   			  intel_display_power_put_async_work);
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
>> index 05880e9da89f..0b1a06f88ae5 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
>> @@ -131,6 +131,25 @@ struct intel_power_domain_mask {
>>   	DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);
>>   };
>>   
>> +/*
>> + * DC3CO enabling triggers (bitmask).
>> + * DC3CO may be enabled when at least one of these triggers is active.
>> + * Additional constraints may still apply.
>> + */
>> +#define DC3CO_TRIGGER_NONE		(0)
>> +#define DC3CO_TRIGGER_PSR2		BIT(0)
>> +#define DC3CO_TRIGGER_LOBF		BIT(1)
>> +#define DC3CO_TRIGGER_PANEL_REPLAY	BIT(2)
>> +#define DC3CO_TRIGGER_ALL		(DC3CO_TRIGGER_PSR2 | \
>> +					 DC3CO_TRIGGER_LOBF | \
>> +					 DC3CO_TRIGGER_PANEL_REPLAY)
>> +
>> +struct intel_dc3co_state {
>> +	struct mutex lock; /* Protects allowed and trigger fields */
>> +	bool allowed; /* DC3CO eligibility result */
>> +	u32 trigger; /* Bitmask of active DC3CO triggers */
>> +};
>> +
>>   struct i915_power_domains {
>>   	/*
>>   	 * Power wells needed for initialization at driver init and suspend
>> @@ -187,6 +206,9 @@ void intel_display_power_set_target_dc_state(struct intel_display *display,
>>   					     u32 state);
>>   u32 intel_display_power_get_current_dc_state(struct intel_display *display);
>>   bool intel_display_power_dc3co_supported(struct intel_display *display);
>> +void intel_display_power_dc3co_update(struct intel_display *display,
>> +				      bool allowed, u32 trigger);
>> +bool intel_display_power_dc3co_allowed(struct intel_display *display);
>>   
>>   bool intel_display_power_is_enabled(struct intel_display *display,
>>   				    enum intel_display_power_domain domain);

Re: [PATCH v4 08/13] drm/i915/display: Store DC3CO eligibility in PSR state

[Dibin Moolakadan Subrahmanian]

On 27-05-2026 18:00, Jani Nikula wrote:
> On Wed, 27 May 2026, Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com> wrote:
>> Store DC3CO eligibility in intel_dp->psr during
>> intel_psr_post_plane_update() so PSR configuration
>> can take DC3CO into account.
>>
>> This will be used to control PSR2 parameters such as idle frames.
>>
>> Changes in v2:
>> - Use intel_display_power_dc3co_allowed(display) instead
>>    of intel_dc3co_allowed(state)
>>
>> Changes in v4:
>> - Update psr.dc3co_eligible before
>>    intel_psr_enable_locked() call (sashiko)
>>
>> Signed-off-by: Dibin Moolakadan Subrahmanian <dibin.moolakadan.subrahmanian@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display_types.h | 2 ++
>>   drivers/gpu/drm/i915/display/intel_psr.c           | 7 +++++++
>>   2 files changed, 9 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 1cfc585530dc..c21f5d1e2003 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1770,6 +1770,8 @@ struct intel_psr {
>>   	ktime_t last_exit;
>>   	bool sink_not_reliable;
>>   	bool irq_aux_error;
>> +	/* DC3CO eligibility used to control PSR configuration */
>> +	bool dc3co_eligible;
>>   	u16 su_w_granularity;
>>   	u16 su_y_granularity;
>>   	bool source_panel_replay_support;
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 730ca7af7873..d4b294beecef 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -2300,6 +2300,7 @@ static void intel_psr_disable_locked(struct intel_dp *intel_dp)
>>   	intel_dp->psr.psr2_sel_fetch_cff_enabled = false;
>>   	intel_dp->psr.active_non_psr_pipes = 0;
>>   	intel_dp->psr.pkg_c_latency_used = 0;
>> +	intel_dp->psr.dc3co_eligible = false;
>>   }
>>   
>>   /**
>> @@ -3090,10 +3091,14 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
>>   	const struct intel_crtc_state *crtc_state =
>>   		intel_atomic_get_new_crtc_state(state, crtc);
>>   	struct intel_encoder *encoder;
>> +	bool dc3co_eligible;
>>   
>>   	if (!crtc_state->has_psr)
>>   		return;
>>   
>> +	dc3co_eligible = intel_display_power_dc3co_allowed(display) &&
>> +			      intel_display_power_dc3co_supported(display);
> Maybe just "allowed"? Eligible sounds fancy, and makes you wonder what's
> the difference with allowed.
>
> And allowed() should never return true if !supported(), i.e. allowed()
> && supported() shouldn't have to be required here.

Agreed, I will fix this in the next version.

>
> BR,
> Jani.
>
>
>> +
>>   	verify_panel_replay_dsc_state(crtc_state);
>>   
>>   	for_each_intel_encoder_mask_with_psr(state->base.dev, encoder,
>> @@ -3121,6 +3126,8 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state,
>>   			keep_disabled = true;
>>   		}
>>   
>> +		intel_dp->psr.dc3co_eligible = dc3co_eligible;
>> +
>>   		if (!psr->enabled && !keep_disabled)
>>   			intel_psr_enable_locked(intel_dp, crtc_state);
>>   		else if (psr->enabled && !crtc_state->wm_level_disabled)

RE: [PATCH v4 02/13] drm/i915/display: Switch DC3CO enable from standalone bit to DC level encoding

[Manna, Animesh]

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Wednesday, May 27, 2026 12:48 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>
> Subject: [PATCH v4 02/13] drm/i915/display: Switch DC3CO enable from
> standalone bit to DC level encoding
> 
> On platforms prior to xe3, DC3CO was controlled via a standalone enable bit.
> Starting with xe3, DC3CO is encoded as part of the existing
> DC_STATE_EN_UPTO_DC* field.
> 
> No functional change, as DC3CO is not enabled on platforms prior to xe3.
> 
> Changes in v2:
> - Update commit header (Uma Shankar)
> 
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_power.c      | 6 +++---
>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 4 ++--
>  drivers/gpu/drm/i915/display/intel_display_regs.h       | 2 +-
>  drivers/gpu/drm/i915/display/intel_dmc_wl.c             | 2 +-
>  4 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 751e6b7d4a29..c70971ffd9f0 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -267,7 +267,7 @@ sanitize_target_dc_state(struct intel_display *display,
>  	static const u32 states[] = {
>  		DC_STATE_EN_UPTO_DC6,
>  		DC_STATE_EN_UPTO_DC5,
> -		DC_STATE_EN_DC3CO,
> +		DC_STATE_EN_UPTO_DC3CO,
>  		DC_STATE_DISABLE,
>  	};
>  	int i;
> @@ -999,10 +999,10 @@ static u32 get_allowed_dc_mask(struct
> intel_display *display, int enable_dc)
> 
>  	switch (requested_dc) {
>  	case 4:
> -		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
> +		mask |= DC_STATE_EN_UPTO_DC3CO |
> DC_STATE_EN_UPTO_DC6;
>  		break;
>  	case 3:
> -		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
> +		mask |= DC_STATE_EN_UPTO_DC3CO |
> DC_STATE_EN_UPTO_DC5;
>  		break;
>  	case 2:
>  		mask |= DC_STATE_EN_UPTO_DC6;
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 2f0d0a77c1a2..611f784d8a7a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -772,7 +772,7 @@ static u32 gen9_dc_mask(struct intel_display
> *display)
>  	mask = DC_STATE_EN_UPTO_DC5;
> 
>  	if (DISPLAY_VER(display) >= 12)
> -		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
> +		mask |= DC_STATE_EN_UPTO_DC3CO |
> DC_STATE_EN_UPTO_DC6
>  					  | DC_STATE_EN_DC9;
>  	else if (DISPLAY_VER(display) == 11)
>  		mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
> @@ -1022,7 +1022,7 @@ static void
> bxt_verify_dpio_phy_power_wells(struct intel_display *display)  static bool
> gen9_dc_off_power_well_enabled(struct intel_display *display,
>  					   struct i915_power_well
> *power_well)  {
> -	return ((intel_de_read(display, DC_STATE_EN) &
> DC_STATE_EN_DC3CO) == 0 &&
> +	return ((intel_de_read(display, DC_STATE_EN) &
> DC_STATE_EN_UPTO_DC3CO)
> +== 0 &&
>  		(intel_de_read(display, DC_STATE_EN) &
> DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);  }

Both DC_STATE_EN_UPTO_DC5_DC6_MASK and DC_STATE_EN_UPTO_DC3CO value is matching which will impact fine granularity to control DC3co.
Only enabling Dc3co or enabling with DC5/DC6 may be an issue.

Regards,
Animesh 

> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 4321f8b529da..680e7dfdcf1b 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -3070,13 +3070,13 @@ enum skl_power_gate {
>  /* GEN9 DC */
>  #define DC_STATE_EN			_MMIO(0x45504)
>  #define  DC_STATE_DISABLE		0
> -#define  DC_STATE_EN_DC3CO		REG_BIT(30)
>  #define  DC_STATE_DC3CO_STATUS		REG_BIT(29)
>  #define  HOLD_PHY_CLKREQ_PG1_LATCH	REG_BIT(21)
>  #define  HOLD_PHY_PG1_LATCH		REG_BIT(20)
>  #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
>  #define  DC_STATE_EN_DC9		(1 << 3)
>  #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
> +#define  DC_STATE_EN_UPTO_DC3CO		(3 << 0)
>  #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
> 
>  #define  DC_STATE_DEBUG                  _MMIO(0x45520)
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> index b007343721e1..ab4e0e9573df 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
> @@ -267,7 +267,7 @@ static bool intel_dmc_wl_check_range(struct
> intel_display *display,
>  	 * the DMC and requires a DC exit for proper access.
>  	 */
>  	switch (dc_state) {
> -	case DC_STATE_EN_DC3CO:
> +	case DC_STATE_EN_UPTO_DC3CO:
>  		ranges = xe3lpd_dc3co_dmc_ranges;
>  		break;
>  	case DC_STATE_EN_UPTO_DC5:
> --
> 2.43.0

RE: [PATCH v4 03/13] drm/i915/display: Use FIELD_PREP() for DC state enable bits

[Manna, Animesh]

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Wednesday, May 27, 2026 12:48 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>
> Subject: [PATCH v4 03/13] drm/i915/display: Use FIELD_PREP() for DC state
> enable bits
> 
> Replace open-coded shifts with REG_GENMASK() and REG_FIELD_PREP() for
> the DC state enable field.
> 
> Suggested-by: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_regs.h | 9 +++++----
>  1 file changed, 5 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index 680e7dfdcf1b..efd1a3e56f76 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -3073,11 +3073,12 @@ enum skl_power_gate {
>  #define  DC_STATE_DC3CO_STATUS		REG_BIT(29)
>  #define  HOLD_PHY_CLKREQ_PG1_LATCH	REG_BIT(21)
>  #define  HOLD_PHY_PG1_LATCH		REG_BIT(20)
> -#define  DC_STATE_EN_UPTO_DC5		(1 << 0)
>  #define  DC_STATE_EN_DC9		(1 << 3)
> -#define  DC_STATE_EN_UPTO_DC6		(2 << 0)
> -#define  DC_STATE_EN_UPTO_DC3CO		(3 << 0)
> -#define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
> +#define  DC_STATE_EN_UPTO_DC5_DC6_MASK   REG_GENMASK(1, 0)
> +#define  DC_STATE_EN_DISABLE
> 	REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 0)
> +#define  DC_STATE_EN_UPTO_DC5
> 	REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 1)
> +#define  DC_STATE_EN_UPTO_DC6
> 	REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 2)
> +#define  DC_STATE_EN_UPTO_DC3CO
> 	REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 3)

Misaligned, need extra tab. 

Regards,
Animesh
> 
>  #define  DC_STATE_DEBUG                  _MMIO(0x45520)
>  #define  DC_STATE_DEBUG_MASK_CORES	(1 << 0)
> --
> 2.43.0

RE: [PATCH v4 04/13] drm/i915/display: Add DC3CO DC_STATE enable/disable support

[Manna, Animesh]

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Wednesday, May 27, 2026 12:48 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>
> Subject: [PATCH v4 04/13] drm/i915/display: Add DC3CO DC_STATE
> enable/disable support
> 
> Add DC3CO handling to the dc_off power well sequencing and disable the
> DMC wakelock when exiting DC3CO.
> 
> BSpec: 75253
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  .../drm/i915/display/intel_display_power_well.c  | 16 +++++++++++++++-
>  1 file changed, 15 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 611f784d8a7a..3ea080d0e21e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -866,6 +866,13 @@ void gen9_set_dc_state(struct intel_display *display,
> u32 state)
>  	power_domains->dc_state = val & mask;
>  }
> 
> +static void xe3lpd_enable_dc3co(struct intel_display *display) {

Better to add a assert_can_enable_dc3co() which is followed for other dc-state programming.

Regards,
Animesh

> +	drm_dbg_kms(display->drm, "Enabling DC3CO\n");
> +	intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC3CO);
> +	gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC3CO); }
> +
>  static void assert_can_enable_dc5(struct intel_display *display)  {
>  	enum i915_power_well_id high_pg;
> @@ -1054,9 +1061,13 @@ void gen9_disable_dc_states(struct intel_display
> *display)
>  	}
> 
>  	if (old_state == DC_STATE_EN_UPTO_DC5 ||
> -	    old_state == DC_STATE_EN_UPTO_DC6)
> +	    old_state == DC_STATE_EN_UPTO_DC6 ||
> +	    old_state == DC_STATE_EN_UPTO_DC3CO)
>  		intel_dmc_wl_disable(display);
> 
> +	if (old_state == DC_STATE_EN_UPTO_DC3CO)
> +		return;
> +
>  	intel_cdclk_get_cdclk(display, &cdclk_config);
>  	/* Can't read out voltage_level so can't use intel_cdclk_changed() */
>  	drm_WARN_ON(display->drm,
> @@ -1092,6 +1103,9 @@ static void gen9_dc_off_power_well_disable(struct
> intel_display *display,
>  		return;
> 
>  	switch (power_domains->target_dc_state) {
> +	case DC_STATE_EN_UPTO_DC3CO:
> +		xe3lpd_enable_dc3co(display);
> +		break;
>  	case DC_STATE_EN_UPTO_DC6:
>  		skl_enable_dc6(display);
>  		break;
> --
> 2.43.0

RE: [PATCH v4 12/13] drm/i915/display: Add helper to enable DC counter

[Manna, Animesh]

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Wednesday, May 27, 2026 12:48 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>
> Subject: [PATCH v4 12/13] drm/i915/display: Add helper to enable DC
> counter
> 
> Add xe3lpd_enable_dc_count() to enable the DC_COUNT_EN register.
> Also define DC_STATE_DC3CO_RESIDENCY to read DC3CO residency.
> Needed to retrieve DC residency for DC3CO.
> 
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display_power_well.c | 5 +++++
> drivers/gpu/drm/i915/display/intel_display_power_well.h | 1 +
>  drivers/gpu/drm/i915/display/intel_display_regs.h       | 5 +++++
>  drivers/gpu/drm/i915/display/intel_dmc.c                | 3 +++
>  4 files changed, 14 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 3ea080d0e21e..0e7e6a2b1547 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -866,6 +866,11 @@ void gen9_set_dc_state(struct intel_display *display,
> u32 state)
>  	power_domains->dc_state = val & mask;
>  }
> 
> +void xe3lpd_enable_dc_count(struct intel_display *display) {
> +	intel_de_write(display, DC_COUNT_EN,
> DC_COUNT_EN_COUNTER_ENABLE); }
> +
>  static void xe3lpd_enable_dc3co(struct intel_display *display)  {
>  	drm_dbg_kms(display->drm, "Enabling DC3CO\n"); diff --git
> a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> index 8f5524da2d06..0ce64b894436 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> @@ -159,6 +159,7 @@ void gen9_set_dc_state(struct intel_display *display,
> u32 state);  void gen9_disable_dc_states(struct intel_display *display);  void
> bxt_enable_dc9(struct intel_display *display);  void bxt_disable_dc9(struct
> intel_display *display);
> +void xe3lpd_enable_dc_count(struct intel_display *display);
> 
>  extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
> extern const struct i915_power_well_ops chv_pipe_power_well_ops; diff --
> git a/drivers/gpu/drm/i915/display/intel_display_regs.h
> b/drivers/gpu/drm/i915/display/intel_display_regs.h
> index efd1a3e56f76..875cd06f2566 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
> @@ -3084,6 +3084,11 @@ enum skl_power_gate {
>  #define  DC_STATE_DEBUG_MASK_CORES	(1 << 0)
>  #define  DC_STATE_DEBUG_MASK_MEMORY_UP	(1 << 1)
> 
> +#define DC_COUNT_EN			_MMIO(0x457B4)
> +#define DC_COUNT_EN_COUNTER_ENABLE	REG_BIT(31)
> +
> +#define DC_STATE_DC3CO_RESIDENCY	_MMIO(0x457B8)
> +
>  #define D_COMP_BDW			_MMIO(0x138144)
> 
>  /* Pipe WM_LINETIME - watermark line time */ diff --git
> a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index 4785001644f5..a133785c815b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -941,6 +941,9 @@ void intel_dmc_load_program(struct intel_display
> *display)
> 
>  	gen9_set_dc_state_debugmask(display);
> 
> +	if (DISPLAY_VER(display) >= 35)

HAS_DC3CO() check instead of display ver?

Regards,
Animesh
> +		xe3lpd_enable_dc_count(display);
> +
>  	pipedmc_clock_gating_wa(display, false);  }
> 
> --
> 2.43.0

RE: [PATCH v4 13/13] drm/i915/display: Add DC3CO count and residency in dmc debugfs

[Manna, Animesh]

> -----Original Message-----
> From: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> Sent: Wednesday, May 27, 2026 12:48 AM
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
> <uma.shankar@intel.com>
> Subject: [PATCH v4 13/13] drm/i915/display: Add DC3CO count and residency
> in dmc debugfs
> 
> Expose DC3CO count and residency for xe3lp platforms via debugfs.
> 
> Changes in v4:
> - Keep dc5_reg register initialization to avoid any
>   invalid access (sashiko)
> 
> Signed-off-by: Dibin Moolakadan Subrahmanian
> <dibin.moolakadan.subrahmanian@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_dmc.c      | 9 ++++++++-
>  drivers/gpu/drm/i915/display/intel_dmc_regs.h | 2 ++
>  2 files changed, 10 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
> b/drivers/gpu/drm/i915/display/intel_dmc.c
> index a133785c815b..5ffe2b1c3c51 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
> @@ -1650,7 +1650,14 @@ static int intel_dmc_debugfs_status_show(struct
> seq_file *m, void *unused)
>  		   DMC_VERSION_MINOR(dmc->version));
> 
>  	if (DISPLAY_VER(display) >= 12) {
> -		if (display->platform.dgfx || DISPLAY_VER(display) >= 14) {
> +		if (DISPLAY_VER(display) >= 35) {
> +			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
> +			seq_printf(m, "DC3CO count: %d\n",
> +				   intel_de_read(display,
> XE3P_DMC_DC3CO_COUNT));
> +
> +			seq_printf(m, "DC3CO residency: %d\n",
> +				   intel_de_read(display,
> DC_STATE_DC3CO_RESIDENCY));
> +		} else if (display->platform.dgfx || DISPLAY_VER(display) >=
> 14) {
>  			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
>  		} else {
>  			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> index 38e342b45af0..1998549b6318 100644
> --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
> @@ -531,6 +531,8 @@ enum pipedmc_event_id {
>  #define TGL_DMC_DEBUG3		_MMIO(0x101090)
>  #define DG1_DMC_DEBUG3		_MMIO(0x13415c)
> 
> +#define XE3P_DMC_DC3CO_COUNT	_MMIO(0x8f05C)

Lower and upper-case mixing.

Regards,
Animesh

> +
>  #define DMC_WAKELOCK_CFG	_MMIO(0x8F1B0)
>  #define  DMC_WAKELOCK_CFG_ENABLE REG_BIT(31)
>  #define DMC_WAKELOCK1_CTL	_MMIO(0x8F140)
> --
> 2.43.0

Re: [PATCH v4 02/13] drm/i915/display: Switch DC3CO enable from standalone bit to DC level encoding

[Dibin Moolakadan Subrahmanian]

On 01-06-2026 10:55, Manna, Animesh wrote:
>
>> -----Original Message-----
>> From: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> Sent: Wednesday, May 27, 2026 12:48 AM
>> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
>> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
>> <uma.shankar@intel.com>
>> Subject: [PATCH v4 02/13] drm/i915/display: Switch DC3CO enable from
>> standalone bit to DC level encoding
>>
>> On platforms prior to xe3, DC3CO was controlled via a standalone enable bit.
>> Starting with xe3, DC3CO is encoded as part of the existing
>> DC_STATE_EN_UPTO_DC* field.
>>
>> No functional change, as DC3CO is not enabled on platforms prior to xe3.
>>
>> Changes in v2:
>> - Update commit header (Uma Shankar)
>>
>> Signed-off-by: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display_power.c      | 6 +++---
>>   drivers/gpu/drm/i915/display/intel_display_power_well.c | 4 ++--
>>   drivers/gpu/drm/i915/display/intel_display_regs.h       | 2 +-
>>   drivers/gpu/drm/i915/display/intel_dmc_wl.c             | 2 +-
>>   4 files changed, 7 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
>> b/drivers/gpu/drm/i915/display/intel_display_power.c
>> index 751e6b7d4a29..c70971ffd9f0 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
>> @@ -267,7 +267,7 @@ sanitize_target_dc_state(struct intel_display *display,
>>   	static const u32 states[] = {
>>   		DC_STATE_EN_UPTO_DC6,
>>   		DC_STATE_EN_UPTO_DC5,
>> -		DC_STATE_EN_DC3CO,
>> +		DC_STATE_EN_UPTO_DC3CO,
>>   		DC_STATE_DISABLE,
>>   	};
>>   	int i;
>> @@ -999,10 +999,10 @@ static u32 get_allowed_dc_mask(struct
>> intel_display *display, int enable_dc)
>>
>>   	switch (requested_dc) {
>>   	case 4:
>> -		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6;
>> +		mask |= DC_STATE_EN_UPTO_DC3CO |
>> DC_STATE_EN_UPTO_DC6;
>>   		break;
>>   	case 3:
>> -		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC5;
>> +		mask |= DC_STATE_EN_UPTO_DC3CO |
>> DC_STATE_EN_UPTO_DC5;
>>   		break;
>>   	case 2:
>>   		mask |= DC_STATE_EN_UPTO_DC6;
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> index 2f0d0a77c1a2..611f784d8a7a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> @@ -772,7 +772,7 @@ static u32 gen9_dc_mask(struct intel_display
>> *display)
>>   	mask = DC_STATE_EN_UPTO_DC5;
>>
>>   	if (DISPLAY_VER(display) >= 12)
>> -		mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
>> +		mask |= DC_STATE_EN_UPTO_DC3CO |
>> DC_STATE_EN_UPTO_DC6
>>   					  | DC_STATE_EN_DC9;
>>   	else if (DISPLAY_VER(display) == 11)
>>   		mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
>> @@ -1022,7 +1022,7 @@ static void
>> bxt_verify_dpio_phy_power_wells(struct intel_display *display)  static bool
>> gen9_dc_off_power_well_enabled(struct intel_display *display,
>>   					   struct i915_power_well
>> *power_well)  {
>> -	return ((intel_de_read(display, DC_STATE_EN) &
>> DC_STATE_EN_DC3CO) == 0 &&
>> +	return ((intel_de_read(display, DC_STATE_EN) &
>> DC_STATE_EN_UPTO_DC3CO)
>> +== 0 &&
>>   		(intel_de_read(display, DC_STATE_EN) &
>> DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);  }
> Both DC_STATE_EN_UPTO_DC5_DC6_MASK and DC_STATE_EN_UPTO_DC3CO value is matching which will impact fine granularity to control DC3co.
> Only enabling Dc3co or enabling with DC5/DC6 may be an issue.

Thanks for the review.
Since the DC3CO enable value is 0x3,
DC_STATE_EN_UPTO_DC3CO and DC_STATE_EN_UPTO_DC5_DC6_MASK evaluate to the same value.

That said, DC_STATE_EN_UPTO_DC5_DC6_MASK can be renamed
to DC_STATE_EN_UPTO_DC3CO_DC5_DC6_MASK to better reflect the bits covered by the mask.

I assumed DC3CO-only enablement would be mainly for validation purposes.
Would it be okay to handle that in a follow-up?

>
> Regards,
> Animesh
>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
>> b/drivers/gpu/drm/i915/display/intel_display_regs.h
>> index 4321f8b529da..680e7dfdcf1b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
>> @@ -3070,13 +3070,13 @@ enum skl_power_gate {
>>   /* GEN9 DC */
>>   #define DC_STATE_EN			_MMIO(0x45504)
>>   #define  DC_STATE_DISABLE		0
>> -#define  DC_STATE_EN_DC3CO		REG_BIT(30)
>>   #define  DC_STATE_DC3CO_STATUS		REG_BIT(29)
>>   #define  HOLD_PHY_CLKREQ_PG1_LATCH	REG_BIT(21)
>>   #define  HOLD_PHY_PG1_LATCH		REG_BIT(20)
>>   #define  DC_STATE_EN_UPTO_DC5		(1 << 0)
>>   #define  DC_STATE_EN_DC9		(1 << 3)
>>   #define  DC_STATE_EN_UPTO_DC6		(2 << 0)
>> +#define  DC_STATE_EN_UPTO_DC3CO		(3 << 0)
>>   #define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
>>
>>   #define  DC_STATE_DEBUG                  _MMIO(0x45520)
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
>> b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
>> index b007343721e1..ab4e0e9573df 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dmc_wl.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_wl.c
>> @@ -267,7 +267,7 @@ static bool intel_dmc_wl_check_range(struct
>> intel_display *display,
>>   	 * the DMC and requires a DC exit for proper access.
>>   	 */
>>   	switch (dc_state) {
>> -	case DC_STATE_EN_DC3CO:
>> +	case DC_STATE_EN_UPTO_DC3CO:
>>   		ranges = xe3lpd_dc3co_dmc_ranges;
>>   		break;
>>   	case DC_STATE_EN_UPTO_DC5:
>> --
>> 2.43.0

Re: [PATCH v4 03/13] drm/i915/display: Use FIELD_PREP() for DC state enable bits

[Dibin Moolakadan Subrahmanian]

On 01-06-2026 11:00, Manna, Animesh wrote:
>
>> -----Original Message-----
>> From: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> Sent: Wednesday, May 27, 2026 12:48 AM
>> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
>> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
>> <uma.shankar@intel.com>
>> Subject: [PATCH v4 03/13] drm/i915/display: Use FIELD_PREP() for DC state
>> enable bits
>>
>> Replace open-coded shifts with REG_GENMASK() and REG_FIELD_PREP() for
>> the DC state enable field.
>>
>> Suggested-by: Jani Nikula <jani.nikula@linux.intel.com>
>> Signed-off-by: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display_regs.h | 9 +++++----
>>   1 file changed, 5 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h
>> b/drivers/gpu/drm/i915/display/intel_display_regs.h
>> index 680e7dfdcf1b..efd1a3e56f76 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
>> @@ -3073,11 +3073,12 @@ enum skl_power_gate {
>>   #define  DC_STATE_DC3CO_STATUS		REG_BIT(29)
>>   #define  HOLD_PHY_CLKREQ_PG1_LATCH	REG_BIT(21)
>>   #define  HOLD_PHY_PG1_LATCH		REG_BIT(20)
>> -#define  DC_STATE_EN_UPTO_DC5		(1 << 0)
>>   #define  DC_STATE_EN_DC9		(1 << 3)
>> -#define  DC_STATE_EN_UPTO_DC6		(2 << 0)
>> -#define  DC_STATE_EN_UPTO_DC3CO		(3 << 0)
>> -#define  DC_STATE_EN_UPTO_DC5_DC6_MASK   0x3
>> +#define  DC_STATE_EN_UPTO_DC5_DC6_MASK   REG_GENMASK(1, 0)
>> +#define  DC_STATE_EN_DISABLE
>> 	REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 0)
>> +#define  DC_STATE_EN_UPTO_DC5
>> 	REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 1)
>> +#define  DC_STATE_EN_UPTO_DC6
>> 	REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 2)
>> +#define  DC_STATE_EN_UPTO_DC3CO
>> 	REG_FIELD_PREP(DC_STATE_EN_UPTO_DC5_DC6_MASK, 3)
> Misaligned, need extra tab.

Thanks, I'll fix the alignment in the next revision.

>
> Regards,
> Animesh
>>   #define  DC_STATE_DEBUG                  _MMIO(0x45520)
>>   #define  DC_STATE_DEBUG_MASK_CORES	(1 << 0)
>> --
>> 2.43.0

Re: [PATCH v4 04/13] drm/i915/display: Add DC3CO DC_STATE enable/disable support

[Dibin Moolakadan Subrahmanian]

On 01-06-2026 11:12, Manna, Animesh wrote:
>
>> -----Original Message-----
>> From: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> Sent: Wednesday, May 27, 2026 12:48 AM
>> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
>> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
>> <uma.shankar@intel.com>
>> Subject: [PATCH v4 04/13] drm/i915/display: Add DC3CO DC_STATE
>> enable/disable support
>>
>> Add DC3CO handling to the dc_off power well sequencing and disable the
>> DMC wakelock when exiting DC3CO.
>>
>> BSpec: 75253
>> Signed-off-by: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>>   .../drm/i915/display/intel_display_power_well.c  | 16 +++++++++++++++-
>>   1 file changed, 15 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> index 611f784d8a7a..3ea080d0e21e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> @@ -866,6 +866,13 @@ void gen9_set_dc_state(struct intel_display *display,
>> u32 state)
>>   	power_domains->dc_state = val & mask;
>>   }
>>
>> +static void xe3lpd_enable_dc3co(struct intel_display *display) {
> Better to add a assert_can_enable_dc3co() which is followed for other dc-state programming.
Thanks, I'll  add this check in the next revision.
>
> Regards,
> Animesh
>
>> +	drm_dbg_kms(display->drm, "Enabling DC3CO\n");
>> +	intel_dmc_wl_enable(display, DC_STATE_EN_UPTO_DC3CO);
>> +	gen9_set_dc_state(display, DC_STATE_EN_UPTO_DC3CO); }
>> +
>>   static void assert_can_enable_dc5(struct intel_display *display)  {
>>   	enum i915_power_well_id high_pg;
>> @@ -1054,9 +1061,13 @@ void gen9_disable_dc_states(struct intel_display
>> *display)
>>   	}
>>
>>   	if (old_state == DC_STATE_EN_UPTO_DC5 ||
>> -	    old_state == DC_STATE_EN_UPTO_DC6)
>> +	    old_state == DC_STATE_EN_UPTO_DC6 ||
>> +	    old_state == DC_STATE_EN_UPTO_DC3CO)
>>   		intel_dmc_wl_disable(display);
>>
>> +	if (old_state == DC_STATE_EN_UPTO_DC3CO)
>> +		return;
>> +
>>   	intel_cdclk_get_cdclk(display, &cdclk_config);
>>   	/* Can't read out voltage_level so can't use intel_cdclk_changed() */
>>   	drm_WARN_ON(display->drm,
>> @@ -1092,6 +1103,9 @@ static void gen9_dc_off_power_well_disable(struct
>> intel_display *display,
>>   		return;
>>
>>   	switch (power_domains->target_dc_state) {
>> +	case DC_STATE_EN_UPTO_DC3CO:
>> +		xe3lpd_enable_dc3co(display);
>> +		break;
>>   	case DC_STATE_EN_UPTO_DC6:
>>   		skl_enable_dc6(display);
>>   		break;
>> --
>> 2.43.0

Re: [PATCH v4 12/13] drm/i915/display: Add helper to enable DC counter

[Dibin Moolakadan Subrahmanian]

On 01-06-2026 11:17, Manna, Animesh wrote:
>
>> -----Original Message-----
>> From: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> Sent: Wednesday, May 27, 2026 12:48 AM
>> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
>> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
>> <uma.shankar@intel.com>
>> Subject: [PATCH v4 12/13] drm/i915/display: Add helper to enable DC
>> counter
>>
>> Add xe3lpd_enable_dc_count() to enable the DC_COUNT_EN register.
>> Also define DC_STATE_DC3CO_RESIDENCY to read DC3CO residency.
>> Needed to retrieve DC residency for DC3CO.
>>
>> Signed-off-by: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_display_power_well.c | 5 +++++
>> drivers/gpu/drm/i915/display/intel_display_power_well.h | 1 +
>>   drivers/gpu/drm/i915/display/intel_display_regs.h       | 5 +++++
>>   drivers/gpu/drm/i915/display/intel_dmc.c                | 3 +++
>>   4 files changed, 14 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> index 3ea080d0e21e..0e7e6a2b1547 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
>> @@ -866,6 +866,11 @@ void gen9_set_dc_state(struct intel_display *display,
>> u32 state)
>>   	power_domains->dc_state = val & mask;
>>   }
>>
>> +void xe3lpd_enable_dc_count(struct intel_display *display) {
>> +	intel_de_write(display, DC_COUNT_EN,
>> DC_COUNT_EN_COUNTER_ENABLE); }
>> +
>>   static void xe3lpd_enable_dc3co(struct intel_display *display)  {
>>   	drm_dbg_kms(display->drm, "Enabling DC3CO\n"); diff --git
>> a/drivers/gpu/drm/i915/display/intel_display_power_well.h
>> b/drivers/gpu/drm/i915/display/intel_display_power_well.h
>> index 8f5524da2d06..0ce64b894436 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
>> @@ -159,6 +159,7 @@ void gen9_set_dc_state(struct intel_display *display,
>> u32 state);  void gen9_disable_dc_states(struct intel_display *display);  void
>> bxt_enable_dc9(struct intel_display *display);  void bxt_disable_dc9(struct
>> intel_display *display);
>> +void xe3lpd_enable_dc_count(struct intel_display *display);
>>
>>   extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
>> extern const struct i915_power_well_ops chv_pipe_power_well_ops; diff --
>> git a/drivers/gpu/drm/i915/display/intel_display_regs.h
>> b/drivers/gpu/drm/i915/display/intel_display_regs.h
>> index efd1a3e56f76..875cd06f2566 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_regs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h
>> @@ -3084,6 +3084,11 @@ enum skl_power_gate {
>>   #define  DC_STATE_DEBUG_MASK_CORES	(1 << 0)
>>   #define  DC_STATE_DEBUG_MASK_MEMORY_UP	(1 << 1)
>>
>> +#define DC_COUNT_EN			_MMIO(0x457B4)
>> +#define DC_COUNT_EN_COUNTER_ENABLE	REG_BIT(31)
>> +
>> +#define DC_STATE_DC3CO_RESIDENCY	_MMIO(0x457B8)
>> +
>>   #define D_COMP_BDW			_MMIO(0x138144)
>>
>>   /* Pipe WM_LINETIME - watermark line time */ diff --git
>> a/drivers/gpu/drm/i915/display/intel_dmc.c
>> b/drivers/gpu/drm/i915/display/intel_dmc.c
>> index 4785001644f5..a133785c815b 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>> @@ -941,6 +941,9 @@ void intel_dmc_load_program(struct intel_display
>> *display)
>>
>>   	gen9_set_dc_state_debugmask(display);
>>
>> +	if (DISPLAY_VER(display) >= 35)
> HAS_DC3CO() check instead of display ver?

The check is intentional.DC count is not tied only to DC3CO support,
so I used the display version check here.

>
> Regards,
> Animesh
>> +		xe3lpd_enable_dc_count(display);
>> +
>>   	pipedmc_clock_gating_wa(display, false);  }
>>
>> --
>> 2.43.0

Re: [PATCH v4 13/13] drm/i915/display: Add DC3CO count and residency in dmc debugfs

[Dibin Moolakadan Subrahmanian]

On 01-06-2026 11:20, Manna, Animesh wrote:
>
>> -----Original Message-----
>> From: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> Sent: Wednesday, May 27, 2026 12:48 AM
>> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
>> Cc: Manna, Animesh <animesh.manna@intel.com>; Shankar, Uma
>> <uma.shankar@intel.com>
>> Subject: [PATCH v4 13/13] drm/i915/display: Add DC3CO count and residency
>> in dmc debugfs
>>
>> Expose DC3CO count and residency for xe3lp platforms via debugfs.
>>
>> Changes in v4:
>> - Keep dc5_reg register initialization to avoid any
>>    invalid access (sashiko)
>>
>> Signed-off-by: Dibin Moolakadan Subrahmanian
>> <dibin.moolakadan.subrahmanian@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_dmc.c      | 9 ++++++++-
>>   drivers/gpu/drm/i915/display/intel_dmc_regs.h | 2 ++
>>   2 files changed, 10 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc.c
>> b/drivers/gpu/drm/i915/display/intel_dmc.c
>> index a133785c815b..5ffe2b1c3c51 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dmc.c
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc.c
>> @@ -1650,7 +1650,14 @@ static int intel_dmc_debugfs_status_show(struct
>> seq_file *m, void *unused)
>>   		   DMC_VERSION_MINOR(dmc->version));
>>
>>   	if (DISPLAY_VER(display) >= 12) {
>> -		if (display->platform.dgfx || DISPLAY_VER(display) >= 14) {
>> +		if (DISPLAY_VER(display) >= 35) {
>> +			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
>> +			seq_printf(m, "DC3CO count: %d\n",
>> +				   intel_de_read(display,
>> XE3P_DMC_DC3CO_COUNT));
>> +
>> +			seq_printf(m, "DC3CO residency: %d\n",
>> +				   intel_de_read(display,
>> DC_STATE_DC3CO_RESIDENCY));
>> +		} else if (display->platform.dgfx || DISPLAY_VER(display) >=
>> 14) {
>>   			dc5_reg = DG1_DMC_DEBUG_DC5_COUNT;
>>   		} else {
>>   			dc5_reg = TGL_DMC_DEBUG_DC5_COUNT;
>> diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
>> b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
>> index 38e342b45af0..1998549b6318 100644
>> --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h
>> @@ -531,6 +531,8 @@ enum pipedmc_event_id {
>>   #define TGL_DMC_DEBUG3		_MMIO(0x101090)
>>   #define DG1_DMC_DEBUG3		_MMIO(0x13415c)
>>
>> +#define XE3P_DMC_DC3CO_COUNT	_MMIO(0x8f05C)
> Lower and upper-case mixing.

Will change it to lower case in the next version.

> Regards,
> Animesh
>
>> +
>>   #define DMC_WAKELOCK_CFG	_MMIO(0x8F1B0)
>>   #define  DMC_WAKELOCK_CFG_ENABLE REG_BIT(31)
>>   #define DMC_WAKELOCK1_CTL	_MMIO(0x8F140)
>> --
>> 2.43.0