From: "Shankar, Uma" <uma.shankar@intel.com>
To: "Gupta, Anshuman" <anshuman.gupta@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>
Cc: "Nikula, Jani" <jani.nikula@intel.com>,
"seanpaul@chromium.org" <seanpaul@chromium.org>
Subject: Re: [Intel-gfx] [PATCH v3 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register
Date: Tue, 27 Oct 2020 07:11:41 +0000 [thread overview]
Message-ID: <3b7df974286b4497ba31ad4a554062e0@intel.com> (raw)
In-Reply-To: <20201023122112.15265-15-anshuman.gupta@intel.com>
> -----Original Message-----
> From: Anshuman Gupta <anshuman.gupta@intel.com>
> Sent: Friday, October 23, 2020 5:51 PM
> To: intel-gfx@lists.freedesktop.org; dri-devel@lists.freedesktop.org
> Cc: seanpaul@chromium.org; Nikula, Jani <jani.nikula@intel.com>; C,
> Ramalingam <ramalingam.c@intel.com>; Li, Juston <juston.li@intel.com>;
> Shankar, Uma <uma.shankar@intel.com>; Gupta, Anshuman
> <anshuman.gupta@intel.com>
> Subject: [PATCH v3 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register
>
> Add HDCP 2.2 DP MST HDCP2_STREAM_STATUS
> and HDCP2_AUTH_STREAM register in i915_reg header.
>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 86a9a5145e47..cb6ec2c241f2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9882,6 +9882,7 @@ enum skl_power_gate {
> _PORTD_HDCP2_BASE, \
> _PORTE_HDCP2_BASE, \
> _PORTF_HDCP2_BASE) + (x))
> +
> #define PORT_HDCP2_AUTH(port) _PORT_HDCP2_BASE(port, 0x98)
> #define _TRANSA_HDCP2_AUTH 0x66498
> #define _TRANSB_HDCP2_AUTH 0x66598
> @@ -9921,6 +9922,35 @@ enum skl_power_gate {
> TRANS_HDCP2_STATUS(trans) : \
> PORT_HDCP2_STATUS(port))
>
> +#define PORT_HDCP2_STREAM_STATUS(port) _PORT_HDCP2_BASE(port,
> 0xC0)
> +#define _TRANSA_HDCP2_STREAM_STATUS 0x664C0
> +#define _TRANSB_HDCP2_STREAM_STATUS 0x665C0
> +#define TRANS_HDCP2_STREAM_STATUS(trans) _MMIO_TRANS(trans, \
> +
> _TRANSA_HDCP2_STREAM_STATUS, \
> +
> _TRANSB_HDCP2_STREAM_STATUS)
> +#define STREAM_ENCRYPTION_STATUS BIT(31)
> +#define STREAM_TYPE_STATUS BIT(30)
> +#define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP2_STREAM_STATUS(trans) :
> \
> + PORT_HDCP2_STREAM_STATUS(port))
> +
> +#define _PORTA_HDCP2_AUTH_STREAM 0x66F00
> +#define _PORTB_HDCP2_AUTH_STREAM 0x66F04
> +#define PORT_HDCP2_AUTH_STREAM(port) _MMIO_PORT(port, \
> +
> _PORTA_HDCP2_AUTH_STREAM, \
> +
> _PORTB_HDCP2_AUTH_STREAM)
Should it also not be defined as the other counterparts for pre Gen12.
> +#define _TRANSA_HDCP2_AUTH_STREAM 0x66F00
> +#define _TRANSB_HDCP2_AUTH_STREAM 0x66F04
> +#define TRANS_HDCP2_AUTH_STREAM(trans) _MMIO_TRANS(trans, \
> +
> _TRANSA_HDCP2_AUTH_STREAM, \
> +
> _TRANSB_HDCP2_AUTH_STREAM)
> +#define AUTH_STREAM_TYPE BIT(31)
> +#define HDCP2_AUTH_STREAM(dev_priv, trans, port) \
> + (INTEL_GEN(dev_priv) >= 12 ? \
> + TRANS_HDCP2_AUTH_STREAM(trans) : \
> + PORT_HDCP2_AUTH_STREAM(port))
> +
> /* Per-pipe DDI Function Control */
> #define _TRANS_DDI_FUNC_CTL_A 0x60400
> #define _TRANS_DDI_FUNC_CTL_B 0x61400
> --
> 2.26.2
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next prev parent reply other threads:[~2020-10-27 7:11 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-23 12:20 [Intel-gfx] [PATCH v3 00/16] HDCP 2.2 and HDCP 1.4 Gen12 DP MST support Anshuman Gupta
2020-10-23 12:20 ` [Intel-gfx] [PATCH v3 01/16] drm/i915/hdcp: Update CP property in update_pipe Anshuman Gupta
2020-10-27 5:32 ` Shankar, Uma
2020-10-27 7:50 ` Anshuman Gupta
2020-10-23 12:20 ` [Intel-gfx] [PATCH v3 02/16] drm/i915/hdcp: Get conn while content_type changed Anshuman Gupta
2020-10-27 5:34 ` Shankar, Uma
2020-10-27 5:37 ` Anshuman Gupta
2020-10-23 12:20 ` [Intel-gfx] [PATCH v3 03/16] drm/i915/hotplug: Handle CP_IRQ for DP-MST Anshuman Gupta
2020-10-27 5:43 ` Shankar, Uma
2020-10-23 12:21 ` [Intel-gfx] [PATCH v3 04/16] drm/i915/hdcp: DP MST transcoder for link and stream Anshuman Gupta
2020-10-27 5:49 ` Shankar, Uma
2020-10-23 12:21 ` [Intel-gfx] [PATCH v3 05/16] drm/i915/hdcp: Move HDCP enc status timeout to header Anshuman Gupta
2020-10-27 5:52 ` Shankar, Uma
2020-10-23 12:21 ` [Intel-gfx] [PATCH v3 06/16] drm/i915/hdcp: HDCP stream encryption support Anshuman Gupta
2020-10-27 6:20 ` Shankar, Uma
2020-10-27 7:46 ` Anshuman Gupta
2020-10-23 12:21 ` [Intel-gfx] [PATCH v3 07/16] drm/i915/hdcp: Enable Gen12 HDCP 1.4 DP MST support Anshuman Gupta
2020-10-27 6:29 ` Shankar, Uma
2020-10-27 7:57 ` Anshuman Gupta
2020-10-27 12:04 ` Anshuman Gupta
2020-10-23 12:21 ` [Intel-gfx] [PATCH v3 08/16] drm/i915/hdcp: Pass dig_port to intel_hdcp_init Anshuman Gupta
2020-10-27 6:30 ` Shankar, Uma
2020-10-23 12:21 ` [Intel-gfx] [PATCH v3 09/16] drm/i915/hdcp: Encapsulate hdcp_port_data to dig_port Anshuman Gupta
2020-10-27 6:34 ` Shankar, Uma
2020-10-23 12:21 ` [Intel-gfx] [PATCH v3 10/16] misc/mei/hdcp: Fix AUTH_STREAM_REQ cmd buffer len Anshuman Gupta
2020-10-27 6:36 ` Shankar, Uma
2020-10-27 6:39 ` Winkler, Tomas
2020-10-23 12:21 ` [Intel-gfx] [PATCH v3 11/16] drm/hdcp: Max MST content streams Anshuman Gupta
2020-10-27 6:41 ` Shankar, Uma
2020-10-23 12:21 ` [Intel-gfx] [PATCH v3 12/16] drm/i915/hdcp: MST streams support in hdcp port_data Anshuman Gupta
2020-10-27 6:55 ` Shankar, Uma
2020-10-23 12:21 ` [Intel-gfx] [PATCH v3 13/16] drm/i915/hdcp: Pass connector to check_2_2_link Anshuman Gupta
2020-10-27 6:57 ` Shankar, Uma
2020-10-23 12:21 ` [Intel-gfx] [PATCH v3 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register Anshuman Gupta
2020-10-27 7:11 ` Shankar, Uma [this message]
2020-10-27 8:57 ` Anshuman Gupta
2020-10-27 9:50 ` Shankar, Uma
2020-10-23 12:21 ` [Intel-gfx] [PATCH v3 15/16] drm/i915/hdcp: Support for HDCP 2.2 MST shim callbacks Anshuman Gupta
2020-10-27 7:20 ` Shankar, Uma
2020-10-23 12:21 ` [Intel-gfx] [PATCH v3 16/16] drm/i915/hdcp: Enable HDCP 2.2 MST support Anshuman Gupta
2020-10-27 7:24 ` Shankar, Uma
2020-10-23 14:41 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for HDCP 2.2 and HDCP 1.4 Gen12 DP " Patchwork
2020-10-23 14:42 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-10-23 15:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-10-23 18:54 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
-- strict thread matches above, loose matches on Subject: below --
2020-10-22 8:55 [Intel-gfx] [PATCH v3 00/16] HDCP 2.2 DP MST Support Anshuman Gupta
2020-10-22 8:55 ` [Intel-gfx] [PATCH v3 14/16] drm/i915/hdcp: Add HDCP 2.2 stream register Anshuman Gupta
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