From: "Hogander, Jouni" <jouni.hogander@intel.com>
To: "intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"Souza, Jose" <jose.souza@intel.com>
Cc: "Lin, Charlton" <charlton.lin@intel.com>
Subject: Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/display: Do not re-enable PSR after it was marked as not reliable
Date: Tue, 15 Mar 2022 13:29:51 +0000 [thread overview]
Message-ID: <3fbbaaecb4683a234e3a4d611b2906c74ef4dd09.camel@intel.com> (raw)
In-Reply-To: <20220311185149.110527-2-jose.souza@intel.com>
On Fri, 2022-03-11 at 10:51 -0800, José Roberto de Souza wrote:
> If a error happens and sink_not_reliable is set, PSR should be
> disabled
> for good but that is not happening.
> It would be disabled by the function handling the PSR error but then
> on the next fastset it would be enabled again in
> _intel_psr_post_plane_update().
> It would only be disabled for good in the next modeset where has_psr
> will be set false.
>
> v2:
> - release psr lock before continue
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
>
> Fixes: 9ce5884e5139 ("drm/i915/display: Only keep PSR enabled if
> there is active planes")
> Reported-by: Khaled Almahallawy <khaled.almahallawy@intel.com>
> Reported-by: Charlton Lin <charlton.lin@intel.com>
> Cc: Jouni Högander <jouni.hogander@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index bbd581ed08159..80002ca6a6ebe 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1853,6 +1853,9 @@ static void _intel_psr_post_plane_update(const
> struct intel_atomic_state *state,
>
> mutex_lock(&psr->lock);
>
> + if (psr->sink_not_reliable)
> + goto exit;
> +
> drm_WARN_ON(&dev_priv->drm, psr->enabled &&
> !crtc_state->active_planes);
>
> /* Only enable if there is active planes */
> @@ -1863,6 +1866,7 @@ static void _intel_psr_post_plane_update(const
> struct intel_atomic_state *state,
> if (crtc_state->crc_enabled && psr->enabled)
> psr_force_hw_tracking_exit(intel_dp);
>
> +exit:
> mutex_unlock(&psr->lock);
> }
> }
next prev parent reply other threads:[~2022-03-15 13:29 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-11 18:51 [Intel-gfx] [PATCH v2 1/2] drm/i915/display: Fix HPD short pulse handling for eDP José Roberto de Souza
2022-03-11 18:51 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/display: Do not re-enable PSR after it was marked as not reliable José Roberto de Souza
2022-03-15 13:29 ` Hogander, Jouni [this message]
2022-03-11 21:20 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [v2,1/2] drm/i915/display: Fix HPD short pulse handling for eDP Patchwork
2022-03-14 14:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/display: Fix HPD short pulse handling for eDP (rev2) Patchwork
2022-03-14 17:38 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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