Re: [PATCH 03/11] drm/i915/bw: Initialize num_planes sensibly for the first plane group in TGL+

["Govindapillai, Vinod" <vinod.govindapillai@intel.com>]

On Thu, 2026-05-28 at 13:34 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The way the TGL+ bw algorithm works is that 'num_planes'
> is really a maximum number of allowed planes (whereas in
> the ICL version it was more of a minimum), and the
> assumption is that the first plane group (max[0]) can be
> used with any number of planes (tgl_max_bw_index() always
> returns 0 at the end).
> 
> To make things a bit less weird let's just set the first
> plane group's num_planes to some big number to indicate it
> has no real limit on the number of planes.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_bw.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> b/drivers/gpu/drm/i915/display/intel_bw.c
> index 887628144864..4b5db4ca7773 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -629,6 +629,8 @@ static int tgl_get_bw_info(struct intel_display
> *display,
>  	 */
>  	clperchgroup = 4 * (8 / num_channels) * qi.deinterleave;
>  
> +	display->bw.max[0].num_planes = U8_MAX;
> +
>  	for (i = 0; i < num_groups; i++) {
>  		struct intel_bw_info *bi = &display->bw.max[i];
>  		struct intel_bw_info *bi_next;
> @@ -701,10 +703,10 @@ static void dg2_get_bw_info(struct
> intel_display *display)
>  {
>  	int i;
>  
> +	display->bw.max[0].num_planes = U8_MAX;
>  	display->bw.max[0].deratedbw[0] = display->platform.dg2_g11
> ? 38000 : 50000;
>  
>  	/* Bandwidth does not depend on # of planes; set all groups
> the same */
> -	display->bw.max[0].num_planes = 1;
>  	display->bw.max[0].num_qgv_points = 1;
>  	for (i = 1; i < ARRAY_SIZE(display->bw.max); i++)
>  		display->bw.max[i] = display->bw.max[0];
> @@ -731,6 +733,8 @@ static int xe2_hpd_get_bw_info(struct
> intel_display *display,
>  	peakbw = tgl_peakbw(num_channels, qi.channel_width,
> icl_sagv_max_dclk(&qi));
>  	maxdebw = min(soc_bw_params->deprogbwlimit * 1000, peakbw *
> DEPROGBWPCLIMIT / 100);
>  
> +	display->bw.max[0].num_planes = U8_MAX;
> +
>  	for (i = 0; i < qi.num_points; i++) {
>  		const struct intel_qgv_point *sp = &qi.points[i];
>  		int bw = tgl_peakbw(num_channels, qi.channel_width,
> sp->dclk);
> @@ -745,7 +749,6 @@ static int xe2_hpd_get_bw_info(struct
> intel_display *display,
>  	}
>  
>  	/* Bandwidth does not depend on # of planes; set all groups
> the same */
> -	display->bw.max[0].num_planes = 1;
>  	display->bw.max[0].num_qgv_points = qi.num_points;
>  	for (i = 1; i < ARRAY_SIZE(display->bw.max); i++)
>  		display->bw.max[i] = display->bw.max[0];
> @@ -808,7 +811,7 @@ static unsigned int tgl_max_bw_index(struct
> intel_display *display,
>  			return i;
>  	}
>  
> -	return 0;
> +	return UINT_MAX;
>  }

Thanks for the details. I had a wrong understanding about this bw
groups. Well it kind of worked when I added the pmdemand stuff related
find qgv points for mtl as it was returning 0 here!

But I see that you had updated the mtl_find_qgv_points() part of this
as a separate patch. Should that be squashed into this as well? 

Other than that, things look much logical now.

Reviewed-by: Vinod Govindapillai <vinod.govindapillai@intel.com>

>  
>  static unsigned int adl_psf_bw(struct intel_display *display,