From: Chris Wilson <chris@chris-wilson.co.uk>
To: Jesse Barnes <jbarnes@virtuousgeek.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 01/11] drm/i915: Fix display pixel format handling
Date: Thu, 01 Nov 2012 14:06:42 +0000 [thread overview]
Message-ID: <453bf0$6acuf6@azsmga001.ch.intel.com> (raw)
In-Reply-To: <20121101140313.GL3791@intel.com>
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On Thu, 1 Nov 2012 16:03:13 +0200, Ville Syrjälä <ville.syrjala@linux.intel.com> wrote:
> On Wed, Oct 31, 2012 at 01:20:23PM -0700, Jesse Barnes wrote:
> > On Wed, 31 Oct 2012 17:50:14 +0200
> > ville.syrjala@linux.intel.com wrote:
> >
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Fix support for all RGB/BGR pixel formats (except the 16:16:16:16 float
> > > format).
> > >
> > > Fix intel_init_framebuffer() to match hardware and driver limitations:
> > > * RGB332 is not supported at all
> > > * CI8 is supported
> > > * XRGB1555 & co. are supported on Gen3 and earlier
> > > * XRGB210101010 & co. are supported from Gen4 onwards
> > > * BGR formats are supported from Gen4 onwards
> > > * YUV formats are supported from Gen5 onwards (driver limitation)
> >
> > Yeah looks nice. I love how our definitions have the component order
> > reversed relative to the fourcc-ish codes.
>
> Yeah. I just copied the names more or less blindly from the spec. I
> usually prefer to keep register definitons and specs in sync, since
> it makes it easier to search for stuff in the spec. But if people
> are bothered by this mess, I won't object to changing the defns to
> match the fourcc stuff.
We have the same issue in userspace, where we follow the spec counter to
the common convention. It is just one of those things you get used to.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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next prev parent reply other threads:[~2012-11-01 14:07 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2012-10-31 15:50 [PATCH 00/11] drm/i915: Patches cherry-picked from drm_atomic ville.syrjala
2012-10-31 15:50 ` [PATCH 01/11] drm/i915: Fix display pixel format handling ville.syrjala
2012-10-31 20:20 ` Jesse Barnes
2012-11-01 14:03 ` Ville Syrjälä
2012-11-01 14:06 ` Chris Wilson [this message]
2012-10-31 15:50 ` [PATCH 02/11] drm/i915: Add SURFLIVE register definitions ville.syrjala
2012-10-31 20:23 ` Jesse Barnes
2012-10-31 22:57 ` Daniel Vetter
2012-11-01 14:16 ` Ville Syrjälä
2012-11-01 14:19 ` Daniel Vetter
2012-11-01 14:23 ` Ville Syrjälä
2012-10-31 15:50 ` [PATCH 03/11] drm/i915: Implement execbuffer wait for all planes ville.syrjala
2012-10-31 15:59 ` Chris Wilson
2012-10-31 15:50 ` [PATCH 04/11] drm/i915: Factor out i9xx_compute_clocks() like ironlake_compute_clocks() ville.syrjala
2012-10-31 16:28 ` Daniel Vetter
2012-10-31 17:04 ` Ville Syrjälä
2012-10-31 18:29 ` Daniel Vetter
2012-10-31 15:50 ` [PATCH 05/11] drm/i915: Check framebuffer stride more thoroughly ville.syrjala
2012-10-31 20:25 ` Jesse Barnes
2012-11-01 14:06 ` Ville Syrjälä
2012-10-31 15:50 ` [PATCH 06/11] drm/i915: Check the framebuffer offset ville.syrjala
2012-10-31 20:26 ` Jesse Barnes
2012-11-01 14:09 ` Ville Syrjälä
2012-11-01 14:18 ` Daniel Vetter
2012-11-01 14:40 ` Jesse Barnes
2012-11-01 14:40 ` Ville Syrjälä
2012-10-31 15:50 ` [PATCH 07/11] drm/i915: pixel_size == cpp ville.syrjala
2012-10-31 20:27 ` Jesse Barnes
2012-10-31 15:50 ` [PATCH 08/11] drm/i915: Bad pixel formats can't reach the sprite code ville.syrjala
2012-10-31 20:27 ` Jesse Barnes
2012-10-31 15:50 ` [PATCH 09/11] drm/i915: Consitify adjusted_mode parameter ville.syrjala
2012-10-31 15:50 ` [PATCH 10/11] drm/i915: Constify mode argument to intel_modeset_adjusted_mode() ville.syrjala
2012-10-31 15:50 ` [PATCH 11/11] drm/i915: Introduce intel_crtc_update_sarea_pos() ville.syrjala
2012-10-31 20:27 ` Jesse Barnes
2012-10-31 23:02 ` Daniel Vetter
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