From: Lionel Landwerlin <lionel.g.landwerlin@linux.intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>,
"Robert Bragg" <robert@sixbynine.org>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3 6/7] drm/i915/perf: per-gen timebase for checking sample freq
Date: Wed, 5 Apr 2017 18:17:36 +0100 [thread overview]
Message-ID: <493dc7dc-c7b4-6cf4-780c-7fe7364f1b1d@linux.intel.com> (raw)
In-Reply-To: <20170405170617.GS30290@intel.com>
On 05/04/17 18:06, Ville Syrjälä wrote:
> On Wed, Apr 05, 2017 at 05:23:19PM +0100, Robert Bragg wrote:
>> An oa_exponent_to_ns() utility and per-gen timebase constants where
>> recently removed when updating the tail pointer race condition WA, and
>> this restores those so we can update the _PROP_OA_EXPONENT validation
>> done in read_properties_unlocked() to not assume we have a 12.5KHz
>> timebase as we did for Haswell.
>>
>> Signed-off-by: Robert Bragg <robert@sixbynine.org>
>> Cc: Lionel Landwerlin <lionel.g.landwerlin@linux.intel.com>
>> ---
>> drivers/gpu/drm/i915/i915_drv.h | 1 +
>> drivers/gpu/drm/i915/i915_perf.c | 21 +++++++++++++++------
>> 2 files changed, 16 insertions(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 3a22b6fd0ee6..48b07d706f06 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -2463,6 +2463,7 @@ struct drm_i915_private {
>>
>> bool periodic;
>> int period_exponent;
>> + int timestamp_frequency;
>>
>> int metrics_set;
>>
>> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
>> index 98eb6415b63a..87c0d1ce1b9f 100644
>> --- a/drivers/gpu/drm/i915/i915_perf.c
>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>> @@ -2549,6 +2549,12 @@ i915_perf_open_ioctl_locked(struct drm_i915_private *dev_priv,
>> return ret;
>> }
>>
>> +static u64 oa_exponent_to_ns(struct drm_i915_private *dev_priv, int exponent)
>> +{
>> + return div_u64(1000000000ULL * (2ULL << exponent),
>> + dev_priv->perf.oa.timestamp_frequency);
>> +}
>> +
>> /**
>> * read_properties_unlocked - validate + copy userspace stream open properties
>> * @dev_priv: i915 device instance
>> @@ -2647,14 +2653,9 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv,
>> /* Theoretically we can program the OA unit to sample
>> * every 160ns but don't allow that by default unless
>> * root.
>> - *
>> - * On Haswell the period is derived from the exponent
>> - * as:
>> - *
>> - * period = 80ns * 2^(exponent + 1)
>> */
>> BUILD_BUG_ON(sizeof(oa_period) != 8);
>> - oa_period = 80ull * (2ull << value);
>> + oa_period = oa_exponent_to_ns(dev_priv, value);
>>
>> /* This check is primarily to ensure that oa_period <=
>> * UINT32_MAX (before passing to do_div which only
>> @@ -2910,6 +2911,8 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
>> dev_priv->perf.oa.ops.oa_hw_tail_read =
>> gen7_oa_hw_tail_read;
>>
>> + dev_priv->perf.oa.timestamp_frequency = 12500000;
>> +
>> dev_priv->perf.oa.oa_formats = hsw_oa_formats;
>>
>> dev_priv->perf.oa.n_builtin_sets =
>> @@ -2923,6 +2926,8 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
>> */
>>
>> if (IS_GEN8(dev_priv)) {
>> + dev_priv->perf.oa.timestamp_frequency = 12500000;
>> +
>> dev_priv->perf.oa.ctx_oactxctrl_offset = 0x120;
>> dev_priv->perf.oa.ctx_flexeu0_offset = 0x2ce;
>> dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<25);
>> @@ -2939,6 +2944,8 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
>> i915_oa_select_metric_set_chv;
>> }
>> } else if (IS_GEN9(dev_priv)) {
>> + dev_priv->perf.oa.timestamp_frequency = 12000000;
>> +
>> dev_priv->perf.oa.ctx_oactxctrl_offset = 0x128;
>> dev_priv->perf.oa.ctx_flexeu0_offset = 0x3de;
>> dev_priv->perf.oa.gen8_valid_ctx_bit = (1<<16);
>> @@ -2959,6 +2966,8 @@ void i915_perf_init(struct drm_i915_private *dev_priv)
>> dev_priv->perf.oa.ops.select_metric_set =
>> i915_oa_select_metric_set_sklgt4;
>> } else if (IS_BROXTON(dev_priv)) {
>> + dev_priv->perf.oa.timestamp_frequency = 19200123;
>> +
> Why isn't this exactly 19.2MHz?
It's based off the timestamp base (from documentation) :
BDW: 80ns
SKL: 83.333ns
BXT: 52.083ns
1000000000 / 19200123 is the closest we can get.
>
>> dev_priv->perf.oa.n_builtin_sets =
>> i915_oa_n_builtin_metric_sets_bxt;
>> dev_priv->perf.oa.ops.select_metric_set =
>> --
>> 2.12.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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next prev parent reply other threads:[~2017-04-05 17:17 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-04-05 16:23 [PATCH v3 0/7] Enable OA unit for Gen 8 and 9 in i915 perf Robert Bragg
2017-04-05 16:23 ` [PATCH v3 1/7] drm/i915: expose _SLICE_MASK GETPARM Robert Bragg
2017-04-05 16:23 ` [PATCH v3 2/7] drm/i915: expose _SUBSLICE_MASK GETPARM Robert Bragg
2017-04-05 16:23 ` [PATCH v3 3/7] drm/i915/perf: Add 'render basic' Gen8+ OA unit configs Robert Bragg
2017-04-05 16:23 ` [PATCH v3 4/7] drm/i915/perf: Add OA unit support for Gen 8+ Robert Bragg
2017-04-06 16:56 ` Lionel Landwerlin
2017-04-12 11:33 ` Matthew Auld
2017-04-12 14:57 ` Robert Bragg
2017-04-05 16:23 ` [PATCH v3 5/7] drm/i915/perf: Add more OA configs for BDW, CHV, SKL + BXT Robert Bragg
2017-04-05 16:23 ` [PATCH v3 6/7] drm/i915/perf: per-gen timebase for checking sample freq Robert Bragg
2017-04-05 16:49 ` Lionel Landwerlin
2017-04-05 17:06 ` Ville Syrjälä
2017-04-05 17:17 ` Lionel Landwerlin [this message]
2017-04-05 17:26 ` Ville Syrjälä
2017-04-05 17:59 ` Robert Bragg
2017-04-05 19:05 ` [PATCH v2] " Robert Bragg
2017-04-12 12:34 ` Matthew Auld
2017-04-12 15:07 ` Robert Bragg
2017-04-05 16:23 ` [PATCH v3 7/7] drm/i915/perf: remove perf.hook_lock Robert Bragg
2017-04-12 11:36 ` Matthew Auld
2017-04-05 16:42 ` ✓ Fi.CI.BAT: success for Enable OA unit for Gen 8 and 9 in i915 perf (rev4) Patchwork
2017-04-05 19:21 ` ✓ Fi.CI.BAT: success for Enable OA unit for Gen 8 and 9 in i915 perf (rev5) Patchwork
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