Re: [Intel-gfx] [PATCH 1/4] drm/i915: Fix GEN9 HDCP1.4 key load process

From: "C, Ramalingam" <ramalingam.c@intel.com>
To: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Cc: daniel.vetter@ffwll.ch, intel-gfx@lists.freedesktop.org,
	seanpaul@chromium.org, dri-devel@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 1/4] drm/i915: Fix GEN9 HDCP1.4 key load process
Date: Tue, 27 Nov 2018 21:57:02 +0530	[thread overview]
Message-ID: <4b7fff81-7b55-34d4-e523-a4089e95b96b@intel.com> (raw)
In-Reply-To: <20181127151545.GZ9144@intel.com>

[-- Attachment #1.1: Type: text/plain, Size: 2190 bytes --]

On 11/27/2018 8:45 PM, Ville Syrjälä wrote:
> On Tue, Nov 27, 2018 at 07:32:56PM +0530, Ramalingam C wrote:
>> HDCP1.4 key load process varies between Intel platform to platform.
>>
>> For Gen9 platforms except BXT and GLK, HDCP1.4 key is loaded using
>> the GT Driver Mailbox interface. Instead of listing all the platforms
>> for this method, adopted this method for all Gen9 platforms with
>> exceptions. In this way we need not extent check for new GEN9 platforms
>> like CFL.
>>
>> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
>> ---
>>   drivers/gpu/drm/i915/intel_hdcp.c | 8 +++++---
>>   1 file changed, 5 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
>> index 1bf487f94254..beacfbb6e5e1 100644
>> --- a/drivers/gpu/drm/i915/intel_hdcp.c
>> +++ b/drivers/gpu/drm/i915/intel_hdcp.c
>> @@ -157,10 +157,12 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
>>   	/*
>>   	 * Initiate loading the HDCP key from fuses.
>>   	 *
>> -	 * BXT+ platforms, HDCP key needs to be loaded by SW. Only SKL and KBL
>> -	 * differ in the key load trigger process from other platforms.
>> +	 * BXT+ platforms, HDCP key needs to be loaded by SW. Only Gen 9
>> +	 * platforms except BXT and GLK, differ in the key load trigger process
>> +	 * from other platforms.
>>   	 */
>> -	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
>> +	if (IS_GEN9(dev_priv) &&
>> +	    (!IS_BROXTON(dev_priv) && !IS_GEMINILAKE(dev_priv))) {
> IS_GEN9_BC()

Bspec doesn't state anything about BC/LP. They have mentioned GEN9+ with BXT, CNL, ICL excluded.
So I am inferring that this method is only for Gen9 excluding BXT and GLK (verified).

Remaining platforms are SKL, KBL, and CFL.
IS_GEN9_BC() will filter them easily. unless we find otherwise, we can use this. Thanks Ville.

--Ram

>
>>   		mutex_lock(&dev_priv->pcu_lock);
>>   		ret = sandybridge_pcode_write(dev_priv,
>>   					      SKL_PCODE_LOAD_HDCP_KEYS, 1);
>> -- 
>> 2.7.4
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[-- Attachment #1.2: Type: text/html, Size: 3172 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel