From: "Souza, Jose" <jose.souza@intel.com>
To: "Intel-gfx@lists.freedesktop.org"
<Intel-gfx@lists.freedesktop.org>,
"Hogander, Jouni" <jouni.hogander@intel.com>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/psr: Remove inappropriate DSC slice alignment warning
Date: Tue, 1 Nov 2022 21:02:43 +0000 [thread overview]
Message-ID: <51ebcaea9c2d4a8a691ae4f473f20ba6e0599ce6.camel@intel.com> (raw)
In-Reply-To: <7fd6c03e88471339440401126043e7422df9a9c7.camel@intel.com>
On Tue, 2022-11-01 at 20:55 +0000, Hogander, Jouni wrote:
> On Tue, 2022-11-01 at 20:00 +0000, Souza, Jose wrote:
> > On Fri, 2022-10-21 at 08:49 +0300, Jouni Högander wrote:
> > > Selective update area is now aligned with DSC slice height when
> > > DSC is enabled. Remove inappropriate warning about missing DSC
> > > alignment.
> > >
> > > Cc: José Roberto de Souza <jose.souza@intel.com>
> > > Cc: Mika Kahola <mika.kahola@intel.com>
> > >
> > > Fixes: 47d4ae2192cb ("drm/i915/mtl: Extend PSR support")
> > > Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/7212
> > > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_psr.c | 3 ---
> > > 1 file changed, 3 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > > b/drivers/gpu/drm/i915/display/intel_psr.c
> > > index 904a1049eff3..64e9e134fdca 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > > @@ -1678,9 +1678,6 @@ static void
> > > intel_psr2_sel_fetch_pipe_alignment(const struct intel_crtc_state
> > > *c
> > > pipe_clip->y1 -= pipe_clip->y1 % y_alignment;
> > > if (pipe_clip->y2 % y_alignment)
> > > pipe_clip->y2 = ((pipe_clip->y2 / y_alignment) + 1)
> > > * y_alignment;
> > > -
> > > - if (IS_ALDERLAKE_P(dev_priv) && crtc_state-
> > > > dsc.compression_enable)
> > > - drm_warn(&dev_priv->drm, "Missing PSR2 sel fetch
> > > alignment with DSC\n");
> >
> > It is necessary check if DSC alignment and PSR2 alignment matches, if
> > not PSR2 can't be enabled.
>
> This check is there at the begin of
> intel_psr2_sel_fetch_pipe_alignment:
>
> /* ADLP aligns the SU region to vdsc slice height in case dsc is
> enabled */
> if (crtc_state->dsc.compression_enable &&
> (IS_ALDERLAKE_P(dev_priv) || DISPLAY_VER(dev_priv) >= 14))
> y_alignment = vdsc_cfg->slice_height;
This is still wrong.
There is no guarantee that required PSR2 alignment matches vdsc_cfg->slice_height.
>
> For some reason when this got merged warning was still left there. Now
> just removing the warning as well.
>
> >
> > > }
> > >
> > > /*
> >
>
next prev parent reply other threads:[~2022-11-01 21:03 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-21 5:49 [Intel-gfx] [PATCH] drm/i915/psr: Remove inappropriate DSC slice alignment warning Jouni Högander
2022-10-21 7:36 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2022-10-21 8:17 ` [Intel-gfx] [PATCH] " Kahola, Mika
2022-10-21 11:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure for " Patchwork
2022-10-24 15:34 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
2022-11-01 20:00 ` [Intel-gfx] [PATCH] " Souza, Jose
2022-11-01 20:55 ` Hogander, Jouni
2022-11-01 21:02 ` Souza, Jose [this message]
2022-11-02 17:48 ` Hogander, Jouni
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