From: "Souza, Jose" <jose.souza@intel.com>
To: "Vivi, Rodrigo" <rodrigo.vivi@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Cc: "De Marchi, Lucas" <lucas.demarchi@intel.com>
Subject: Re: [PATCH 7/9] drm/i915/ehl: Set proper eu slice/subslice parameters for EHL
Date: Thu, 14 Mar 2019 21:40:26 +0000 [thread overview]
Message-ID: <521a3cfb31977c213c118451663cde7eee47896d.camel@intel.com> (raw)
In-Reply-To: <20190313211144.4842-7-rodrigo.vivi@intel.com>
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On Wed, 2019-03-13 at 14:11 -0700, Rodrigo Vivi wrote:
> From: Bob Paauwe <bob.j.paauwe@intel.com>
>
> EHL has a different number of subslices.
>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Signed-off-by: Bob Paauwe <bob.j.paauwe@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_device_info.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c
> b/drivers/gpu/drm/i915/intel_device_info.c
> index c8c0f4134bdb..31411f1cdbb4 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -156,9 +156,15 @@ static void gen11_sseu_info_init(struct
> drm_i915_private *dev_priv)
> u8 eu_en;
> int s;
>
> - sseu->max_slices = 1;
> - sseu->max_subslices = 8;
> - sseu->max_eus_per_subslice = 8;
> + if (IS_ELKHARTLAKE(dev_priv)) {
> + sseu->max_slices = 1;
> + sseu->max_subslices = 4;
> + sseu->max_eus_per_subslice = 8;
> + } else {
> + sseu->max_slices = 1;
> + sseu->max_subslices = 8;
> + sseu->max_eus_per_subslice = 8;
> + }
>
> s_en = I915_READ(GEN11_GT_SLICE_ENABLE) & GEN11_GT_S_ENA_MASK;
> ss_en = ~I915_READ(GEN11_GT_SUBSLICE_DISABLE);
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next prev parent reply other threads:[~2019-03-14 21:40 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-03-13 21:11 [PATCH 1/9] drm/i915/ehl: Add EHL platform info and PCI IDs Rodrigo Vivi
2019-03-13 21:11 ` [PATCH 2/9] drm/i915/ehl: Add ElkhartLake platform Rodrigo Vivi
2019-03-14 20:45 ` Souza, Jose
2019-03-14 22:53 ` Lucas De Marchi
2019-03-13 21:11 ` [PATCH 3/9] drm/i915/ehl: ehl and icl are both gen11 Rodrigo Vivi
2019-03-14 21:11 ` Souza, Jose
2019-04-05 0:38 ` Lucas De Marchi
2019-03-14 22:59 ` Lucas De Marchi
2019-03-13 21:11 ` [PATCH 4/9] drm/i915/ehl: Add dpll mgr Rodrigo Vivi
2019-03-14 21:38 ` Souza, Jose
2019-03-13 21:11 ` [PATCH 5/9] drm/i915/ehl: All EHL ports are combo phys Rodrigo Vivi
2019-03-14 20:27 ` Souza, Jose
2019-03-14 23:00 ` Lucas De Marchi
2019-03-20 21:15 ` [PATCH] drm/i915/ehl: All EHL ports are combo phys (v2) Bob Paauwe
2019-03-20 21:20 ` Souza, Jose
2019-04-02 22:17 ` Lucas De Marchi
2019-03-21 8:09 ` kbuild test robot
2019-03-21 8:37 ` kbuild test robot
2019-03-13 21:11 ` [PATCH 6/9] drm/i915/ehl: EHL outputs are different from ICL Rodrigo Vivi
2019-03-14 21:39 ` Souza, Jose
2019-03-14 23:19 ` Lucas De Marchi
2019-03-13 21:11 ` [PATCH 7/9] drm/i915/ehl: Set proper eu slice/subslice parameters for EHL Rodrigo Vivi
2019-03-14 21:40 ` Souza, Jose [this message]
2019-03-14 23:22 ` Lucas De Marchi
2019-03-13 21:11 ` [PATCH 8/9] drm/i915/ehl: ehl has only 36bit extended ppgtt support Rodrigo Vivi
2019-03-14 7:34 ` Chris Wilson
2019-03-13 21:11 ` [PATCH 9/9] drm/i915/ehl: Add Support for DMC on EHL Rodrigo Vivi
2019-03-14 21:49 ` Souza, Jose
2019-03-14 23:29 ` Lucas De Marchi
2019-03-14 2:24 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs Patchwork
2019-03-14 2:28 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-03-14 3:07 ` ✓ Fi.CI.BAT: success " Patchwork
2019-03-14 9:30 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-03-14 20:43 ` [PATCH 1/9] " Souza, Jose
2019-03-14 21:34 ` ✗ Fi.CI.BAT: failure for series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs (rev2) Patchwork
2019-03-20 23:10 ` ✗ Fi.CI.BAT: failure for series starting with [1/9] drm/i915/ehl: Add EHL platform info and PCI IDs (rev3) Patchwork
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