[PATCH 0/5] PSR/PR Selective Fetch Early Transport fixes

[PATCH 0/5] PSR/PR Selective Fetch Early Transport fixes

[Jouni Högander]

This patch set contains fixes for Selective Fetch Early Transport configuration:

  - add necessary DSC Early Transport configuration
  - corner case fix for Selective Update area when Early Transport is
    in use and cursor plane is included into SU are due to alignment.
  - remove useless parameter from intel_psr2_sel_fetch_et_alignment

Jouni Högander (5):
  drm/i915/psr: Repeat Selective Update area alignment
  drm/i915/psr: Add DSC_SU_PARAMETER_SET_0 registers for PSR
    configuration
  drm/i915/dsc: Convert intel_dsc_get_vdsc_per_pipe as non-static
  drm/i915/psr: DSC configuration for Early Transport
  drm/i915/psr: Drop cursor_in_su_area from
    intel_psr2_sel_fetch_et_alignment

 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 63 ++++++++++++++-----
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 12 ++++
 drivers/gpu/drm/i915/display/intel_vdsc.c     |  2 +-
 drivers/gpu/drm/i915/display/intel_vdsc.h     |  1 +
 5 files changed, 62 insertions(+), 17 deletions(-)

-- 
2.43.0

[PATCH 1/5] drm/i915/psr: Repeat Selective Update area alignment

[Jouni Högander]

Currently we are aligning Selective Update area to cover cursor fully if
needed only once. It may happen that cursor is in Selective Update area
after pipe alignment and after that covering cursor plane only
partially. Fix this by looping alignment as long as alignment isn't needed
anymore.

Fixes: 1bff93b8bc27 ("drm/i915/psr: Extend SU area to cover cursor fully if needed")
Cc: <stable@vger.kernel.org> # v6.9+
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 32 ++++++++++++++++--------
 1 file changed, 21 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 5bea2eda744b..331645a2c9f6 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2688,11 +2688,12 @@ static void clip_area_update(struct drm_rect *overlap_damage_area,
 		overlap_damage_area->y2 = damage_area->y2;
 }
 
-static void intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_state)
+static bool intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_state)
 {
 	struct intel_display *display = to_intel_display(crtc_state);
 	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
 	u16 y_alignment;
+	bool aligned = false;
 
 	/* ADLP aligns the SU region to vdsc slice height in case dsc is enabled */
 	if (crtc_state->dsc.compression_enable &&
@@ -2701,10 +2702,18 @@ static void intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_st
 	else
 		y_alignment = crtc_state->su_y_granularity;
 
-	crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1 % y_alignment;
-	if (crtc_state->psr2_su_area.y2 % y_alignment)
+	if (crtc_state->psr2_su_area.y1 % y_alignment) {
+		crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1 % y_alignment;
+		aligned = true;
+	}
+
+	if (crtc_state->psr2_su_area.y2 % y_alignment) {
 		crtc_state->psr2_su_area.y2 = ((crtc_state->psr2_su_area.y2 /
 						y_alignment) + 1) * y_alignment;
+		aligned = true;
+	}
+
+	return aligned;
 }
 
 /*
@@ -2945,15 +2954,16 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 	if (ret)
 		return ret;
 
-	/*
-	 * Adjust su area to cover cursor fully as necessary (early
-	 * transport). This needs to be done after
-	 * drm_atomic_add_affected_planes to ensure visible cursor is added into
-	 * affected planes even when cursor is not updated by itself.
-	 */
-	intel_psr2_sel_fetch_et_alignment(state, crtc, &cursor_in_su_area);
+	do {
+		/*
+		 * Adjust su area to cover cursor fully as necessary (early
+		 * transport). This needs to be done after
+		 * drm_atomic_add_affected_planes to ensure visible cursor is added into
+		 * affected planes even when cursor is not updated by itself.
+		 */
+		intel_psr2_sel_fetch_et_alignment(state, crtc, &cursor_in_su_area);
 
-	intel_psr2_sel_fetch_pipe_alignment(crtc_state);
+	} while (intel_psr2_sel_fetch_pipe_alignment(crtc_state));
 
 	/*
 	 * Now that we have the pipe damaged area check if it intersect with
-- 
2.43.0

Re: [PATCH 1/5] drm/i915/psr: Repeat Selective Update area alignment

[Nautiyal, Ankit K]

On 2/19/2026 6:37 PM, Jouni Högander wrote:
> Currently we are aligning Selective Update area to cover cursor fully if
> needed only once. It may happen that cursor is in Selective Update area
> after pipe alignment and after that covering cursor plane only
> partially. Fix this by looping alignment as long as alignment isn't needed
> anymore.

If I understand correctly, intel_psr2_sel_fetch_et_alignment() tries to 
expand the current su area so that it includes the cursor if it was 
partially covered.

Then the intel_psr2_sel_fetch_pipe_alignment() tries to expand the su 
area to align with the slice height/y granularity.

Hence it is possible that after aligning the area with the slice 
height/y granularity, the cursor which might have been outside the su 
area, has now become partially inside the su area.

So the iteration makes sense. However there are couple of things:

- if the cursor was already inside the su area, then even after pipe 
alignment which expands the su area (y1 decreases goes vertically up and 
y2 increases goes vertically down) the cursor will still be inside the 
su area.

  In that case we dont need to do another iteration we can exit the loop.

- cursor_in_su_area is set and never used.


Perhaps we can change the loop a bit like:

bool su_area_changed;
.....
do {
     bool cursor_in_su_area = false;

     intel_psr2_sel_fetch_et_alignment(state, crtc, 
&cursor_in_su_area);     // Cursor is now either fully inside su area OR 
fully outside.
     su_area_changed = intel_psr2_sel_fetch_pipe_alignment(crtc_state);  
   // Alignment increased the su area.

/*
  * If the cursor was outside the SU area before alignment, the 
alignment step
  * (which only expands SU) may pull the cursor partially inside, so we must
  * run ET alignment again to fully cover it.
  *
  * But if the cursor was already fully inside before alignment, 
expanding the
  * SU area won't change that, so no further work is needed.
  */
     if (cursor_in_su_area)
         break;
} while (su_area_changed);



>
> Fixes: 1bff93b8bc27 ("drm/i915/psr: Extend SU area to cover cursor fully if needed")
> Cc: <stable@vger.kernel.org> # v6.9+
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_psr.c | 32 ++++++++++++++++--------
>   1 file changed, 21 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 5bea2eda744b..331645a2c9f6 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2688,11 +2688,12 @@ static void clip_area_update(struct drm_rect *overlap_damage_area,
>   		overlap_damage_area->y2 = damage_area->y2;
>   }
>   
> -static void intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_state)
> +static bool intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_display *display = to_intel_display(crtc_state);
>   	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
>   	u16 y_alignment;
> +	bool aligned = false;


Here also it would make sense if we make this su_area_changed. (ofcourse 
after alignment)

Hope I am making some sense and not totally off.

Regards,

Ankit


>   
>   	/* ADLP aligns the SU region to vdsc slice height in case dsc is enabled */
>   	if (crtc_state->dsc.compression_enable &&
> @@ -2701,10 +2702,18 @@ static void intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_st
>   	else
>   		y_alignment = crtc_state->su_y_granularity;
>   
> -	crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1 % y_alignment;
> -	if (crtc_state->psr2_su_area.y2 % y_alignment)
> +	if (crtc_state->psr2_su_area.y1 % y_alignment) {
> +		crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1 % y_alignment;
> +		aligned = true;
> +	}
> +
> +	if (crtc_state->psr2_su_area.y2 % y_alignment) {
>   		crtc_state->psr2_su_area.y2 = ((crtc_state->psr2_su_area.y2 /
>   						y_alignment) + 1) * y_alignment;
> +		aligned = true;
> +	}
> +
> +	return aligned;
>   }
>   
>   /*
> @@ -2945,15 +2954,16 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>   	if (ret)
>   		return ret;
>   
> -	/*
> -	 * Adjust su area to cover cursor fully as necessary (early
> -	 * transport). This needs to be done after
> -	 * drm_atomic_add_affected_planes to ensure visible cursor is added into
> -	 * affected planes even when cursor is not updated by itself.
> -	 */
> -	intel_psr2_sel_fetch_et_alignment(state, crtc, &cursor_in_su_area);
> +	do {
> +		/*
> +		 * Adjust su area to cover cursor fully as necessary (early
> +		 * transport). This needs to be done after
> +		 * drm_atomic_add_affected_planes to ensure visible cursor is added into
> +		 * affected planes even when cursor is not updated by itself.
> +		 */
> +		intel_psr2_sel_fetch_et_alignment(state, crtc, &cursor_in_su_area);
>   
> -	intel_psr2_sel_fetch_pipe_alignment(crtc_state);
> +	} while (intel_psr2_sel_fetch_pipe_alignment(crtc_state));
>   
>   	/*
>   	 * Now that we have the pipe damaged area check if it intersect with

Re: [PATCH 1/5] drm/i915/psr: Repeat Selective Update area alignment

[Hogander, Jouni]

On Wed, 2026-02-25 at 09:43 +0530, Nautiyal, Ankit K wrote:
> 
> On 2/19/2026 6:37 PM, Jouni Högander wrote:
> > Currently we are aligning Selective Update area to cover cursor
> > fully if
> > needed only once. It may happen that cursor is in Selective Update
> > area
> > after pipe alignment and after that covering cursor plane only
> > partially. Fix this by looping alignment as long as alignment isn't
> > needed
> > anymore.
> 
> If I understand correctly, intel_psr2_sel_fetch_et_alignment() tries
> to 
> expand the current su area so that it includes the cursor if it was 
> partially covered.
> 
> Then the intel_psr2_sel_fetch_pipe_alignment() tries to expand the su
> area to align with the slice height/y granularity.
> 
> Hence it is possible that after aligning the area with the slice 
> height/y granularity, the cursor which might have been outside the su
> area, has now become partially inside the su area.
> 
> So the iteration makes sense. However there are couple of things:
> 
> - if the cursor was already inside the su area, then even after pipe 
> alignment which expands the su area (y1 decreases goes vertically up
> and 
> y2 increases goes vertically down) the cursor will still be inside
> the 
> su area.
> 
>   In that case we dont need to do another iteration we can exit the
> loop.
> 
> - cursor_in_su_area is set and never used.
> 
> 
> Perhaps we can change the loop a bit like:
> 
> bool su_area_changed;
> .....
> do {
>      bool cursor_in_su_area = false;
> 
>      intel_psr2_sel_fetch_et_alignment(state, crtc, 
> &cursor_in_su_area);     // Cursor is now either fully inside su area
> OR 
> fully outside.
>      su_area_changed =
> intel_psr2_sel_fetch_pipe_alignment(crtc_state);  
>    // Alignment increased the su area.
> 
> /*
>   * If the cursor was outside the SU area before alignment, the 
> alignment step
>   * (which only expands SU) may pull the cursor partially inside, so
> we must
>   * run ET alignment again to fully cover it.
>   *
>   * But if the cursor was already fully inside before alignment, 
> expanding the
>   * SU area won't change that, so no further work is needed.
>   */
>      if (cursor_in_su_area)
>          break;
> } while (su_area_changed);
> 
> 
> 
> > 
> > Fixes: 1bff93b8bc27 ("drm/i915/psr: Extend SU area to cover cursor
> > fully if needed")
> > Cc: <stable@vger.kernel.org> # v6.9+
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_psr.c | 32 ++++++++++++++++---
> > -----
> >   1 file changed, 21 insertions(+), 11 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 5bea2eda744b..331645a2c9f6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -2688,11 +2688,12 @@ static void clip_area_update(struct
> > drm_rect *overlap_damage_area,
> >   		overlap_damage_area->y2 = damage_area->y2;
> >   }
> >   
> > -static void intel_psr2_sel_fetch_pipe_alignment(struct
> > intel_crtc_state *crtc_state)
> > +static bool intel_psr2_sel_fetch_pipe_alignment(struct
> > intel_crtc_state *crtc_state)
> >   {
> >   	struct intel_display *display =
> > to_intel_display(crtc_state);
> >   	const struct drm_dsc_config *vdsc_cfg = &crtc_state-
> > >dsc.config;
> >   	u16 y_alignment;
> > +	bool aligned = false;
> 
> 
> Here also it would make sense if we make this su_area_changed.
> (ofcourse 
> after alignment)
> 
> Hope I am making some sense and not totally off.

Yes, you are making good suggestions here. I will rework the loop and
change this as well. Thank you.

BR,
Jouni Högander

> 
> Regards,
> 
> Ankit
> 
> 
> >   
> >   	/* ADLP aligns the SU region to vdsc slice height in case
> > dsc is enabled */
> >   	if (crtc_state->dsc.compression_enable &&
> > @@ -2701,10 +2702,18 @@ static void
> > intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state
> > *crtc_st
> >   	else
> >   		y_alignment = crtc_state->su_y_granularity;
> >   
> > -	crtc_state->psr2_su_area.y1 -= crtc_state->psr2_su_area.y1
> > % y_alignment;
> > -	if (crtc_state->psr2_su_area.y2 % y_alignment)
> > +	if (crtc_state->psr2_su_area.y1 % y_alignment) {
> > +		crtc_state->psr2_su_area.y1 -= crtc_state-
> > >psr2_su_area.y1 % y_alignment;
> > +		aligned = true;
> > +	}
> > +
> > +	if (crtc_state->psr2_su_area.y2 % y_alignment) {
> >   		crtc_state->psr2_su_area.y2 = ((crtc_state-
> > >psr2_su_area.y2 /
> >   						y_alignment) + 1)
> > * y_alignment;
> > +		aligned = true;
> > +	}
> > +
> > +	return aligned;
> >   }
> >   
> >   /*
> > @@ -2945,15 +2954,16 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >   	if (ret)
> >   		return ret;
> >   
> > -	/*
> > -	 * Adjust su area to cover cursor fully as necessary
> > (early
> > -	 * transport). This needs to be done after
> > -	 * drm_atomic_add_affected_planes to ensure visible cursor
> > is added into
> > -	 * affected planes even when cursor is not updated by
> > itself.
> > -	 */
> > -	intel_psr2_sel_fetch_et_alignment(state, crtc,
> > &cursor_in_su_area);
> > +	do {
> > +		/*
> > +		 * Adjust su area to cover cursor fully as
> > necessary (early
> > +		 * transport). This needs to be done after
> > +		 * drm_atomic_add_affected_planes to ensure
> > visible cursor is added into
> > +		 * affected planes even when cursor is not updated
> > by itself.
> > +		 */
> > +		intel_psr2_sel_fetch_et_alignment(state, crtc,
> > &cursor_in_su_area);
> >   
> > -	intel_psr2_sel_fetch_pipe_alignment(crtc_state);
> > +	} while (intel_psr2_sel_fetch_pipe_alignment(crtc_state));
> >   
> >   	/*
> >   	 * Now that we have the pipe damaged area check if it
> > intersect with

[PATCH 2/5] drm/i915/psr: Add DSC_SU_PARAMETER_SET_0 registers for PSR configuration

[Jouni Högander]

Add DSC_SU_PARAMETER_SET_0_DSC0 and DSC_SU_PARAMETER_SET_0_DSC1 register
definitions for Selective Update Early Transport configuration.

Bspec: 71709
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr_regs.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 8afbf5a38335..3d1523dece8b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -266,6 +266,18 @@
 #define _PIPE_SRCSZ_ERLY_TPT_B	0x71074
 #define PIPE_SRCSZ_ERLY_TPT(pipe)	_MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B)
 
+#define _DSC_SU_PARAMETER_SET_0_DSC0_A		0x78064
+#define _DSC_SU_PARAMETER_SET_0_DSC0_B		0x78264
+#define DSC_SU_PARAMETER_SET_0_DSC0(pipe)	_MMIO_PIPE((pipe), _DSC_SU_PARAMETER_SET_0_DSC0_A, _DSC_SU_PARAMETER_SET_0_DSC0_B)
+#define   DSC_SU_PARAMETER_SET_0_SU_SLICE_ROW_PER_FRAME_MASK	REG_GENMASK(31, 20)
+#define   DSC_SU_PARAMETER_SET_0_SU_SLICE_ROW_PER_FRAME(rows)	REG_FIELD_PREP(DSC_SU_PARAMETER_SET_0_SU_SLICE_ROW_PER_FRAME_MASK, (rows))
+#define   DSC_SU_PARAMETER_SET_0_SU_PIC_HEIGHT_MASK		REG_GENMASK(15, 0)
+#define   DSC_SU_PARAMETER_SET_0_SU_PIC_HEIGHT(h)		REG_FIELD_PREP(DSC_SU_PARAMETER_SET_0_SU_PIC_HEIGHT_MASK, (h))
+
+#define _DSC_SU_PARAMETER_SET_0_DSC1_A		0x78164
+#define _DSC_SU_PARAMETER_SET_0_DSC1_B		0x78364
+#define DSC_SU_PARAMETER_SET_0_DSC1(pipe)	_MMIO_PIPE((pipe), _DSC_SU_PARAMETER_SET_0_DSC1_A, _DSC_SU_PARAMETER_SET_0_DSC1_B)
+
 #define _PR_ALPM_CTL_A	0x60948
 #define PR_ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _PR_ALPM_CTL_A)
 #define  PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU	BIT(6)
-- 
2.43.0

Re: [PATCH 2/5] drm/i915/psr: Add DSC_SU_PARAMETER_SET_0 registers for PSR configuration

[Nautiyal, Ankit K]

On 2/19/2026 6:37 PM, Jouni Högander wrote:
> Add DSC_SU_PARAMETER_SET_0_DSC0 and DSC_SU_PARAMETER_SET_0_DSC1 register
> definitions for Selective Update Early Transport configuration.
>
> Bspec: 71709
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_psr_regs.h | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> index 8afbf5a38335..3d1523dece8b 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> @@ -266,6 +266,18 @@
>   #define _PIPE_SRCSZ_ERLY_TPT_B	0x71074
>   #define PIPE_SRCSZ_ERLY_TPT(pipe)	_MMIO_PIPE((pipe), _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B)
>   
> +#define _DSC_SU_PARAMETER_SET_0_DSC0_A		0x78064


I understand these are needed for PSR SU region, but these seem to 
belong to DSC registers file with other DSC registers.


Regards,

Ankit

> +#define _DSC_SU_PARAMETER_SET_0_DSC0_B		0x78264
> +#define DSC_SU_PARAMETER_SET_0_DSC0(pipe)	_MMIO_PIPE((pipe), _DSC_SU_PARAMETER_SET_0_DSC0_A, _DSC_SU_PARAMETER_SET_0_DSC0_B)
> +#define   DSC_SU_PARAMETER_SET_0_SU_SLICE_ROW_PER_FRAME_MASK	REG_GENMASK(31, 20)
> +#define   DSC_SU_PARAMETER_SET_0_SU_SLICE_ROW_PER_FRAME(rows)	REG_FIELD_PREP(DSC_SU_PARAMETER_SET_0_SU_SLICE_ROW_PER_FRAME_MASK, (rows))
> +#define   DSC_SU_PARAMETER_SET_0_SU_PIC_HEIGHT_MASK		REG_GENMASK(15, 0)
> +#define   DSC_SU_PARAMETER_SET_0_SU_PIC_HEIGHT(h)		REG_FIELD_PREP(DSC_SU_PARAMETER_SET_0_SU_PIC_HEIGHT_MASK, (h))
> +
> +#define _DSC_SU_PARAMETER_SET_0_DSC1_A		0x78164
> +#define _DSC_SU_PARAMETER_SET_0_DSC1_B		0x78364
> +#define DSC_SU_PARAMETER_SET_0_DSC1(pipe)	_MMIO_PIPE((pipe), _DSC_SU_PARAMETER_SET_0_DSC1_A, _DSC_SU_PARAMETER_SET_0_DSC1_B)
> +
>   #define _PR_ALPM_CTL_A	0x60948
>   #define PR_ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv, tran, _PR_ALPM_CTL_A)
>   #define  PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU	BIT(6)

Re: [PATCH 2/5] drm/i915/psr: Add DSC_SU_PARAMETER_SET_0 registers for PSR configuration

[Hogander, Jouni]

On Wed, 2026-02-25 at 09:51 +0530, Nautiyal, Ankit K wrote:
> 
> On 2/19/2026 6:37 PM, Jouni Högander wrote:
> > Add DSC_SU_PARAMETER_SET_0_DSC0 and DSC_SU_PARAMETER_SET_0_DSC1
> > register
> > definitions for Selective Update Early Transport configuration.
> > 
> > Bspec: 71709
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_psr_regs.h | 12 ++++++++++++
> >   1 file changed, 12 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > index 8afbf5a38335..3d1523dece8b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
> > @@ -266,6 +266,18 @@
> >   #define _PIPE_SRCSZ_ERLY_TPT_B	0x71074
> >   #define PIPE_SRCSZ_ERLY_TPT(pipe)	_MMIO_PIPE((pipe),
> > _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B)
> >   
> > +#define _DSC_SU_PARAMETER_SET_0_DSC0_A		0x78064
> 
> 
> I understand these are needed for PSR SU region, but these seem to 
> belong to DSC registers file with other DSC registers.

I also considered to place it there and decided this would be more
clear as Early Transport specific and written only in intel_psr.c.
PIPE_SRCSZ_ERLY_TPT is here as well. You can't even find definition in
Bsec DSC documentation (see Bspec 68912) We can consider moving these
later (PIPE_SRCSZ_ERLY_TPT and DSC_SU_PARAMETER_SE_0) at once and move
configuration of them from intel_psr.c. Thought I'm not sure if we want
todo that. What do you think?

BR,
Jouni Högander

> 
> 
> Regards,
> 
> Ankit
> 
> > +#define _DSC_SU_PARAMETER_SET_0_DSC0_B		0x78264
> > +#define DSC_SU_PARAMETER_SET_0_DSC0(pipe)	_MMIO_PIPE((pipe),
> > _DSC_SU_PARAMETER_SET_0_DSC0_A, _DSC_SU_PARAMETER_SET_0_DSC0_B)
> > +#define  
> > DSC_SU_PARAMETER_SET_0_SU_SLICE_ROW_PER_FRAME_MASK	REG_GENMASK(31, 20)
> > +#define  
> > DSC_SU_PARAMETER_SET_0_SU_SLICE_ROW_PER_FRAME(rows)	REG_FIELD_PREP(DSC_SU_PARAMETER_SET_0_SU_SLICE_ROW_PER_FRAME_MASK,(rows))
> > +#define  
> > DSC_SU_PARAMETER_SET_0_SU_PIC_HEIGHT_MASK		REG_GENMASK(15, 0)
> > +#define  
> > DSC_SU_PARAMETER_SET_0_SU_PIC_HEIGHT(h)		REG_FIELD_PREP(DSC_SU_PARAMETER_SET_0_SU_PIC_HEIGHT_MASK,(h))
> > +
> > +#define _DSC_SU_PARAMETER_SET_0_DSC1_A		0x78164
> > +#define _DSC_SU_PARAMETER_SET_0_DSC1_B		0x78364
> > +#define DSC_SU_PARAMETER_SET_0_DSC1(pipe)	_MMIO_PIPE((pipe),
> > _DSC_SU_PARAMETER_SET_0_DSC1_A, _DSC_SU_PARAMETER_SET_0_DSC1_B)
> > +
> >   #define _PR_ALPM_CTL_A	0x60948
> >   #define PR_ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv,
> > tran, _PR_ALPM_CTL_A)
> >   #define 
> > PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU	BIT(6)

Re: [PATCH 2/5] drm/i915/psr: Add DSC_SU_PARAMETER_SET_0 registers for PSR configuration

[Nautiyal, Ankit K]

On 2/25/2026 12:00 PM, Hogander, Jouni wrote:
> On Wed, 2026-02-25 at 09:51 +0530, Nautiyal, Ankit K wrote:
>> On 2/19/2026 6:37 PM, Jouni Högander wrote:
>>> Add DSC_SU_PARAMETER_SET_0_DSC0 and DSC_SU_PARAMETER_SET_0_DSC1
>>> register
>>> definitions for Selective Update Early Transport configuration.
>>>
>>> Bspec: 71709
>>> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
>>> ---
>>>    drivers/gpu/drm/i915/display/intel_psr_regs.h | 12 ++++++++++++
>>>    1 file changed, 12 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h
>>> b/drivers/gpu/drm/i915/display/intel_psr_regs.h
>>> index 8afbf5a38335..3d1523dece8b 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
>>> @@ -266,6 +266,18 @@
>>>    #define _PIPE_SRCSZ_ERLY_TPT_B	0x71074
>>>    #define PIPE_SRCSZ_ERLY_TPT(pipe)	_MMIO_PIPE((pipe),
>>> _PIPE_SRCSZ_ERLY_TPT_A, _PIPE_SRCSZ_ERLY_TPT_B)
>>>    
>>> +#define _DSC_SU_PARAMETER_SET_0_DSC0_A		0x78064
>>
>> I understand these are needed for PSR SU region, but these seem to
>> belong to DSC registers file with other DSC registers.
> I also considered to place it there and decided this would be more
> clear as Early Transport specific and written only in intel_psr.c.
> PIPE_SRCSZ_ERLY_TPT is here as well. You can't even find definition in
> Bsec DSC documentation (see Bspec 68912) We can consider moving these
> later (PIPE_SRCSZ_ERLY_TPT and DSC_SU_PARAMETER_SE_0) at once and move
> configuration of them from intel_psr.c. Thought I'm not sure if we want
> todo that. What do you think?

I understand the ET context and the existing PIPE_SRCSZ_ERLY_TPT, which 
also seem to be out of place.

What I can see is:
- 0x78064 and the rest sit inside the DSC MMIO range
- this still appears to be a DSC PPS register, which is needed for PSR 
ET condition.

So I believe that long term it will be cleaner if these are included 
with other VDSC registers.

We don’t need to move anything right now, keeping them with PSR regs is 
fine, but I think at some point of time these might be better placed in 
their respective files.

Regards,

Ankit


>
> BR,
> Jouni Högander
>
>>
>> Regards,
>>
>> Ankit
>>
>>> +#define _DSC_SU_PARAMETER_SET_0_DSC0_B		0x78264
>>> +#define DSC_SU_PARAMETER_SET_0_DSC0(pipe)	_MMIO_PIPE((pipe),
>>> _DSC_SU_PARAMETER_SET_0_DSC0_A, _DSC_SU_PARAMETER_SET_0_DSC0_B)
>>> +#define
>>> DSC_SU_PARAMETER_SET_0_SU_SLICE_ROW_PER_FRAME_MASK	REG_GENMASK(31, 20)
>>> +#define
>>> DSC_SU_PARAMETER_SET_0_SU_SLICE_ROW_PER_FRAME(rows)	REG_FIELD_PREP(DSC_SU_PARAMETER_SET_0_SU_SLICE_ROW_PER_FRAME_MASK,(rows))
>>> +#define
>>> DSC_SU_PARAMETER_SET_0_SU_PIC_HEIGHT_MASK		REG_GENMASK(15, 0)
>>> +#define
>>> DSC_SU_PARAMETER_SET_0_SU_PIC_HEIGHT(h)		REG_FIELD_PREP(DSC_SU_PARAMETER_SET_0_SU_PIC_HEIGHT_MASK,(h))
>>> +
>>> +#define _DSC_SU_PARAMETER_SET_0_DSC1_A		0x78164
>>> +#define _DSC_SU_PARAMETER_SET_0_DSC1_B		0x78364
>>> +#define DSC_SU_PARAMETER_SET_0_DSC1(pipe)	_MMIO_PIPE((pipe),
>>> _DSC_SU_PARAMETER_SET_0_DSC1_A, _DSC_SU_PARAMETER_SET_0_DSC1_B)
>>> +
>>>    #define _PR_ALPM_CTL_A	0x60948
>>>    #define PR_ALPM_CTL(dev_priv, tran)	_MMIO_TRANS2(dev_priv,
>>> tran, _PR_ALPM_CTL_A)
>>>    #define
>>> PR_ALPM_CTL_ALLOW_LINK_OFF_BETWEEN_AS_SDP_AND_SU	BIT(6)

[PATCH 3/5] drm/i915/dsc: Convert intel_dsc_get_vdsc_per_pipe as non-static

[Jouni Högander]

We need to do some configurations on DSC when using PSR2/PR Selective
Update Early Transport. Convert intel_dsc_get_vdsc_per_pipe as non-static
to make it available for PSR code.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 2 +-
 drivers/gpu/drm/i915/display/intel_vdsc.h | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 7e53201b3cb1..f27ec0251613 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -467,7 +467,7 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
 		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
 }
 
-static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state)
+int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state)
 {
 	return crtc_state->dsc.slice_config.streams_per_pipe;
 }
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
index f4d5b37293cf..b70ac86ca9ab 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.h
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
@@ -44,5 +44,6 @@ unsigned int intel_vdsc_prefill_lines(const struct intel_crtc_state *crtc_state)
 int intel_dsc_get_pixel_rate_with_dsc_bubbles(struct intel_display *display,
 					      int pixel_rate, int htotal,
 					      int dsc_horizontal_slices);
+int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state);
 
 #endif /* __INTEL_VDSC_H__ */
-- 
2.43.0

Re: [PATCH 3/5] drm/i915/dsc: Convert intel_dsc_get_vdsc_per_pipe as non-static

[Nautiyal, Ankit K]

On 2/19/2026 6:37 PM, Jouni Högander wrote:
> We need to do some configurations on DSC when using PSR2/PR Selective
> Update Early Transport. Convert intel_dsc_get_vdsc_per_pipe as non-static
> to make it available for PSR code.
>
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>


> ---
>   drivers/gpu/drm/i915/display/intel_vdsc.c | 2 +-
>   drivers/gpu/drm/i915/display/intel_vdsc.h | 1 +
>   2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
> index 7e53201b3cb1..f27ec0251613 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
> @@ -467,7 +467,7 @@ intel_dsc_power_domain(struct intel_crtc *crtc, enum transcoder cpu_transcoder)
>   		return POWER_DOMAIN_TRANSCODER_VDSC_PW2;
>   }
>   
> -static int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state)
> +int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state)
>   {
>   	return crtc_state->dsc.slice_config.streams_per_pipe;
>   }
> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.h b/drivers/gpu/drm/i915/display/intel_vdsc.h
> index f4d5b37293cf..b70ac86ca9ab 100644
> --- a/drivers/gpu/drm/i915/display/intel_vdsc.h
> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.h
> @@ -44,5 +44,6 @@ unsigned int intel_vdsc_prefill_lines(const struct intel_crtc_state *crtc_state)
>   int intel_dsc_get_pixel_rate_with_dsc_bubbles(struct intel_display *display,
>   					      int pixel_rate, int htotal,
>   					      int dsc_horizontal_slices);
> +int intel_dsc_get_vdsc_per_pipe(const struct intel_crtc_state *crtc_state);
>   
>   #endif /* __INTEL_VDSC_H__ */

[PATCH 4/5] drm/i915/psr: DSC configuration for Early Transport

[Jouni Högander]

There is Selective Update slice row per frame and picture height
configurations needed on DSC when using Selective Update Early
Transport. Calculate and configure these when using Early Transport.

Bspec: 68927
Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible")
Cc: <stable@vger.kernel.org> # v6.9+
Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  1 +
 drivers/gpu/drm/i915/display/intel_psr.c      | 24 +++++++++++++++++++
 2 files changed, 25 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index e8e4af03a6a6..8903804c04b1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1381,6 +1381,7 @@ struct intel_crtc_state {
 	u32 psr2_man_track_ctl;
 
 	u32 pipe_srcsz_early_tpt;
+	u32 dsc_su_parameter_set_0_calc;
 
 	struct drm_rect psr2_su_area;
 
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 331645a2c9f6..0a2948ec308d 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2618,6 +2618,11 @@ void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb,
 
 	intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
 			   crtc_state->pipe_srcsz_early_tpt);
+	intel_de_write_dsb(display, dsb, DSC_SU_PARAMETER_SET_0_DSC0(crtc->pipe),
+			   crtc_state->dsc_su_parameter_set_0_calc);
+	if (intel_dsc_get_vdsc_per_pipe(crtc_state) > 1)
+		intel_de_write_dsb(display, dsb, DSC_SU_PARAMETER_SET_0_DSC1(crtc->pipe),
+				   crtc_state->dsc_su_parameter_set_0_calc);
 }
 
 static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
@@ -2668,6 +2673,23 @@ static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state,
 	return PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1);
 }
 
+static u32 psr2_dsc_su_parameter_set_0_calc(struct intel_crtc_state *crtc_state,
+					    bool full_update)
+{
+	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
+	int slice_row_per_frame, pic_height;
+
+	if (!crtc_state->enable_psr2_su_region_et || full_update ||
+	    !crtc_state->dsc.compression_enable)
+		return 0;
+
+	slice_row_per_frame = drm_rect_height(&crtc_state->psr2_su_area) / vdsc_cfg->slice_height;
+	pic_height = slice_row_per_frame * vdsc_cfg->slice_height;
+
+	return DSC_SU_PARAMETER_SET_0_SU_SLICE_ROW_PER_FRAME(slice_row_per_frame) |
+		DSC_SU_PARAMETER_SET_0_SU_PIC_HEIGHT(pic_height);
+}
+
 static void clip_area_update(struct drm_rect *overlap_damage_area,
 			     struct drm_rect *damage_area,
 			     struct drm_rect *pipe_src)
@@ -3026,6 +3048,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 	psr2_man_trk_ctl_calc(crtc_state, full_update);
 	crtc_state->pipe_srcsz_early_tpt =
 		psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update);
+	crtc_state->dsc_su_parameter_set_0_calc = psr2_dsc_su_parameter_set_0_calc(crtc_state,
+										   full_update);
 	return 0;
 }
 
-- 
2.43.0

Re: [PATCH 4/5] drm/i915/psr: DSC configuration for Early Transport

[Nautiyal, Ankit K]

On 2/19/2026 6:37 PM, Jouni Högander wrote:
> There is Selective Update slice row per frame and picture height
> configurations needed on DSC when using Selective Update Early
> Transport. Calculate and configure these when using Early Transport.
>
> Bspec: 68927
> Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible")
> Cc: <stable@vger.kernel.org> # v6.9+


This patch needs the other patch where registers are defined. I am not 
sure if stable will only pick this patch or will try to find out the 
dependency patch.

We need to check if there is a way to tell the dependency patch/commit 
to stable, so that both patches are applied together.

If we want this change to get ported to older kernels, we might need to 
squash the register definition patch with this patch.


> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> ---
>   .../drm/i915/display/intel_display_types.h    |  1 +
>   drivers/gpu/drm/i915/display/intel_psr.c      | 24 +++++++++++++++++++
>   2 files changed, 25 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index e8e4af03a6a6..8903804c04b1 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -1381,6 +1381,7 @@ struct intel_crtc_state {
>   	u32 psr2_man_track_ctl;
>   
>   	u32 pipe_srcsz_early_tpt;
> +	u32 dsc_su_parameter_set_0_calc;

I think let's just have a bool parameter something like 
psr_su_update_dsc_pps.

We can set this bool variable during intel_psr2_sel_fetch_update()


>   
>   	struct drm_rect psr2_su_area;
>   
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 331645a2c9f6..0a2948ec308d 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -2618,6 +2618,11 @@ void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb,
>   
>   	intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
>   			   crtc_state->pipe_srcsz_early_tpt);
> +	intel_de_write_dsb(display, dsb, DSC_SU_PARAMETER_SET_0_DSC0(crtc->pipe),
> +			   crtc_state->dsc_su_parameter_set_0_calc);
> +	if (intel_dsc_get_vdsc_per_pipe(crtc_state) > 1)
> +		intel_de_write_dsb(display, dsb, DSC_SU_PARAMETER_SET_0_DSC1(crtc->pipe),
> +				   crtc_state->dsc_su_parameter_set_0_calc);
>   }
>   
>   static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
> @@ -2668,6 +2673,23 @@ static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state,
>   	return PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1);
>   }
>   
> +static u32 psr2_dsc_su_parameter_set_0_calc(struct intel_crtc_state *crtc_state,
> +					    bool full_update)
> +{
> +	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> +	int slice_row_per_frame, pic_height;
> +
> +	if (!crtc_state->enable_psr2_su_region_et || full_update ||
> +	    !crtc_state->dsc.compression_enable)
> +		return 0;
> +

Although we are making sure that height of the psr2_su_area is a 
multiple of the slice_height, perhaps it would be good to have a 
drm_WARN here to flag any misconfiguration i.e. if height is not a 
multiple of slice_height.


> +	slice_row_per_frame = drm_rect_height(&crtc_state->psr2_su_area) / vdsc_cfg->slice_height;
> +	pic_height = slice_row_per_frame * vdsc_cfg->slice_height;
> +
> +	return DSC_SU_PARAMETER_SET_0_SU_SLICE_ROW_PER_FRAME(slice_row_per_frame) |
> +		DSC_SU_PARAMETER_SET_0_SU_PIC_HEIGHT(pic_height);
> +}

Since this writes a DSC register belonging to PPS Set 0, this function 
should be moved to intel_vdsc.c.

Also, based on the boolean flag (psr_su_update_dsc_pps) discussed above, 
this function should simply retrieve the required fields from crtc_state 
and program the register.

Such a helper function should then be called from 
intel_psr2_program_trans_man_trk_ctl() in place of the direct 
intel_reg_write() call.

IMO, all register reads/writes, along with the wrappers/helpers around 
them, should live in the file corresponding to the block that owns those 
registers, based on context.


Regards,

Ankit

> +
>   static void clip_area_update(struct drm_rect *overlap_damage_area,
>   			     struct drm_rect *damage_area,
>   			     struct drm_rect *pipe_src)
> @@ -3026,6 +3048,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>   	psr2_man_trk_ctl_calc(crtc_state, full_update);
>   	crtc_state->pipe_srcsz_early_tpt =
>   		psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update);
> +	crtc_state->dsc_su_parameter_set_0_calc = psr2_dsc_su_parameter_set_0_calc(crtc_state,
> +										   full_update);
>   	return 0;
>   }
>   

Re: [PATCH 4/5] drm/i915/psr: DSC configuration for Early Transport

[Hogander, Jouni]

On Wed, 2026-02-25 at 17:36 +0530, Nautiyal, Ankit K wrote:
> 
> On 2/19/2026 6:37 PM, Jouni Högander wrote:
> > There is Selective Update slice row per frame and picture height
> > configurations needed on DSC when using Selective Update Early
> > Transport. Calculate and configure these when using Early
> > Transport.
> > 
> > Bspec: 68927
> > Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as
> > possible")
> > Cc: <stable@vger.kernel.org> # v6.9+
> 
> 
> This patch needs the other patch where registers are defined. I am
> not 
> sure if stable will only pick this patch or will try to find out the 
> dependency patch.
> 
> We need to check if there is a way to tell the dependency
> patch/commit 
> to stable, so that both patches are applied together.
> 
> If we want this change to get ported to older kernels, we might need
> to 
> squash the register definition patch with this patch.
> 
> 
> > Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
> > ---
> >   .../drm/i915/display/intel_display_types.h    |  1 +
> >   drivers/gpu/drm/i915/display/intel_psr.c      | 24
> > +++++++++++++++++++
> >   2 files changed, 25 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index e8e4af03a6a6..8903804c04b1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -1381,6 +1381,7 @@ struct intel_crtc_state {
> >   	u32 psr2_man_track_ctl;
> >   
> >   	u32 pipe_srcsz_early_tpt;
> > +	u32 dsc_su_parameter_set_0_calc;
> 
> I think let's just have a bool parameter something like 
> psr_su_update_dsc_pps.
> 
> We can set this bool variable during intel_psr2_sel_fetch_update()

You mean calculating value for the register when writing it? I think
for that purpose we can rely on crtc_state->enable_psr2_su_region_et
and crtc_state->dsc.compression_enable. No need to add new boolean.
Let's do it that way.
> 
> 
> >   
> >   	struct drm_rect psr2_su_area;
> >   
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 331645a2c9f6..0a2948ec308d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -2618,6 +2618,11 @@ void
> > intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb,
> >   
> >   	intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc-
> > >pipe),
> >   			   crtc_state->pipe_srcsz_early_tpt);
> > +	intel_de_write_dsb(display, dsb,
> > DSC_SU_PARAMETER_SET_0_DSC0(crtc->pipe),
> > +			   crtc_state-
> > >dsc_su_parameter_set_0_calc);
> > +	if (intel_dsc_get_vdsc_per_pipe(crtc_state) > 1)
> > +		intel_de_write_dsb(display, dsb,
> > DSC_SU_PARAMETER_SET_0_DSC1(crtc->pipe),
> > +				   crtc_state-
> > >dsc_su_parameter_set_0_calc);
> >   }
> >   
> >   static void psr2_man_trk_ctl_calc(struct intel_crtc_state
> > *crtc_state,
> > @@ -2668,6 +2673,23 @@ static u32
> > psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state,
> >   	return PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height -
> > 1);
> >   }
> >   
> > +static u32 psr2_dsc_su_parameter_set_0_calc(struct
> > intel_crtc_state *crtc_state,
> > +					    bool full_update)
> > +{
> > +	const struct drm_dsc_config *vdsc_cfg = &crtc_state-
> > >dsc.config;
> > +	int slice_row_per_frame, pic_height;
> > +
> > +	if (!crtc_state->enable_psr2_su_region_et || full_update
> > ||
> > +	    !crtc_state->dsc.compression_enable)
> > +		return 0;
> > +
> 
> Although we are making sure that height of the psr2_su_area is a 
> multiple of the slice_height, perhaps it would be good to have a 
> drm_WARN here to flag any misconfiguration i.e. if height is not a 
> multiple of slice_height.

I will add that warning and move these to intel_vdsc.c. I will also
move those register definitions you commented in patch 2.

> 
> 
> > +	slice_row_per_frame = drm_rect_height(&crtc_state-
> > >psr2_su_area) / vdsc_cfg->slice_height;
> > +	pic_height = slice_row_per_frame * vdsc_cfg->slice_height;
> > +
> > +	return
> > DSC_SU_PARAMETER_SET_0_SU_SLICE_ROW_PER_FRAME(slice_row_per_frame)
> > |
> > +		DSC_SU_PARAMETER_SET_0_SU_PIC_HEIGHT(pic_height);
> > +}
> 
> Since this writes a DSC register belonging to PPS Set 0, this
> function 
> should be moved to intel_vdsc.c.
> 
> Also, based on the boolean flag (psr_su_update_dsc_pps) discussed
> above, 
> this function should simply retrieve the required fields from
> crtc_state 
> and program the register.

Now as you pointed this out I see there is no real reason follow what
is done for PSR2_MAN_TRK_CTL.

> 
> Such a helper function should then be called from 
> intel_psr2_program_trans_man_trk_ctl() in place of the direct 
> intel_reg_write() call.
> 
> IMO, all register reads/writes, along with the wrappers/helpers
> around 
> them, should live in the file corresponding to the block that owns
> those 
> registers, based on context.

Ok, you convinced me. I will move these.

BR,
Jouni Högander

> 
> 
> Regards,
> 
> Ankit
> 
> > +
> >   static void clip_area_update(struct drm_rect
> > *overlap_damage_area,
> >   			     struct drm_rect *damage_area,
> >   			     struct drm_rect *pipe_src)
> > @@ -3026,6 +3048,8 @@ int intel_psr2_sel_fetch_update(struct
> > intel_atomic_state *state,
> >   	psr2_man_trk_ctl_calc(crtc_state, full_update);
> >   	crtc_state->pipe_srcsz_early_tpt =
> >   		psr2_pipe_srcsz_early_tpt_calc(crtc_state,
> > full_update);
> > +	crtc_state->dsc_su_parameter_set_0_calc =
> > psr2_dsc_su_parameter_set_0_calc(crtc_state,
> > +								
> > 		   full_update);
> >   	return 0;
> >   }
> >   

Re: [PATCH 4/5] drm/i915/psr: DSC configuration for Early Transport

[Jani Nikula]

On Wed, 25 Feb 2026, "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com> wrote:
> On 2/19/2026 6:37 PM, Jouni Högander wrote:
>> There is Selective Update slice row per frame and picture height
>> configurations needed on DSC when using Selective Update Early
>> Transport. Calculate and configure these when using Early Transport.
>>
>> Bspec: 68927
>> Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible")
>> Cc: <stable@vger.kernel.org> # v6.9+
>
>
> This patch needs the other patch where registers are defined. I am not 
> sure if stable will only pick this patch or will try to find out the 
> dependency patch.
>
> We need to check if there is a way to tell the dependency patch/commit 
> to stable, so that both patches are applied together.
>
> If we want this change to get ported to older kernels, we might need to 
> squash the register definition patch with this patch.

Nope. Neither we nor stable want dependencies squashed. They'll happily
pick up extra dependency commits if needed, though.

Someone(tm) just needs to let them know about the dependencies when they
send the mail about (the presumably failed) backport attempt.

BR,
Jani.


>
>
>> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
>> ---
>>   .../drm/i915/display/intel_display_types.h    |  1 +
>>   drivers/gpu/drm/i915/display/intel_psr.c      | 24 +++++++++++++++++++
>>   2 files changed, 25 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index e8e4af03a6a6..8903804c04b1 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -1381,6 +1381,7 @@ struct intel_crtc_state {
>>   	u32 psr2_man_track_ctl;
>>   
>>   	u32 pipe_srcsz_early_tpt;
>> +	u32 dsc_su_parameter_set_0_calc;
>
> I think let's just have a bool parameter something like 
> psr_su_update_dsc_pps.
>
> We can set this bool variable during intel_psr2_sel_fetch_update()
>
>
>>   
>>   	struct drm_rect psr2_su_area;
>>   
>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>> index 331645a2c9f6..0a2948ec308d 100644
>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>> @@ -2618,6 +2618,11 @@ void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb,
>>   
>>   	intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
>>   			   crtc_state->pipe_srcsz_early_tpt);
>> +	intel_de_write_dsb(display, dsb, DSC_SU_PARAMETER_SET_0_DSC0(crtc->pipe),
>> +			   crtc_state->dsc_su_parameter_set_0_calc);
>> +	if (intel_dsc_get_vdsc_per_pipe(crtc_state) > 1)
>> +		intel_de_write_dsb(display, dsb, DSC_SU_PARAMETER_SET_0_DSC1(crtc->pipe),
>> +				   crtc_state->dsc_su_parameter_set_0_calc);
>>   }
>>   
>>   static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
>> @@ -2668,6 +2673,23 @@ static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state,
>>   	return PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1);
>>   }
>>   
>> +static u32 psr2_dsc_su_parameter_set_0_calc(struct intel_crtc_state *crtc_state,
>> +					    bool full_update)
>> +{
>> +	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
>> +	int slice_row_per_frame, pic_height;
>> +
>> +	if (!crtc_state->enable_psr2_su_region_et || full_update ||
>> +	    !crtc_state->dsc.compression_enable)
>> +		return 0;
>> +
>
> Although we are making sure that height of the psr2_su_area is a 
> multiple of the slice_height, perhaps it would be good to have a 
> drm_WARN here to flag any misconfiguration i.e. if height is not a 
> multiple of slice_height.
>
>
>> +	slice_row_per_frame = drm_rect_height(&crtc_state->psr2_su_area) / vdsc_cfg->slice_height;
>> +	pic_height = slice_row_per_frame * vdsc_cfg->slice_height;
>> +
>> +	return DSC_SU_PARAMETER_SET_0_SU_SLICE_ROW_PER_FRAME(slice_row_per_frame) |
>> +		DSC_SU_PARAMETER_SET_0_SU_PIC_HEIGHT(pic_height);
>> +}
>
> Since this writes a DSC register belonging to PPS Set 0, this function 
> should be moved to intel_vdsc.c.
>
> Also, based on the boolean flag (psr_su_update_dsc_pps) discussed above, 
> this function should simply retrieve the required fields from crtc_state 
> and program the register.
>
> Such a helper function should then be called from 
> intel_psr2_program_trans_man_trk_ctl() in place of the direct 
> intel_reg_write() call.
>
> IMO, all register reads/writes, along with the wrappers/helpers around 
> them, should live in the file corresponding to the block that owns those 
> registers, based on context.
>
>
> Regards,
>
> Ankit
>
>> +
>>   static void clip_area_update(struct drm_rect *overlap_damage_area,
>>   			     struct drm_rect *damage_area,
>>   			     struct drm_rect *pipe_src)
>> @@ -3026,6 +3048,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>>   	psr2_man_trk_ctl_calc(crtc_state, full_update);
>>   	crtc_state->pipe_srcsz_early_tpt =
>>   		psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update);
>> +	crtc_state->dsc_su_parameter_set_0_calc = psr2_dsc_su_parameter_set_0_calc(crtc_state,
>> +										   full_update);
>>   	return 0;
>>   }
>>   

-- 
Jani Nikula, Intel

Re: [PATCH 4/5] drm/i915/psr: DSC configuration for Early Transport

[Nautiyal, Ankit K]

On 2/25/2026 6:59 PM, Jani Nikula wrote:
> On Wed, 25 Feb 2026, "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com> wrote:
>> On 2/19/2026 6:37 PM, Jouni Högander wrote:
>>> There is Selective Update slice row per frame and picture height
>>> configurations needed on DSC when using Selective Update Early
>>> Transport. Calculate and configure these when using Early Transport.
>>>
>>> Bspec: 68927
>>> Fixes: 467e4e061c44 ("drm/i915/psr: Enable psr2 early transport as possible")
>>> Cc: <stable@vger.kernel.org> # v6.9+
>>
>> This patch needs the other patch where registers are defined. I am not
>> sure if stable will only pick this patch or will try to find out the
>> dependency patch.
>>
>> We need to check if there is a way to tell the dependency patch/commit
>> to stable, so that both patches are applied together.
>>
>> If we want this change to get ported to older kernels, we might need to
>> squash the register definition patch with this patch.
> Nope. Neither we nor stable want dependencies squashed. They'll happily
> pick up extra dependency commits if needed, though.
>
> Someone(tm) just needs to let them know about the dependencies when they
> send the mail about (the presumably failed) backport attempt.

Got it :) thanks Jani.

Regards,

Ankit

>
> BR,
> Jani.
>
>
>>
>>> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
>>> ---
>>>    .../drm/i915/display/intel_display_types.h    |  1 +
>>>    drivers/gpu/drm/i915/display/intel_psr.c      | 24 +++++++++++++++++++
>>>    2 files changed, 25 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> index e8e4af03a6a6..8903804c04b1 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>>> @@ -1381,6 +1381,7 @@ struct intel_crtc_state {
>>>    	u32 psr2_man_track_ctl;
>>>    
>>>    	u32 pipe_srcsz_early_tpt;
>>> +	u32 dsc_su_parameter_set_0_calc;
>> I think let's just have a bool parameter something like
>> psr_su_update_dsc_pps.
>>
>> We can set this bool variable during intel_psr2_sel_fetch_update()
>>
>>
>>>    
>>>    	struct drm_rect psr2_su_area;
>>>    
>>> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
>>> index 331645a2c9f6..0a2948ec308d 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_psr.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
>>> @@ -2618,6 +2618,11 @@ void intel_psr2_program_trans_man_trk_ctl(struct intel_dsb *dsb,
>>>    
>>>    	intel_de_write_dsb(display, dsb, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
>>>    			   crtc_state->pipe_srcsz_early_tpt);
>>> +	intel_de_write_dsb(display, dsb, DSC_SU_PARAMETER_SET_0_DSC0(crtc->pipe),
>>> +			   crtc_state->dsc_su_parameter_set_0_calc);
>>> +	if (intel_dsc_get_vdsc_per_pipe(crtc_state) > 1)
>>> +		intel_de_write_dsb(display, dsb, DSC_SU_PARAMETER_SET_0_DSC1(crtc->pipe),
>>> +				   crtc_state->dsc_su_parameter_set_0_calc);
>>>    }
>>>    
>>>    static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
>>> @@ -2668,6 +2673,23 @@ static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state,
>>>    	return PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1);
>>>    }
>>>    
>>> +static u32 psr2_dsc_su_parameter_set_0_calc(struct intel_crtc_state *crtc_state,
>>> +					    bool full_update)
>>> +{
>>> +	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
>>> +	int slice_row_per_frame, pic_height;
>>> +
>>> +	if (!crtc_state->enable_psr2_su_region_et || full_update ||
>>> +	    !crtc_state->dsc.compression_enable)
>>> +		return 0;
>>> +
>> Although we are making sure that height of the psr2_su_area is a
>> multiple of the slice_height, perhaps it would be good to have a
>> drm_WARN here to flag any misconfiguration i.e. if height is not a
>> multiple of slice_height.
>>
>>
>>> +	slice_row_per_frame = drm_rect_height(&crtc_state->psr2_su_area) / vdsc_cfg->slice_height;
>>> +	pic_height = slice_row_per_frame * vdsc_cfg->slice_height;
>>> +
>>> +	return DSC_SU_PARAMETER_SET_0_SU_SLICE_ROW_PER_FRAME(slice_row_per_frame) |
>>> +		DSC_SU_PARAMETER_SET_0_SU_PIC_HEIGHT(pic_height);
>>> +}
>> Since this writes a DSC register belonging to PPS Set 0, this function
>> should be moved to intel_vdsc.c.
>>
>> Also, based on the boolean flag (psr_su_update_dsc_pps) discussed above,
>> this function should simply retrieve the required fields from crtc_state
>> and program the register.
>>
>> Such a helper function should then be called from
>> intel_psr2_program_trans_man_trk_ctl() in place of the direct
>> intel_reg_write() call.
>>
>> IMO, all register reads/writes, along with the wrappers/helpers around
>> them, should live in the file corresponding to the block that owns those
>> registers, based on context.
>>
>>
>> Regards,
>>
>> Ankit
>>
>>> +
>>>    static void clip_area_update(struct drm_rect *overlap_damage_area,
>>>    			     struct drm_rect *damage_area,
>>>    			     struct drm_rect *pipe_src)
>>> @@ -3026,6 +3048,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
>>>    	psr2_man_trk_ctl_calc(crtc_state, full_update);
>>>    	crtc_state->pipe_srcsz_early_tpt =
>>>    		psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update);
>>> +	crtc_state->dsc_su_parameter_set_0_calc = psr2_dsc_su_parameter_set_0_calc(crtc_state,
>>> +										   full_update);
>>>    	return 0;
>>>    }
>>>    

[PATCH 5/5] drm/i915/psr: Drop cursor_in_su_area from intel_psr2_sel_fetch_et_alignment

[Jouni Högander]

Boolean variable cursor_in_su_area is not really used for anything. Remove
it.

Signed-off-by: Jouni Högander <jouni.hogander@intel.com>
---
 drivers/gpu/drm/i915/display/intel_psr.c | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 0a2948ec308d..55d93db72691 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -2744,8 +2744,7 @@ static bool intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_st
  */
 static void
 intel_psr2_sel_fetch_et_alignment(struct intel_atomic_state *state,
-				  struct intel_crtc *crtc,
-				  bool *cursor_in_su_area)
+				  struct intel_crtc *crtc)
 {
 	struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_plane_state *new_plane_state;
@@ -2773,7 +2772,6 @@ intel_psr2_sel_fetch_et_alignment(struct intel_atomic_state *state,
 
 		clip_area_update(&crtc_state->psr2_su_area, &new_plane_state->uapi.dst,
 				 &crtc_state->pipe_src);
-		*cursor_in_su_area = true;
 	}
 }
 
@@ -2869,7 +2867,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 	struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
 	struct intel_plane_state *new_plane_state, *old_plane_state;
 	struct intel_plane *plane;
-	bool full_update = false, cursor_in_su_area = false;
+	bool full_update = false;
 	int i, ret;
 
 	if (!crtc_state->enable_psr2_sel_fetch)
@@ -2983,8 +2981,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
 		 * drm_atomic_add_affected_planes to ensure visible cursor is added into
 		 * affected planes even when cursor is not updated by itself.
 		 */
-		intel_psr2_sel_fetch_et_alignment(state, crtc, &cursor_in_su_area);
-
+		intel_psr2_sel_fetch_et_alignment(state, crtc);
 	} while (intel_psr2_sel_fetch_pipe_alignment(crtc_state));
 
 	/*
-- 
2.43.0

✓ i915.CI.BAT: success for PSR/PR Selective Fetch Early Transport fixes

[Patchwork]

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== Series Details ==

Series: PSR/PR Selective Fetch Early Transport fixes
URL   : https://patchwork.freedesktop.org/series/161836/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_18006 -> Patchwork_161836v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/index.html

Participating hosts (43 -> 41)
------------------------------

  Missing    (2): bat-dg2-13 fi-snb-2520m 

Known issues
------------

  Here are the changes found in Patchwork_161836v1 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live:
    - bat-mtlp-8:         [PASS][1] -> [DMESG-FAIL][2] ([i915#12061]) +1 other test dmesg-fail
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/bat-mtlp-8/igt@i915_selftest@live.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/bat-mtlp-8/igt@i915_selftest@live.html

  * igt@i915_selftest@live@workarounds:
    - bat-dg2-9:          [PASS][3] -> [DMESG-FAIL][4] ([i915#12061]) +1 other test dmesg-fail
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/bat-dg2-9/igt@i915_selftest@live@workarounds.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/bat-dg2-9/igt@i915_selftest@live@workarounds.html

  
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061


Build changes
-------------

  * Linux: CI_DRM_18006 -> Patchwork_161836v1

  CI-20190529: 20190529
  CI_DRM_18006: c81e41f7aca96f583296a2a875f0179484b7a81f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8761: 8761
  Patchwork_161836v1: c81e41f7aca96f583296a2a875f0179484b7a81f @ git://anongit.freedesktop.org/gfx-ci/linux

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/index.html

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✗ i915.CI.Full: failure for PSR/PR Selective Fetch Early Transport fixes

[Patchwork]

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== Series Details ==

Series: PSR/PR Selective Fetch Early Transport fixes
URL   : https://patchwork.freedesktop.org/series/161836/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_18006_full -> Patchwork_161836v1_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_161836v1_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_161836v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_161836v1_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_plane_lowres@tiling-x@pipe-d-hdmi-a-4:
    - shard-dg1:          NOTRUN -> [FAIL][1] +3 other tests fail
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg1-18/igt@kms_plane_lowres@tiling-x@pipe-d-hdmi-a-4.html

  
#### Warnings ####

  * igt@kms_pm_dc@dc6-dpms:
    - shard-tglu:         [SKIP][2] ([i915#15128]) -> [FAIL][3]
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-tglu-6/igt@kms_pm_dc@dc6-dpms.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-3/igt@kms_pm_dc@dc6-dpms.html

  
New tests
---------

  New tests have been introduced between CI_DRM_18006_full and Patchwork_161836v1_full:

### New IGT tests (1) ###

  * igt@kms_cursor_edge_walk@256x256-top-bottom@pipe-c-hdmi-a-2:
    - Statuses : 1 pass(s)
    - Exec time: [3.62] s

  

Known issues
------------

  Here are the changes found in Patchwork_161836v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_bad_reloc@negative-reloc-lut:
    - shard-mtlp:         NOTRUN -> [SKIP][4] ([i915#3281])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-mtlp-8/igt@gem_bad_reloc@negative-reloc-lut.html

  * igt@gem_ccs@ctrl-surf-copy:
    - shard-rkl:          NOTRUN -> [SKIP][5] ([i915#3555] / [i915#9323])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-3/igt@gem_ccs@ctrl-surf-copy.html

  * igt@gem_create@create-ext-cpu-access-big:
    - shard-mtlp:         NOTRUN -> [SKIP][6] ([i915#6335])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-mtlp-8/igt@gem_create@create-ext-cpu-access-big.html

  * igt@gem_create@create-ext-set-pat:
    - shard-tglu-1:       NOTRUN -> [SKIP][7] ([i915#8562])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@gem_create@create-ext-set-pat.html

  * igt@gem_ctx_freq@sysfs@gt0:
    - shard-dg2:          [PASS][8] -> [FAIL][9] ([i915#9561]) +1 other test fail
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg2-5/igt@gem_ctx_freq@sysfs@gt0.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-3/igt@gem_ctx_freq@sysfs@gt0.html

  * igt@gem_ctx_isolation@preservation-s3@rcs0:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][10] ([i915#13356]) +1 other test incomplete
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-glk10/igt@gem_ctx_isolation@preservation-s3@rcs0.html

  * igt@gem_eio@in-flight-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][11] ([i915#13390])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-glk9/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_balancer@parallel-contexts:
    - shard-rkl:          NOTRUN -> [SKIP][12] ([i915#4525])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-3/igt@gem_exec_balancer@parallel-contexts.html

  * igt@gem_exec_capture@capture-invisible@smem0:
    - shard-tglu-1:       NOTRUN -> [SKIP][13] ([i915#6334]) +1 other test skip
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@gem_exec_capture@capture-invisible@smem0.html

  * igt@gem_exec_capture@capture-recoverable:
    - shard-tglu:         NOTRUN -> [SKIP][14] ([i915#6344])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@gem_exec_capture@capture-recoverable.html

  * igt@gem_exec_reloc@basic-write-gtt-active:
    - shard-rkl:          NOTRUN -> [SKIP][15] ([i915#3281]) +3 other tests skip
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-3/igt@gem_exec_reloc@basic-write-gtt-active.html

  * igt@gem_exec_suspend@basic-s0:
    - shard-dg2:          [PASS][16] -> [INCOMPLETE][17] ([i915#13356]) +1 other test incomplete
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg2-8/igt@gem_exec_suspend@basic-s0.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-1/igt@gem_exec_suspend@basic-s0.html

  * igt@gem_lmem_swapping@heavy-random:
    - shard-glk:          NOTRUN -> [SKIP][18] ([i915#4613]) +1 other test skip
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-glk9/igt@gem_lmem_swapping@heavy-random.html
    - shard-tglu:         NOTRUN -> [SKIP][19] ([i915#4613])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@gem_lmem_swapping@heavy-random.html

  * igt@gem_lmem_swapping@heavy-verify-random:
    - shard-rkl:          NOTRUN -> [SKIP][20] ([i915#4613]) +1 other test skip
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-3/igt@gem_lmem_swapping@heavy-verify-random.html

  * igt@gem_lmem_swapping@parallel-random-verify-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][21] ([i915#4613]) +3 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@gem_lmem_swapping@parallel-random-verify-ccs.html

  * igt@gem_mmap_wc@read-write:
    - shard-mtlp:         NOTRUN -> [SKIP][22] ([i915#4083])
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-mtlp-8/igt@gem_mmap_wc@read-write.html

  * igt@gem_partial_pwrite_pread@reads-uncached:
    - shard-rkl:          NOTRUN -> [SKIP][23] ([i915#3282]) +2 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@gem_partial_pwrite_pread@reads-uncached.html

  * igt@gem_pwrite@basic-exhaustion:
    - shard-tglu:         NOTRUN -> [WARN][24] ([i915#2658])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@gem_pwrite@basic-exhaustion.html

  * igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled:
    - shard-mtlp:         NOTRUN -> [SKIP][25] ([i915#8428])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-mtlp-8/igt@gem_render_copy@yf-tiled-mc-ccs-to-vebox-y-tiled.html

  * igt@gem_userptr_blits@coherency-sync:
    - shard-rkl:          NOTRUN -> [SKIP][26] ([i915#3297]) +1 other test skip
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@gem_userptr_blits@coherency-sync.html

  * igt@gem_userptr_blits@dmabuf-sync:
    - shard-tglu:         NOTRUN -> [SKIP][27] ([i915#3297] / [i915#3323])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@gem_userptr_blits@dmabuf-sync.html

  * igt@gem_userptr_blits@dmabuf-unsync:
    - shard-tglu-1:       NOTRUN -> [SKIP][28] ([i915#3297]) +2 other tests skip
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@gem_userptr_blits@dmabuf-unsync.html

  * igt@gem_userptr_blits@unsync-unmap-cycles:
    - shard-tglu:         NOTRUN -> [SKIP][29] ([i915#3297])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@gem_userptr_blits@unsync-unmap-cycles.html

  * igt@gen7_exec_parse@chained-batch:
    - shard-mtlp:         NOTRUN -> [SKIP][30]
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-mtlp-8/igt@gen7_exec_parse@chained-batch.html

  * igt@gen9_exec_parse@basic-rejected-ctx-param:
    - shard-rkl:          NOTRUN -> [SKIP][31] ([i915#2527]) +1 other test skip
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@gen9_exec_parse@basic-rejected-ctx-param.html

  * igt@gen9_exec_parse@bb-large:
    - shard-tglu-1:       NOTRUN -> [SKIP][32] ([i915#2527] / [i915#2856]) +2 other tests skip
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@gen9_exec_parse@bb-large.html

  * igt@gen9_exec_parse@bb-start-param:
    - shard-tglu:         NOTRUN -> [SKIP][33] ([i915#2527] / [i915#2856]) +1 other test skip
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@gen9_exec_parse@bb-start-param.html

  * igt@i915_module_load@resize-bar:
    - shard-tglu-1:       NOTRUN -> [SKIP][34] ([i915#6412])
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@i915_module_load@resize-bar.html

  * igt@i915_pm_freq_api@freq-basic-api:
    - shard-tglu:         NOTRUN -> [SKIP][35] ([i915#8399])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@i915_pm_freq_api@freq-basic-api.html

  * igt@i915_pm_freq_api@freq-reset-multiple:
    - shard-tglu-1:       NOTRUN -> [SKIP][36] ([i915#8399])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@i915_pm_freq_api@freq-reset-multiple.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-rkl:          [PASS][37] -> [INCOMPLETE][38] ([i915#13356])
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-5/igt@i915_pm_rpm@system-suspend.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-3/igt@i915_pm_rpm@system-suspend.html

  * igt@i915_pm_sseu@full-enable:
    - shard-tglu-1:       NOTRUN -> [SKIP][39] ([i915#4387])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@i915_pm_sseu@full-enable.html

  * igt@i915_suspend@sysfs-reader:
    - shard-rkl:          [PASS][40] -> [INCOMPLETE][41] ([i915#4817])
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@i915_suspend@sysfs-reader.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@i915_suspend@sysfs-reader.html

  * igt@kms_async_flips@async-flip-suspend-resume:
    - shard-rkl:          [PASS][42] -> [INCOMPLETE][43] ([i915#12761])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-5/igt@kms_async_flips@async-flip-suspend-resume.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-4/igt@kms_async_flips@async-flip-suspend-resume.html

  * igt@kms_async_flips@async-flip-suspend-resume@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [INCOMPLETE][44] ([i915#12761])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-4/igt@kms_async_flips@async-flip-suspend-resume@pipe-a-hdmi-a-2.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels:
    - shard-tglu-1:       NOTRUN -> [SKIP][45] ([i915#1769] / [i915#3555])
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_atomic_transition@plane-all-modeset-transition-fencing-internal-panels.html

  * igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3:
    - shard-dg2:          [PASS][46] -> [FAIL][47] ([i915#5956]) +1 other test fail
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg2-5/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-8/igt@kms_atomic_transition@plane-toggle-modeset-transition@pipe-a-hdmi-a-3.html

  * igt@kms_big_fb@4-tiled-16bpp-rotate-0:
    - shard-rkl:          NOTRUN -> [SKIP][48] ([i915#5286]) +4 other tests skip
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-3/igt@kms_big_fb@4-tiled-16bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-90:
    - shard-tglu-1:       NOTRUN -> [SKIP][49] ([i915#5286]) +2 other tests skip
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_big_fb@4-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-mtlp:         [PASS][50] -> [FAIL][51] ([i915#5138])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-tglu:         NOTRUN -> [SKIP][52] ([i915#5286]) +3 other tests skip
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip:
    - shard-snb:          NOTRUN -> [SKIP][53] +72 other tests skip
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-snb7/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip.html
    - shard-tglu:         NOTRUN -> [SKIP][54] ([i915#3828])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180-hflip.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0:
    - shard-dg1:          [PASS][55] -> [DMESG-WARN][56] ([i915#4423]) +4 other tests dmesg-warn
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg1-18/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg1-12/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_fb@x-tiled-16bpp-rotate-90:
    - shard-rkl:          NOTRUN -> [SKIP][57] ([i915#3638]) +1 other test skip
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_big_fb@x-tiled-16bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-16bpp-rotate-270:
    - shard-rkl:          NOTRUN -> [SKIP][58] +11 other tests skip
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_big_fb@yf-tiled-16bpp-rotate-270.html

  * igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][59] ([i915#10307] / [i915#10434] / [i915#6095]) +2 other tests skip
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-4/igt@kms_ccs@bad-aux-stride-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-hdmi-a-3:
    - shard-dg1:          NOTRUN -> [SKIP][60] ([i915#6095]) +167 other tests skip
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg1-12/igt@kms_ccs@ccs-on-another-bo-y-tiled-ccs@pipe-b-hdmi-a-3.html

  * igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [SKIP][61] ([i915#6095]) +39 other tests skip
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_ccs@ccs-on-another-bo-y-tiled-gen12-mc-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][62] ([i915#12313]) +1 other test skip
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-3/igt@kms_ccs@crc-primary-basic-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][63] ([i915#6095]) +79 other tests skip
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_ccs@crc-primary-basic-4-tiled-mtl-mc-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs:
    - shard-tglu-1:       NOTRUN -> [SKIP][64] ([i915#12313])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_ccs@crc-primary-rotation-180-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2:
    - shard-glk:          NOTRUN -> [SKIP][65] +244 other tests skip
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-glk5/igt@kms_ccs@crc-primary-rotation-180-4-tiled-mtl-mc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs:
    - shard-rkl:          NOTRUN -> [SKIP][66] ([i915#12805])
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_ccs@crc-primary-suspend-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][67] ([i915#6095]) +55 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-4/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-dg2-mc-ccs@pipe-d-hdmi-a-1.html

  * igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3:
    - shard-dg2:          NOTRUN -> [SKIP][68] ([i915#10307] / [i915#6095]) +140 other tests skip
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-6/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-3.html

  * igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs@pipe-c-hdmi-a-1:
    - shard-rkl:          NOTRUN -> [SKIP][69] ([i915#14098] / [i915#6095]) +46 other tests skip
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_ccs@crc-sprite-planes-basic-y-tiled-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1:
    - shard-tglu-1:       NOTRUN -> [SKIP][70] ([i915#6095]) +49 other tests skip
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs@pipe-b-hdmi-a-1.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-edp-1:
    - shard-mtlp:         NOTRUN -> [SKIP][71] ([i915#6095]) +4 other tests skip
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-mtlp-8/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-b-edp-1.html

  * igt@kms_cdclk@mode-transition:
    - shard-tglu-1:       NOTRUN -> [SKIP][72] ([i915#3742])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_cdclk@mode-transition.html

  * igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1:
    - shard-dg2:          NOTRUN -> [SKIP][73] ([i915#13781]) +3 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-4/igt@kms_cdclk@mode-transition@pipe-d-hdmi-a-1.html

  * igt@kms_chamelium_edid@dp-edid-stress-resolution-4k:
    - shard-tglu:         NOTRUN -> [SKIP][74] ([i915#11151] / [i915#7828]) +3 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_chamelium_edid@dp-edid-stress-resolution-4k.html

  * igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k:
    - shard-rkl:          NOTRUN -> [SKIP][75] ([i915#11151] / [i915#7828]) +5 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_chamelium_edid@hdmi-edid-stress-resolution-non-4k.html

  * igt@kms_chamelium_frames@dp-crc-single:
    - shard-tglu-1:       NOTRUN -> [SKIP][76] ([i915#11151] / [i915#7828]) +5 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_chamelium_frames@dp-crc-single.html

  * igt@kms_content_protection@atomic:
    - shard-rkl:          NOTRUN -> [SKIP][77] ([i915#6944] / [i915#7118] / [i915#9424])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_content_protection@atomic.html

  * igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-3:
    - shard-dg2:          NOTRUN -> [FAIL][78] ([i915#7173])
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-11/igt@kms_content_protection@atomic-dpms-hdcp14@pipe-a-dp-3.html

  * igt@kms_content_protection@atomic-hdcp14:
    - shard-tglu-1:       NOTRUN -> [SKIP][79] ([i915#6944]) +1 other test skip
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_content_protection@atomic-hdcp14.html

  * igt@kms_content_protection@dp-mst-type-0:
    - shard-rkl:          NOTRUN -> [SKIP][80] ([i915#15330] / [i915#3116])
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_content_protection@dp-mst-type-0.html

  * igt@kms_content_protection@dp-mst-type-1-suspend-resume:
    - shard-tglu-1:       NOTRUN -> [SKIP][81] ([i915#15330])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_content_protection@dp-mst-type-1-suspend-resume.html

  * igt@kms_content_protection@mei-interface:
    - shard-tglu:         NOTRUN -> [SKIP][82] ([i915#6944] / [i915#9424])
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_content_protection@mei-interface.html

  * igt@kms_content_protection@suspend-resume:
    - shard-tglu:         NOTRUN -> [SKIP][83] ([i915#6944])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_content_protection@suspend-resume.html

  * igt@kms_cursor_crc@cursor-offscreen-512x512:
    - shard-tglu:         NOTRUN -> [SKIP][84] ([i915#13049])
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_cursor_crc@cursor-offscreen-512x512.html

  * igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1:
    - shard-tglu:         NOTRUN -> [FAIL][85] ([i915#13566]) +1 other test fail
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_cursor_crc@cursor-random-128x42@pipe-a-hdmi-a-1.html

  * igt@kms_cursor_crc@cursor-sliding-64x21:
    - shard-rkl:          [PASS][86] -> [FAIL][87] ([i915#13566])
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-2/igt@kms_cursor_crc@cursor-sliding-64x21.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-4/igt@kms_cursor_crc@cursor-sliding-64x21.html

  * igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-2:
    - shard-rkl:          NOTRUN -> [FAIL][88] ([i915#13566]) +3 other tests fail
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-4/igt@kms_cursor_crc@cursor-sliding-64x21@pipe-a-hdmi-a-2.html

  * igt@kms_cursor_crc@cursor-sliding-max-size:
    - shard-tglu-1:       NOTRUN -> [SKIP][89] ([i915#3555]) +4 other tests skip
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_cursor_crc@cursor-sliding-max-size.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-glk:          NOTRUN -> [FAIL][90] ([i915#13028])
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-glk5/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - shard-tglu-1:       NOTRUN -> [SKIP][91] ([i915#4103]) +1 other test skip
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@cursorb-vs-flipa-legacy:
    - shard-mtlp:         NOTRUN -> [SKIP][92] ([i915#9809])
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-mtlp-8/igt@kms_cursor_legacy@cursorb-vs-flipa-legacy.html

  * igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle:
    - shard-rkl:          NOTRUN -> [SKIP][93] ([i915#4103])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_cursor_legacy@short-busy-flip-before-cursor-toggle.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-rkl:          NOTRUN -> [SKIP][94] ([i915#9723])
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-3/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-dg2:          [PASS][95] -> [SKIP][96] ([i915#3555])
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg2-11/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-5/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dp_aux_dev:
    - shard-tglu:         NOTRUN -> [SKIP][97] ([i915#1257])
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_dp_aux_dev.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-tglu-1:       NOTRUN -> [SKIP][98] ([i915#13707])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dp_linktrain_fallback@dsc-fallback:
    - shard-rkl:          NOTRUN -> [SKIP][99] ([i915#13707])
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_dp_linktrain_fallback@dsc-fallback.html

  * igt@kms_dsc@dsc-fractional-bpp-with-bpc:
    - shard-tglu:         NOTRUN -> [SKIP][100] ([i915#3840])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_dsc@dsc-fractional-bpp-with-bpc.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-tglu-1:       NOTRUN -> [SKIP][101] ([i915#3555] / [i915#3840])
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_dsc@dsc-with-output-formats-with-bpc:
    - shard-tglu-1:       NOTRUN -> [SKIP][102] ([i915#3840] / [i915#9053])
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_dsc@dsc-with-output-formats-with-bpc.html

  * igt@kms_fbcon_fbt@psr:
    - shard-tglu-1:       NOTRUN -> [SKIP][103] ([i915#3469])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_fbcon_fbt@psr.html

  * igt@kms_feature_discovery@display-2x:
    - shard-tglu:         NOTRUN -> [SKIP][104] ([i915#1839])
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_feature_discovery@display-2x.html

  * igt@kms_flip@2x-absolute-wf_vblank:
    - shard-tglu-1:       NOTRUN -> [SKIP][105] ([i915#3637] / [i915#9934]) +5 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_flip@2x-absolute-wf_vblank.html

  * igt@kms_flip@2x-blocking-wf_vblank:
    - shard-mtlp:         NOTRUN -> [SKIP][106] ([i915#3637] / [i915#9934])
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-mtlp-8/igt@kms_flip@2x-blocking-wf_vblank.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible:
    - shard-glk:          NOTRUN -> [INCOMPLETE][107] ([i915#12314] / [i915#12745] / [i915#4839])
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-glk5/igt@kms_flip@2x-flip-vs-suspend-interruptible.html

  * igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-hdmi-a1-hdmi-a2:
    - shard-glk:          NOTRUN -> [INCOMPLETE][108] ([i915#12314] / [i915#4839])
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-glk5/igt@kms_flip@2x-flip-vs-suspend-interruptible@ab-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@2x-plain-flip-fb-recreate:
    - shard-rkl:          NOTRUN -> [SKIP][109] ([i915#9934]) +2 other tests skip
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_flip@2x-plain-flip-fb-recreate.html

  * igt@kms_flip@2x-plain-flip-interruptible:
    - shard-tglu:         NOTRUN -> [SKIP][110] ([i915#3637] / [i915#9934]) +1 other test skip
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_flip@2x-plain-flip-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-glk:          NOTRUN -> [INCOMPLETE][111] ([i915#12745] / [i915#4839] / [i915#6113])
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-glk2/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a1:
    - shard-glk:          NOTRUN -> [INCOMPLETE][112] ([i915#12745])
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-glk2/igt@kms_flip@flip-vs-suspend-interruptible@a-hdmi-a1.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling:
    - shard-rkl:          NOTRUN -> [SKIP][113] ([i915#15643])
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-3/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-16bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling:
    - shard-tglu-1:       NOTRUN -> [SKIP][114] ([i915#15643]) +3 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-16bpp-yftile-downscaling.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen:
    - shard-tglu-1:       NOTRUN -> [SKIP][115] +44 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-rkl:          NOTRUN -> [SKIP][116] ([i915#1825]) +22 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt:
    - shard-dg2:          [PASS][117] -> [FAIL][118] ([i915#15389] / [i915#6880])
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-7/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-tiling-4:
    - shard-rkl:          NOTRUN -> [SKIP][119] ([i915#5439])
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_frontbuffer_tracking@fbc-tiling-4.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-blt:
    - shard-rkl:          NOTRUN -> [SKIP][120] ([i915#15102]) +2 other tests skip
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt:
    - shard-glk10:        NOTRUN -> [SKIP][121] +214 other tests skip
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-glk10/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-fullscreen:
    - shard-tglu:         NOTRUN -> [SKIP][122] +28 other tests skip
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-fullscreen.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt:
    - shard-mtlp:         NOTRUN -> [SKIP][123] ([i915#8708])
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-mtlp-8/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-gtt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc:
    - shard-tglu-1:       NOTRUN -> [SKIP][124] ([i915#15102]) +16 other tests skip
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render:
    - shard-rkl:          NOTRUN -> [SKIP][125] ([i915#15102] / [i915#3023]) +9 other tests skip
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
    - shard-tglu:         NOTRUN -> [SKIP][126] ([i915#15102]) +10 other tests skip
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html

  * igt@kms_hdr@bpc-switch:
    - shard-tglu-1:       NOTRUN -> [SKIP][127] ([i915#3555] / [i915#8228]) +1 other test skip
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_hdr@bpc-switch.html

  * igt@kms_hdr@invalid-metadata-sizes:
    - shard-rkl:          [PASS][128] -> [SKIP][129] ([i915#3555] / [i915#8228]) +1 other test skip
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_hdr@invalid-metadata-sizes.html
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_hdr@invalid-metadata-sizes.html

  * igt@kms_hdr@static-swap:
    - shard-dg2:          [PASS][130] -> [SKIP][131] ([i915#3555] / [i915#8228])
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg2-11/igt@kms_hdr@static-swap.html
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-6/igt@kms_hdr@static-swap.html

  * igt@kms_hdr@static-toggle-dpms:
    - shard-rkl:          NOTRUN -> [SKIP][132] ([i915#3555] / [i915#8228])
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_hdr@static-toggle-dpms.html

  * igt@kms_joiner@invalid-modeset-force-ultra-joiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][133] ([i915#15458]) +1 other test skip
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_joiner@invalid-modeset-force-ultra-joiner.html

  * igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
    - shard-tglu-1:       NOTRUN -> [SKIP][134] ([i915#15638])
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html

  * igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
    - shard-rkl:          NOTRUN -> [SKIP][135] ([i915#1839] / [i915#4816])
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-3/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html

  * igt@kms_pipe_crc_basic@suspend-read-crc:
    - shard-rkl:          [PASS][136] -> [INCOMPLETE][137] ([i915#12756] / [i915#13476])
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_pipe_crc_basic@suspend-read-crc.html
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_pipe_crc_basic@suspend-read-crc.html

  * igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-2:
    - shard-rkl:          [PASS][138] -> [INCOMPLETE][139] ([i915#13476])
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-2.html
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_pipe_crc_basic@suspend-read-crc@pipe-a-hdmi-a-2.html

  * igt@kms_pipe_stress@stress-xrgb8888-yftiled:
    - shard-tglu-1:       NOTRUN -> [SKIP][140] ([i915#14712])
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_pipe_stress@stress-xrgb8888-yftiled.html

  * igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping:
    - shard-tglu:         NOTRUN -> [SKIP][141] ([i915#15709])
   [141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_plane@pixel-format-4-tiled-lnl-ccs-modifier-source-clamping.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier:
    - shard-rkl:          NOTRUN -> [SKIP][142] ([i915#15709]) +1 other test skip
   [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_plane@pixel-format-4-tiled-mtl-mc-ccs-modifier.html

  * igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier@pipe-a-plane-5:
    - shard-rkl:          NOTRUN -> [SKIP][143] ([i915#15608]) +1 other test skip
   [143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_plane@pixel-format-y-tiled-gen12-rc-ccs-cc-modifier@pipe-a-plane-5.html

  * igt@kms_plane@pixel-format-yf-tiled-modifier-source-clamping:
    - shard-tglu-1:       NOTRUN -> [SKIP][144] ([i915#15709]) +3 other tests skip
   [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_plane@pixel-format-yf-tiled-modifier-source-clamping.html

  * igt@kms_plane_alpha_blend@alpha-basic:
    - shard-glk:          NOTRUN -> [FAIL][145] ([i915#12178])
   [145]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-glk5/igt@kms_plane_alpha_blend@alpha-basic.html

  * igt@kms_plane_alpha_blend@alpha-basic@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [FAIL][146] ([i915#7862]) +1 other test fail
   [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-glk5/igt@kms_plane_alpha_blend@alpha-basic@pipe-a-hdmi-a-1.html

  * igt@kms_plane_lowres@tiling-4:
    - shard-rkl:          NOTRUN -> [SKIP][147] ([i915#3555]) +1 other test skip
   [147]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_plane_lowres@tiling-4.html

  * igt@kms_plane_multiple@2x-tiling-yf:
    - shard-tglu:         NOTRUN -> [SKIP][148] ([i915#13958]) +1 other test skip
   [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_plane_multiple@2x-tiling-yf.html

  * igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a:
    - shard-tglu-1:       NOTRUN -> [SKIP][149] ([i915#15329]) +9 other tests skip
   [149]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a.html

  * igt@kms_pm_dc@dc3co-vpb-simulation:
    - shard-tglu:         NOTRUN -> [SKIP][150] ([i915#9685])
   [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-dg2:          [PASS][151] -> [SKIP][152] ([i915#9340])
   [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg2-4/igt@kms_pm_lpsp@kms-lpsp.html
   [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-11/igt@kms_pm_lpsp@kms-lpsp.html
    - shard-tglu-1:       NOTRUN -> [SKIP][153] ([i915#3828])
   [153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_pm_lpsp@screens-disabled:
    - shard-tglu:         NOTRUN -> [SKIP][154] ([i915#8430])
   [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_pm_lpsp@screens-disabled.html

  * igt@kms_pm_rpm@dpms-lpsp:
    - shard-dg2:          [PASS][155] -> [SKIP][156] ([i915#15073]) +2 other tests skip
   [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg2-4/igt@kms_pm_rpm@dpms-lpsp.html
   [156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-8/igt@kms_pm_rpm@dpms-lpsp.html
    - shard-rkl:          [PASS][157] -> [SKIP][158] ([i915#15073]) +2 other tests skip
   [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-8/igt@kms_pm_rpm@dpms-lpsp.html
   [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-3/igt@kms_pm_rpm@dpms-lpsp.html

  * igt@kms_pm_rpm@dpms-non-lpsp:
    - shard-rkl:          NOTRUN -> [SKIP][159] ([i915#15073])
   [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_pm_rpm@dpms-non-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp:
    - shard-tglu:         NOTRUN -> [SKIP][160] ([i915#15073])
   [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_pm_rpm@modeset-non-lpsp.html

  * igt@kms_pm_rpm@package-g7:
    - shard-tglu-1:       NOTRUN -> [SKIP][161] ([i915#15403])
   [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_pm_rpm@package-g7.html

  * igt@kms_pm_rpm@system-suspend-idle:
    - shard-rkl:          [PASS][162] -> [INCOMPLETE][163] ([i915#14419])
   [162]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_pm_rpm@system-suspend-idle.html
   [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_pm_rpm@system-suspend-idle.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf:
    - shard-rkl:          NOTRUN -> [SKIP][164] ([i915#11520]) +5 other tests skip
   [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-3/igt@kms_psr2_sf@fbc-pr-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area:
    - shard-snb:          NOTRUN -> [SKIP][165] ([i915#11520]) +1 other test skip
   [165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-snb7/igt@kms_psr2_sf@fbc-pr-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area:
    - shard-tglu-1:       NOTRUN -> [SKIP][166] ([i915#11520]) +5 other tests skip
   [166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_psr2_sf@fbc-pr-plane-move-sf-dmg-area.html

  * igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-glk10:        NOTRUN -> [SKIP][167] ([i915#11520]) +6 other tests skip
   [167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-glk10/igt@kms_psr2_sf@psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-tglu:         NOTRUN -> [SKIP][168] ([i915#11520]) +5 other tests skip
   [168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area:
    - shard-glk:          NOTRUN -> [SKIP][169] ([i915#11520]) +7 other tests skip
   [169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-glk5/igt@kms_psr2_sf@psr2-overlay-primary-update-sf-dmg-area.html

  * igt@kms_psr@fbc-pr-cursor-plane-move:
    - shard-mtlp:         NOTRUN -> [SKIP][170] ([i915#9688])
   [170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-mtlp-8/igt@kms_psr@fbc-pr-cursor-plane-move.html

  * igt@kms_psr@fbc-psr-no-drrs:
    - shard-tglu:         NOTRUN -> [SKIP][171] ([i915#9732]) +9 other tests skip
   [171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_psr@fbc-psr-no-drrs.html

  * igt@kms_psr@fbc-psr2-primary-blt:
    - shard-tglu-1:       NOTRUN -> [SKIP][172] ([i915#9732]) +16 other tests skip
   [172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_psr@fbc-psr2-primary-blt.html

  * igt@kms_psr@fbc-psr2-sprite-render:
    - shard-rkl:          NOTRUN -> [SKIP][173] ([i915#1072] / [i915#9732]) +11 other tests skip
   [173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_psr@fbc-psr2-sprite-render.html

  * igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
    - shard-tglu-1:       NOTRUN -> [SKIP][174] ([i915#9685]) +1 other test skip
   [174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html

  * igt@kms_rotation_crc@multiplane-rotation-cropping-top:
    - shard-glk10:        NOTRUN -> [INCOMPLETE][175] ([i915#15492]) +1 other test incomplete
   [175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-glk10/igt@kms_rotation_crc@multiplane-rotation-cropping-top.html

  * igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90:
    - shard-tglu-1:       NOTRUN -> [SKIP][176] ([i915#5289])
   [176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_rotation_crc@primary-yf-tiled-reflect-x-90.html

  * igt@kms_selftest@drm_framebuffer:
    - shard-glk:          NOTRUN -> [ABORT][177] ([i915#13179]) +1 other test abort
   [177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-glk5/igt@kms_selftest@drm_framebuffer.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - shard-tglu:         NOTRUN -> [SKIP][178] ([i915#3555]) +1 other test skip
   [178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@kms_setmode@basic-clone-single-crtc.html

  * igt@kms_vrr@max-min:
    - shard-rkl:          NOTRUN -> [SKIP][179] ([i915#9906])
   [179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_vrr@max-min.html

  * igt@kms_vrr@seamless-rr-switch-vrr:
    - shard-tglu-1:       NOTRUN -> [SKIP][180] ([i915#9906]) +1 other test skip
   [180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-1/igt@kms_vrr@seamless-rr-switch-vrr.html

  * igt@perf@gen8-unprivileged-single-ctx-counters:
    - shard-rkl:          NOTRUN -> [SKIP][181] ([i915#2436])
   [181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@perf@gen8-unprivileged-single-ctx-counters.html

  * igt@perf_pmu@module-unload:
    - shard-tglu:         NOTRUN -> [FAIL][182] ([i915#14433])
   [182]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@perf_pmu@module-unload.html

  * igt@perf_pmu@most-busy-check-all:
    - shard-rkl:          [PASS][183] -> [FAIL][184] ([i915#4349]) +1 other test fail
   [183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@perf_pmu@most-busy-check-all.html
   [184]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@perf_pmu@most-busy-check-all.html

  * igt@perf_pmu@rc6-suspend:
    - shard-glk:          NOTRUN -> [INCOMPLETE][185] ([i915#13356])
   [185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-glk6/igt@perf_pmu@rc6-suspend.html

  * igt@sriov_basic@enable-vfs-bind-unbind-each@numvfs-random:
    - shard-tglu:         NOTRUN -> [FAIL][186] ([i915#12910]) +8 other tests fail
   [186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-9/igt@sriov_basic@enable-vfs-bind-unbind-each@numvfs-random.html

  
#### Possible fixes ####

  * igt@gem_eio@in-flight-suspend:
    - shard-dg1:          [DMESG-WARN][187] ([i915#4391] / [i915#4423]) -> [PASS][188]
   [187]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg1-14/igt@gem_eio@in-flight-suspend.html
   [188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg1-15/igt@gem_eio@in-flight-suspend.html

  * igt@gem_exec_endless@dispatch:
    - shard-dg2:          [TIMEOUT][189] ([i915#3778] / [i915#7016]) -> [PASS][190]
   [189]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg2-11/igt@gem_exec_endless@dispatch.html
   [190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-6/igt@gem_exec_endless@dispatch.html

  * igt@gem_exec_endless@dispatch@vecs1:
    - shard-dg2:          [TIMEOUT][191] ([i915#7016]) -> [PASS][192]
   [191]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg2-11/igt@gem_exec_endless@dispatch@vecs1.html
   [192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-6/igt@gem_exec_endless@dispatch@vecs1.html

  * igt@gem_mmap_offset@clear-via-pagefault:
    - shard-mtlp:         [ABORT][193] ([i915#14809]) -> [PASS][194] +1 other test pass
   [193]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-mtlp-7/igt@gem_mmap_offset@clear-via-pagefault.html
   [194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-mtlp-8/igt@gem_mmap_offset@clear-via-pagefault.html

  * igt@gem_softpin@noreloc-s3:
    - shard-rkl:          [INCOMPLETE][195] ([i915#13809]) -> [PASS][196]
   [195]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@gem_softpin@noreloc-s3.html
   [196]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@gem_softpin@noreloc-s3.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
    - shard-rkl:          [INCOMPLETE][197] ([i915#13356]) -> [PASS][198]
   [197]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@i915_pm_rpm@system-suspend-execbuf.html
   [198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@i915_pm_rpm@system-suspend-execbuf.html

  * igt@i915_pm_rps@reset:
    - shard-snb:          [INCOMPLETE][199] ([i915#13729] / [i915#13821]) -> [PASS][200]
   [199]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-snb6/igt@i915_pm_rps@reset.html
   [200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-snb7/igt@i915_pm_rps@reset.html

  * igt@i915_selftest@live:
    - shard-mtlp:         [DMESG-FAIL][201] ([i915#12061] / [i915#15560]) -> [PASS][202]
   [201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-mtlp-3/igt@i915_selftest@live.html
   [202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-mtlp-1/igt@i915_selftest@live.html

  * igt@i915_selftest@live@workarounds:
    - shard-mtlp:         [DMESG-FAIL][203] ([i915#12061]) -> [PASS][204]
   [203]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-mtlp-3/igt@i915_selftest@live@workarounds.html
   [204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-mtlp-1/igt@i915_selftest@live@workarounds.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-fencing:
    - shard-dg2:          [FAIL][205] ([i915#5956]) -> [PASS][206]
   [205]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg2-3/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html
   [206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-4/igt@kms_atomic_transition@plane-all-modeset-transition-fencing.html

  * igt@kms_dither@fb-8bpc-vs-panel-8bpc:
    - shard-dg2:          [SKIP][207] ([i915#3555]) -> [PASS][208]
   [207]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg2-3/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html
   [208]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-11/igt@kms_dither@fb-8bpc-vs-panel-8bpc.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-dg2:          [SKIP][209] ([i915#13707]) -> [PASS][210]
   [209]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg2-4/igt@kms_dp_linktrain_fallback@dp-fallback.html
   [210]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-11/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2:
    - shard-glk:          [FAIL][211] ([i915#13027]) -> [PASS][212] +1 other test pass
   [211]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html
   [212]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-glk9/igt@kms_flip@2x-flip-vs-expired-vblank@ac-hdmi-a1-hdmi-a2.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-rkl:          [INCOMPLETE][213] ([i915#6113]) -> [PASS][214]
   [213]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-3/igt@kms_flip@flip-vs-suspend-interruptible.html
   [214]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-dg2:          [SKIP][215] ([i915#3555] / [i915#8228]) -> [PASS][216]
   [215]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg2-4/igt@kms_hdr@bpc-switch-dpms.html
   [216]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-11/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_hdr@static-toggle:
    - shard-rkl:          [SKIP][217] ([i915#3555] / [i915#8228]) -> [PASS][218] +1 other test pass
   [217]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_hdr@static-toggle.html
   [218]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_hdr@static-toggle.html

  * igt@kms_joiner@invalid-modeset-force-big-joiner:
    - shard-dg2:          [SKIP][219] ([i915#15459]) -> [PASS][220]
   [219]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg2-6/igt@kms_joiner@invalid-modeset-force-big-joiner.html
   [220]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-11/igt@kms_joiner@invalid-modeset-force-big-joiner.html

  * igt@kms_pm_rpm@modeset-lpsp:
    - shard-rkl:          [SKIP][221] ([i915#14544] / [i915#15073]) -> [PASS][222]
   [221]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_pm_rpm@modeset-lpsp.html
   [222]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_pm_rpm@modeset-lpsp.html

  * igt@kms_pm_rpm@modeset-non-lpsp-stress:
    - shard-rkl:          [SKIP][223] ([i915#15073]) -> [PASS][224]
   [223]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-5/igt@kms_pm_rpm@modeset-non-lpsp-stress.html
   [224]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-3/igt@kms_pm_rpm@modeset-non-lpsp-stress.html

  * igt@kms_rotation_crc@primary-rotation-90:
    - shard-dg1:          [DMESG-WARN][225] ([i915#4423]) -> [PASS][226] +1 other test pass
   [225]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg1-18/igt@kms_rotation_crc@primary-rotation-90.html
   [226]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg1-12/igt@kms_rotation_crc@primary-rotation-90.html

  * igt@kms_setmode@basic:
    - shard-tglu:         [FAIL][227] ([i915#15106]) -> [PASS][228] +2 other tests pass
   [227]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-tglu-5/igt@kms_setmode@basic.html
   [228]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-4/igt@kms_setmode@basic.html

  * igt@kms_setmode@basic@pipe-b-edp-1:
    - shard-mtlp:         [FAIL][229] ([i915#15106]) -> [PASS][230] +1 other test pass
   [229]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-mtlp-8/igt@kms_setmode@basic@pipe-b-edp-1.html
   [230]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-mtlp-4/igt@kms_setmode@basic@pipe-b-edp-1.html

  * igt@perf_pmu@busy-double-start@rcs0:
    - shard-mtlp:         [FAIL][231] ([i915#4349]) -> [PASS][232]
   [231]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-mtlp-7/igt@perf_pmu@busy-double-start@rcs0.html
   [232]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-mtlp-8/igt@perf_pmu@busy-double-start@rcs0.html

  
#### Warnings ####

  * igt@api_intel_bb@object-reloc-purge-cache:
    - shard-rkl:          [SKIP][233] ([i915#14544] / [i915#8411]) -> [SKIP][234] ([i915#8411])
   [233]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@api_intel_bb@object-reloc-purge-cache.html
   [234]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@api_intel_bb@object-reloc-purge-cache.html

  * igt@device_reset@unbind-cold-reset-rebind:
    - shard-rkl:          [SKIP][235] ([i915#11078]) -> [SKIP][236] ([i915#11078] / [i915#14544]) +1 other test skip
   [235]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@device_reset@unbind-cold-reset-rebind.html
   [236]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@device_reset@unbind-cold-reset-rebind.html

  * igt@gem_ccs@block-multicopy-compressed:
    - shard-rkl:          [SKIP][237] ([i915#9323]) -> [SKIP][238] ([i915#14544] / [i915#9323])
   [237]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@gem_ccs@block-multicopy-compressed.html
   [238]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@gem_ccs@block-multicopy-compressed.html

  * igt@gem_ccs@suspend-resume:
    - shard-rkl:          [SKIP][239] ([i915#14544] / [i915#9323]) -> [SKIP][240] ([i915#9323])
   [239]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@gem_ccs@suspend-resume.html
   [240]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@gem_ccs@suspend-resume.html

  * igt@gem_close_race@multigpu-basic-threads:
    - shard-rkl:          [SKIP][241] ([i915#14544] / [i915#7697]) -> [SKIP][242] ([i915#7697])
   [241]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@gem_close_race@multigpu-basic-threads.html
   [242]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@gem_close_race@multigpu-basic-threads.html

  * igt@gem_ctx_sseu@invalid-args:
    - shard-rkl:          [SKIP][243] ([i915#280]) -> [SKIP][244] ([i915#14544] / [i915#280])
   [243]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@gem_ctx_sseu@invalid-args.html
   [244]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@gem_ctx_sseu@invalid-args.html

  * igt@gem_exec_balancer@parallel:
    - shard-rkl:          [SKIP][245] ([i915#4525]) -> [SKIP][246] ([i915#14544] / [i915#4525]) +1 other test skip
   [245]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@gem_exec_balancer@parallel.html
   [246]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@gem_exec_balancer@parallel.html

  * igt@gem_exec_balancer@parallel-keep-submit-fence:
    - shard-rkl:          [SKIP][247] ([i915#14544] / [i915#4525]) -> [SKIP][248] ([i915#4525])
   [247]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@gem_exec_balancer@parallel-keep-submit-fence.html
   [248]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@gem_exec_balancer@parallel-keep-submit-fence.html

  * igt@gem_exec_reloc@basic-gtt-cpu:
    - shard-rkl:          [SKIP][249] ([i915#14544] / [i915#3281]) -> [SKIP][250] ([i915#3281]) +2 other tests skip
   [249]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@gem_exec_reloc@basic-gtt-cpu.html
   [250]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@gem_exec_reloc@basic-gtt-cpu.html

  * igt@gem_exec_reloc@basic-gtt-wc:
    - shard-rkl:          [SKIP][251] ([i915#3281]) -> [SKIP][252] ([i915#14544] / [i915#3281]) +3 other tests skip
   [251]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@gem_exec_reloc@basic-gtt-wc.html
   [252]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@gem_exec_reloc@basic-gtt-wc.html

  * igt@gem_lmem_evict@dontneed-evict-race:
    - shard-rkl:          [SKIP][253] ([i915#14544] / [i915#4613] / [i915#7582]) -> [SKIP][254] ([i915#4613] / [i915#7582])
   [253]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@gem_lmem_evict@dontneed-evict-race.html
   [254]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@gem_lmem_evict@dontneed-evict-race.html

  * igt@gem_lmem_swapping@heavy-multi:
    - shard-rkl:          [SKIP][255] ([i915#4613]) -> [SKIP][256] ([i915#14544] / [i915#4613])
   [255]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@gem_lmem_swapping@heavy-multi.html
   [256]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@gem_lmem_swapping@heavy-multi.html

  * igt@gem_lmem_swapping@random:
    - shard-rkl:          [SKIP][257] ([i915#14544] / [i915#4613]) -> [SKIP][258] ([i915#4613])
   [257]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@gem_lmem_swapping@random.html
   [258]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@gem_lmem_swapping@random.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-snoop:
    - shard-rkl:          [SKIP][259] ([i915#14544] / [i915#3282]) -> [SKIP][260] ([i915#3282]) +3 other tests skip
   [259]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html
   [260]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@gem_partial_pwrite_pread@writes-after-reads-snoop.html

  * igt@gem_partial_pwrite_pread@writes-after-reads-uncached:
    - shard-rkl:          [SKIP][261] ([i915#3282]) -> [SKIP][262] ([i915#14544] / [i915#3282]) +1 other test skip
   [261]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html
   [262]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@gem_partial_pwrite_pread@writes-after-reads-uncached.html

  * igt@gem_userptr_blits@invalid-mmap-offset-unsync:
    - shard-rkl:          [SKIP][263] ([i915#14544] / [i915#3297]) -> [SKIP][264] ([i915#3297])
   [263]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html
   [264]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@gem_userptr_blits@invalid-mmap-offset-unsync.html

  * igt@gen9_exec_parse@secure-batches:
    - shard-rkl:          [SKIP][265] ([i915#2527]) -> [SKIP][266] ([i915#14544] / [i915#2527]) +1 other test skip
   [265]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@gen9_exec_parse@secure-batches.html
   [266]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@gen9_exec_parse@secure-batches.html

  * igt@gen9_exec_parse@valid-registers:
    - shard-rkl:          [SKIP][267] ([i915#14544] / [i915#2527]) -> [SKIP][268] ([i915#2527]) +2 other tests skip
   [267]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@gen9_exec_parse@valid-registers.html
   [268]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@gen9_exec_parse@valid-registers.html

  * igt@i915_pm_freq_api@freq-suspend:
    - shard-rkl:          [SKIP][269] ([i915#8399]) -> [SKIP][270] ([i915#14544] / [i915#8399]) +1 other test skip
   [269]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@i915_pm_freq_api@freq-suspend.html
   [270]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@i915_pm_freq_api@freq-suspend.html

  * igt@i915_pm_freq_mult@media-freq@gt0:
    - shard-rkl:          [SKIP][271] ([i915#6590]) -> [SKIP][272] ([i915#14544] / [i915#6590]) +1 other test skip
   [271]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@i915_pm_freq_mult@media-freq@gt0.html
   [272]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@i915_pm_freq_mult@media-freq@gt0.html

  * igt@i915_pm_rc6_residency@media-rc6-accuracy:
    - shard-rkl:          [SKIP][273] -> [SKIP][274] ([i915#14544]) +15 other tests skip
   [273]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@i915_pm_rc6_residency@media-rc6-accuracy.html
   [274]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@i915_pm_rc6_residency@media-rc6-accuracy.html

  * igt@i915_query@test-query-geometry-subslices:
    - shard-rkl:          [SKIP][275] ([i915#5723]) -> [SKIP][276] ([i915#14544] / [i915#5723])
   [275]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@i915_query@test-query-geometry-subslices.html
   [276]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@i915_query@test-query-geometry-subslices.html

  * igt@intel_hwmon@hwmon-read:
    - shard-rkl:          [SKIP][277] ([i915#14544] / [i915#7707]) -> [SKIP][278] ([i915#7707])
   [277]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@intel_hwmon@hwmon-read.html
   [278]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@intel_hwmon@hwmon-read.html

  * igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels:
    - shard-rkl:          [SKIP][279] ([i915#14544] / [i915#1769] / [i915#3555]) -> [SKIP][280] ([i915#1769] / [i915#3555])
   [279]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html
   [280]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_atomic_transition@plane-all-modeset-transition-internal-panels.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-0:
    - shard-rkl:          [SKIP][281] ([i915#5286]) -> [SKIP][282] ([i915#14544] / [i915#5286]) +4 other tests skip
   [281]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html
   [282]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_big_fb@4-tiled-32bpp-rotate-0.html

  * igt@kms_big_fb@4-tiled-32bpp-rotate-180:
    - shard-rkl:          [SKIP][283] ([i915#14544] / [i915#5286]) -> [SKIP][284] ([i915#5286]) +1 other test skip
   [283]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_big_fb@4-tiled-32bpp-rotate-180.html
   [284]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_big_fb@4-tiled-32bpp-rotate-180.html

  * igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip:
    - shard-rkl:          [SKIP][285] ([i915#14544] / [i915#3828]) -> [SKIP][286] ([i915#3828])
   [285]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip.html
   [286]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_big_fb@linear-max-hw-stride-64bpp-rotate-0-hflip.html

  * igt@kms_big_fb@x-tiled-8bpp-rotate-270:
    - shard-rkl:          [SKIP][287] ([i915#14544] / [i915#3638]) -> [SKIP][288] ([i915#3638])
   [287]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html
   [288]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_big_fb@x-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-270:
    - shard-rkl:          [SKIP][289] ([i915#3638]) -> [SKIP][290] ([i915#14544] / [i915#3638]) +1 other test skip
   [289]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html
   [290]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_big_fb@y-tiled-64bpp-rotate-270.html

  * igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-2:
    - shard-rkl:          [SKIP][291] ([i915#6095]) -> [SKIP][292] ([i915#14544] / [i915#6095]) +17 other tests skip
   [291]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-2.html
   [292]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_ccs@bad-aux-stride-4-tiled-mtl-mc-ccs@pipe-a-hdmi-a-2.html

  * igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2:
    - shard-rkl:          [SKIP][293] ([i915#14098] / [i915#6095]) -> [SKIP][294] ([i915#14098] / [i915#14544] / [i915#6095]) +19 other tests skip
   [293]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2.html
   [294]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_ccs@bad-pixel-format-4-tiled-dg2-rc-ccs-cc@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs:
    - shard-rkl:          [SKIP][295] ([i915#12313] / [i915#14544]) -> [SKIP][296] ([i915#12313]) +1 other test skip
   [295]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html
   [296]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_ccs@bad-rotation-90-4-tiled-bmg-ccs.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs:
    - shard-rkl:          [SKIP][297] ([i915#12313]) -> [SKIP][298] ([i915#12313] / [i915#14544])
   [297]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html
   [298]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs.html

  * igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs:
    - shard-rkl:          [SKIP][299] ([i915#12805] / [i915#14544]) -> [SKIP][300] ([i915#12805])
   [299]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html
   [300]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_ccs@crc-primary-suspend-4-tiled-bmg-ccs.html

  * igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs:
    - shard-rkl:          [SKIP][301] ([i915#14098] / [i915#14544] / [i915#6095]) -> [SKIP][302] ([i915#14098] / [i915#6095]) +4 other tests skip
   [301]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html
   [302]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_ccs@crc-primary-suspend-yf-tiled-ccs.html

  * igt@kms_chamelium_frames@hdmi-frame-dump:
    - shard-rkl:          [SKIP][303] ([i915#11151] / [i915#7828]) -> [SKIP][304] ([i915#11151] / [i915#14544] / [i915#7828]) +5 other tests skip
   [303]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_chamelium_frames@hdmi-frame-dump.html
   [304]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_chamelium_frames@hdmi-frame-dump.html

  * igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode:
    - shard-rkl:          [SKIP][305] ([i915#11151] / [i915#14544] / [i915#7828]) -> [SKIP][306] ([i915#11151] / [i915#7828]) +6 other tests skip
   [305]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html
   [306]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_chamelium_hpd@dp-hpd-enable-disable-mode.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-dg2:          [FAIL][307] ([i915#7173]) -> [SKIP][308] ([i915#6944] / [i915#7118] / [i915#9424]) +1 other test skip
   [307]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg2-11/igt@kms_content_protection@atomic-dpms.html
   [308]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-6/igt@kms_content_protection@atomic-dpms.html
    - shard-rkl:          [SKIP][309] ([i915#14544] / [i915#6944] / [i915#7118] / [i915#9424]) -> [SKIP][310] ([i915#6944] / [i915#7118] / [i915#9424])
   [309]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_content_protection@atomic-dpms.html
   [310]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_content_protection@atomic-dpms.html

  * igt@kms_content_protection@atomic-dpms-hdcp14:
    - shard-dg2:          [SKIP][311] ([i915#6944]) -> [FAIL][312] ([i915#7173])
   [311]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg2-4/igt@kms_content_protection@atomic-dpms-hdcp14.html
   [312]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-11/igt@kms_content_protection@atomic-dpms-hdcp14.html
    - shard-rkl:          [SKIP][313] ([i915#6944]) -> [SKIP][314] ([i915#14544] / [i915#6944])
   [313]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_content_protection@atomic-dpms-hdcp14.html
   [314]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_content_protection@atomic-dpms-hdcp14.html

  * igt@kms_content_protection@dp-mst-type-1:
    - shard-rkl:          [SKIP][315] ([i915#15330] / [i915#3116]) -> [SKIP][316] ([i915#14544] / [i915#15330] / [i915#3116])
   [315]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_content_protection@dp-mst-type-1.html
   [316]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_content_protection@dp-mst-type-1.html

  * igt@kms_content_protection@lic-type-0-hdcp14:
    - shard-dg2:          [FAIL][317] ([i915#7173]) -> [SKIP][318] ([i915#6944])
   [317]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg2-11/igt@kms_content_protection@lic-type-0-hdcp14.html
   [318]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-5/igt@kms_content_protection@lic-type-0-hdcp14.html

  * igt@kms_content_protection@lic-type-1:
    - shard-rkl:          [SKIP][319] ([i915#14544] / [i915#6944] / [i915#9424]) -> [SKIP][320] ([i915#6944] / [i915#9424])
   [319]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_content_protection@lic-type-1.html
   [320]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_content_protection@lic-type-1.html

  * igt@kms_content_protection@type1:
    - shard-dg2:          [SKIP][321] ([i915#6944] / [i915#7118] / [i915#9424]) -> [SKIP][322] ([i915#6944] / [i915#7118] / [i915#7162] / [i915#9424])
   [321]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg2-6/igt@kms_content_protection@type1.html
   [322]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-11/igt@kms_content_protection@type1.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-rkl:          [SKIP][323] ([i915#13049] / [i915#14544]) -> [SKIP][324] ([i915#13049])
   [323]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_cursor_crc@cursor-offscreen-512x170.html
   [324]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-onscreen-32x32:
    - shard-rkl:          [SKIP][325] ([i915#14544] / [i915#3555]) -> [SKIP][326] ([i915#3555]) +1 other test skip
   [325]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_cursor_crc@cursor-onscreen-32x32.html
   [326]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_cursor_crc@cursor-onscreen-32x32.html

  * igt@kms_cursor_crc@cursor-rapid-movement-32x10:
    - shard-rkl:          [SKIP][327] ([i915#3555]) -> [SKIP][328] ([i915#14544] / [i915#3555]) +3 other tests skip
   [327]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html
   [328]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_cursor_crc@cursor-rapid-movement-32x10.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-rkl:          [SKIP][329] ([i915#14544]) -> [SKIP][330] +11 other tests skip
   [329]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
   [330]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - shard-rkl:          [SKIP][331] ([i915#4103]) -> [SKIP][332] ([i915#14544] / [i915#4103]) +1 other test skip
   [331]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
   [332]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
    - shard-rkl:          [SKIP][333] ([i915#14544] / [i915#4103]) -> [SKIP][334] ([i915#4103])
   [333]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
   [334]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc:
    - shard-rkl:          [SKIP][335] ([i915#3555] / [i915#3804]) -> [SKIP][336] ([i915#14544] / [i915#3555] / [i915#3804])
   [335]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
   [336]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2:
    - shard-rkl:          [SKIP][337] ([i915#3804]) -> [SKIP][338] ([i915#14544] / [i915#3804])
   [337]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html
   [338]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-2.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-rkl:          [SKIP][339] ([i915#13748]) -> [SKIP][340] ([i915#13748] / [i915#14544])
   [339]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_dp_link_training@uhbr-sst.html
   [340]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_dp_linktrain_fallback@dp-fallback:
    - shard-rkl:          [SKIP][341] ([i915#13707]) -> [SKIP][342] ([i915#13707] / [i915#14544])
   [341]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_dp_linktrain_fallback@dp-fallback.html
   [342]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_dp_linktrain_fallback@dp-fallback.html

  * igt@kms_dsc@dsc-with-output-formats:
    - shard-rkl:          [SKIP][343] ([i915#3555] / [i915#3840]) -> [SKIP][344] ([i915#14544] / [i915#3555] / [i915#3840])
   [343]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_dsc@dsc-with-output-formats.html
   [344]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_dsc@dsc-with-output-formats.html

  * igt@kms_feature_discovery@chamelium:
    - shard-rkl:          [SKIP][345] ([i915#14544] / [i915#4854]) -> [SKIP][346] ([i915#4854])
   [345]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_feature_discovery@chamelium.html
   [346]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_feature_discovery@chamelium.html

  * igt@kms_feature_discovery@dp-mst:
    - shard-rkl:          [SKIP][347] ([i915#14544] / [i915#9337]) -> [SKIP][348] ([i915#9337])
   [347]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_feature_discovery@dp-mst.html
   [348]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_feature_discovery@dp-mst.html

  * igt@kms_feature_discovery@psr1:
    - shard-rkl:          [SKIP][349] ([i915#14544] / [i915#658]) -> [SKIP][350] ([i915#658])
   [349]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_feature_discovery@psr1.html
   [350]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_feature_discovery@psr1.html

  * igt@kms_feature_discovery@psr2:
    - shard-rkl:          [SKIP][351] ([i915#658]) -> [SKIP][352] ([i915#14544] / [i915#658])
   [351]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_feature_discovery@psr2.html
   [352]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_feature_discovery@psr2.html

  * igt@kms_flip@2x-flip-vs-dpms:
    - shard-rkl:          [SKIP][353] ([i915#9934]) -> [SKIP][354] ([i915#14544] / [i915#9934]) +7 other tests skip
   [353]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_flip@2x-flip-vs-dpms.html
   [354]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_flip@2x-flip-vs-dpms.html

  * igt@kms_flip@2x-plain-flip:
    - shard-rkl:          [SKIP][355] ([i915#14544] / [i915#9934]) -> [SKIP][356] ([i915#9934]) +3 other tests skip
   [355]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_flip@2x-plain-flip.html
   [356]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_flip@2x-plain-flip.html

  * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling:
    - shard-rkl:          [SKIP][357] ([i915#15643]) -> [SKIP][358] ([i915#14544] / [i915#15643])
   [357]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html
   [358]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-64bpp-4tile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling:
    - shard-rkl:          [SKIP][359] ([i915#14544] / [i915#15643]) -> [SKIP][360] ([i915#15643]) +3 other tests skip
   [359]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html
   [360]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_flip_scaled_crc@flip-64bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-render:
    - shard-rkl:          [SKIP][361] ([i915#15102]) -> [SKIP][362] ([i915#14544] / [i915#15102])
   [361]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-render.html
   [362]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscreen-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu:
    - shard-dg2:          [SKIP][363] ([i915#15102] / [i915#3458]) -> [SKIP][364] ([i915#10433] / [i915#15102] / [i915#3458]) +1 other test skip
   [363]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg2-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu.html
   [364]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-mmap-cpu.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt:
    - shard-rkl:          [SKIP][365] ([i915#1825]) -> [SKIP][366] ([i915#14544] / [i915#1825]) +26 other tests skip
   [365]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html
   [366]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-pwrite:
    - shard-dg1:          [SKIP][367] ([i915#15102]) -> [SKIP][368] ([i915#15102] / [i915#4423])
   [367]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg1-18/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-pwrite.html
   [368]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg1-12/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-blt:
    - shard-rkl:          [SKIP][369] ([i915#14544] / [i915#15102]) -> [SKIP][370] ([i915#15102]) +1 other test skip
   [369]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-blt.html
   [370]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-1p-offscreen-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
    - shard-rkl:          [SKIP][371] ([i915#15102] / [i915#3023]) -> [SKIP][372] ([i915#14544] / [i915#15102] / [i915#3023]) +10 other tests skip
   [371]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html
   [372]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt:
    - shard-dg2:          [SKIP][373] ([i915#10433] / [i915#15102] / [i915#3458]) -> [SKIP][374] ([i915#15102] / [i915#3458])
   [373]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg2-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html
   [374]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt:
    - shard-rkl:          [SKIP][375] ([i915#14544] / [i915#1825]) -> [SKIP][376] ([i915#1825]) +23 other tests skip
   [375]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html
   [376]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-indfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
    - shard-rkl:          [SKIP][377] ([i915#14544] / [i915#15102] / [i915#3023]) -> [SKIP][378] ([i915#15102] / [i915#3023]) +11 other tests skip
   [377]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html
   [378]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html

  * igt@kms_hdr@brightness-with-hdr:
    - shard-rkl:          [SKIP][379] ([i915#12713]) -> [SKIP][380] ([i915#13331])
   [379]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-7/igt@kms_hdr@brightness-with-hdr.html
   [380]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-1/igt@kms_hdr@brightness-with-hdr.html

  * igt@kms_hdr@invalid-hdr:
    - shard-rkl:          [SKIP][381] ([i915#3555] / [i915#8228]) -> [SKIP][382] ([i915#14544] / [i915#3555] / [i915#8228])
   [381]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_hdr@invalid-hdr.html
   [382]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_hdr@invalid-hdr.html

  * igt@kms_joiner@invalid-modeset-big-joiner:
    - shard-rkl:          [SKIP][383] ([i915#14544] / [i915#15460]) -> [SKIP][384] ([i915#15460])
   [383]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_joiner@invalid-modeset-big-joiner.html
   [384]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_joiner@invalid-modeset-big-joiner.html

  * igt@kms_panel_fitting@atomic-fastset:
    - shard-rkl:          [SKIP][385] ([i915#6301]) -> [SKIP][386] ([i915#14544] / [i915#6301])
   [385]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_panel_fitting@atomic-fastset.html
   [386]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_panel_fitting@atomic-fastset.html

  * igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier:
    - shard-rkl:          [SKIP][387] ([i915#15709]) -> [SKIP][388] ([i915#14544] / [i915#15709])
   [387]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier.html
   [388]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_plane@pixel-format-4-tiled-mtl-rc-ccs-cc-modifier.html

  * igt@kms_plane@pixel-format-yf-tiled-modifier:
    - shard-rkl:          [SKIP][389] ([i915#14544]) -> [SKIP][390] ([i915#15709]) +3 other tests skip
   [389]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_plane@pixel-format-yf-tiled-modifier.html
   [390]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_plane@pixel-format-yf-tiled-modifier.html

  * igt@kms_plane_multiple@2x-tiling-x:
    - shard-rkl:          [SKIP][391] ([i915#13958]) -> [SKIP][392] ([i915#13958] / [i915#14544])
   [391]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_plane_multiple@2x-tiling-x.html
   [392]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_plane_multiple@2x-tiling-x.html

  * igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-b:
    - shard-rkl:          [SKIP][393] ([i915#14544] / [i915#15329]) -> [SKIP][394] ([i915#15329]) +3 other tests skip
   [393]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-b.html
   [394]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_plane_scaling@plane-scaler-unity-scaling-with-rotation@pipe-b.html

  * igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a:
    - shard-rkl:          [SKIP][395] ([i915#15329]) -> [SKIP][396] ([i915#14544] / [i915#15329]) +7 other tests skip
   [395]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a.html
   [396]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_plane_scaling@plane-upscale-20x20-with-rotation@pipe-a.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-rkl:          [SKIP][397] ([i915#12343] / [i915#14544]) -> [SKIP][398] ([i915#12343])
   [397]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_pm_backlight@brightness-with-dpms.html
   [398]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_dc@dc6-psr:
    - shard-rkl:          [SKIP][399] ([i915#9685]) -> [SKIP][400] ([i915#14544] / [i915#9685])
   [399]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_pm_dc@dc6-psr.html
   [400]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_pm_dc@dc6-psr.html

  * igt@kms_pm_dc@dc9-dpms:
    - shard-tglu:         [SKIP][401] -> [SKIP][402] ([i915#15128])
   [401]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-tglu-4/igt@kms_pm_dc@dc9-dpms.html
   [402]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-tglu-6/igt@kms_pm_dc@dc9-dpms.html

  * igt@kms_pm_lpsp@kms-lpsp:
    - shard-rkl:          [SKIP][403] ([i915#9340]) -> [SKIP][404] ([i915#14544] / [i915#9340])
   [403]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_pm_lpsp@kms-lpsp.html
   [404]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_pm_lpsp@kms-lpsp.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf:
    - shard-rkl:          [SKIP][405] ([i915#11520]) -> [SKIP][406] ([i915#11520] / [i915#14544]) +5 other tests skip
   [405]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html
   [406]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-rkl:          [SKIP][407] ([i915#11520] / [i915#14544]) -> [SKIP][408] ([i915#11520]) +4 other tests skip
   [407]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html
   [408]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_psr2_sf@fbc-psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-rkl:          [SKIP][409] ([i915#14544] / [i915#9683]) -> [SKIP][410] ([i915#9683])
   [409]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_psr2_su@page_flip-xrgb8888.html
   [410]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-psr-cursor-plane-move:
    - shard-rkl:          [SKIP][411] ([i915#1072] / [i915#14544] / [i915#9732]) -> [SKIP][412] ([i915#1072] / [i915#9732]) +12 other tests skip
   [411]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_psr@fbc-psr-cursor-plane-move.html
   [412]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_psr@fbc-psr-cursor-plane-move.html

  * igt@kms_psr@fbc-psr2-primary-blt:
    - shard-rkl:          [SKIP][413] ([i915#1072] / [i915#9732]) -> [SKIP][414] ([i915#1072] / [i915#14544] / [i915#9732]) +12 other tests skip
   [413]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_psr@fbc-psr2-primary-blt.html
   [414]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_psr@fbc-psr2-primary-blt.html

  * igt@kms_psr@fbc-psr2-primary-page-flip:
    - shard-dg1:          [SKIP][415] ([i915#1072] / [i915#4423] / [i915#9732]) -> [SKIP][416] ([i915#1072] / [i915#9732])
   [415]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-dg1-18/igt@kms_psr@fbc-psr2-primary-page-flip.html
   [416]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-dg1-12/igt@kms_psr@fbc-psr2-primary-page-flip.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - shard-rkl:          [SKIP][417] ([i915#14544] / [i915#9685]) -> [SKIP][418] ([i915#9685])
   [417]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
   [418]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
    - shard-rkl:          [SKIP][419] ([i915#5289]) -> [SKIP][420] ([i915#14544] / [i915#5289])
   [419]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html
   [420]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html

  * igt@kms_vrr@flipline:
    - shard-rkl:          [SKIP][421] ([i915#15243] / [i915#3555]) -> [SKIP][422] ([i915#14544] / [i915#15243] / [i915#3555])
   [421]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_vrr@flipline.html
   [422]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_vrr@flipline.html

  * igt@kms_vrr@lobf:
    - shard-rkl:          [SKIP][423] ([i915#11920] / [i915#14544]) -> [SKIP][424] ([i915#11920])
   [423]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@kms_vrr@lobf.html
   [424]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-5/igt@kms_vrr@lobf.html

  * igt@kms_vrr@negative-basic:
    - shard-rkl:          [SKIP][425] ([i915#3555] / [i915#9906]) -> [SKIP][426] ([i915#14544] / [i915#3555] / [i915#9906])
   [425]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_vrr@negative-basic.html
   [426]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_vrr@negative-basic.html

  * igt@kms_vrr@seamless-rr-switch-drrs:
    - shard-rkl:          [SKIP][427] ([i915#9906]) -> [SKIP][428] ([i915#14544] / [i915#9906])
   [427]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@kms_vrr@seamless-rr-switch-drrs.html
   [428]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@kms_vrr@seamless-rr-switch-drrs.html

  * igt@perf@per-context-mode-unprivileged:
    - shard-rkl:          [SKIP][429] ([i915#14544] / [i915#2435]) -> [SKIP][430] ([i915#2435])
   [429]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-6/igt@perf@per-context-mode-unprivileged.html
   [430]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-2/igt@perf@per-context-mode-unprivileged.html

  * igt@perf@unprivileged-single-ctx-counters:
    - shard-rkl:          [SKIP][431] ([i915#2433]) -> [SKIP][432] ([i915#14544] / [i915#2433])
   [431]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@perf@unprivileged-single-ctx-counters.html
   [432]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@perf@unprivileged-single-ctx-counters.html

  * igt@perf_pmu@rc6-suspend:
    - shard-rkl:          [INCOMPLETE][433] ([i915#13520]) -> [ABORT][434] ([i915#15131])
   [433]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-3/igt@perf_pmu@rc6-suspend.html
   [434]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-1/igt@perf_pmu@rc6-suspend.html

  * igt@prime_vgem@basic-fence-read:
    - shard-rkl:          [SKIP][435] ([i915#3291] / [i915#3708]) -> [SKIP][436] ([i915#14544] / [i915#3291] / [i915#3708])
   [435]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_18006/shard-rkl-4/igt@prime_vgem@basic-fence-read.html
   [436]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/shard-rkl-6/igt@prime_vgem@basic-fence-read.html

  
  [i915#10307]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10307
  [i915#10433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10433
  [i915#10434]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10434
  [i915#1072]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1072
  [i915#11078]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11078
  [i915#11151]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11151
  [i915#11520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11520
  [i915#11920]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/11920
  [i915#12061]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12061
  [i915#12178]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12178
  [i915#12313]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12313
  [i915#12314]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12314
  [i915#12343]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12343
  [i915#1257]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1257
  [i915#12713]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12713
  [i915#12745]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12745
  [i915#12756]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12756
  [i915#12761]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12761
  [i915#12805]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12805
  [i915#12910]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12910
  [i915#13027]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13027
  [i915#13028]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13028
  [i915#13049]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13049
  [i915#13179]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13179
  [i915#13331]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13331
  [i915#13356]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13356
  [i915#13390]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13390
  [i915#13476]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13476
  [i915#13520]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13520
  [i915#13566]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13566
  [i915#13707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13707
  [i915#13729]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13729
  [i915#13748]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13748
  [i915#13781]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13781
  [i915#13809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13809
  [i915#13821]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13821
  [i915#13958]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/13958
  [i915#14098]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14098
  [i915#14419]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14419
  [i915#14433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14433
  [i915#14544]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14544
  [i915#14712]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14712
  [i915#14809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/14809
  [i915#15073]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15073
  [i915#15102]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15102
  [i915#15106]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15106
  [i915#15128]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15128
  [i915#15131]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15131
  [i915#15243]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15243
  [i915#15329]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15329
  [i915#15330]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15330
  [i915#15389]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15389
  [i915#15403]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15403
  [i915#15458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15458
  [i915#15459]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15459
  [i915#15460]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15460
  [i915#15492]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15492
  [i915#15560]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15560
  [i915#15608]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15608
  [i915#15638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15638
  [i915#15643]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15643
  [i915#15709]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/15709
  [i915#1769]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1769
  [i915#1825]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/1839
  [i915#2433]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2433
  [i915#2435]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2435
  [i915#2436]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2436
  [i915#2527]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2527
  [i915#2658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2658
  [i915#280]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/280
  [i915#2856]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2856
  [i915#3023]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3023
  [i915#3116]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3116
  [i915#3281]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3282
  [i915#3291]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3291
  [i915#3297]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3297
  [i915#3323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3323
  [i915#3458]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3458
  [i915#3469]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3469
  [i915#3555]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3555
  [i915#3637]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3638
  [i915#3708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3708
  [i915#3742]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3742
  [i915#3778]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3778
  [i915#3804]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3804
  [i915#3828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3828
  [i915#3840]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/3840
  [i915#4083]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4083
  [i915#4103]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4103
  [i915#4349]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4349
  [i915#4387]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4387
  [i915#4391]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4391
  [i915#4423]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4423
  [i915#4525]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4525
  [i915#4613]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4613
  [i915#4816]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4816
  [i915#4817]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4817
  [i915#4839]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4839
  [i915#4854]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4854
  [i915#5138]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5138
  [i915#5286]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5286
  [i915#5289]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5289
  [i915#5439]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5439
  [i915#5723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5723
  [i915#5956]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/5956
  [i915#6095]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6095
  [i915#6113]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6113
  [i915#6301]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6301
  [i915#6334]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6334
  [i915#6335]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6335
  [i915#6344]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6344
  [i915#6412]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6412
  [i915#658]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/658
  [i915#6590]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6590
  [i915#6880]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6880
  [i915#6944]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/6944
  [i915#7016]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7016
  [i915#7118]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7118
  [i915#7162]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7162
  [i915#7173]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7173
  [i915#7582]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7582
  [i915#7697]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7697
  [i915#7707]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7707
  [i915#7828]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7828
  [i915#7862]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/7862
  [i915#8228]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8228
  [i915#8399]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8399
  [i915#8411]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8411
  [i915#8428]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8428
  [i915#8430]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8430
  [i915#8562]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8562
  [i915#8708]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/8708
  [i915#9053]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9053
  [i915#9323]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9323
  [i915#9337]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9337
  [i915#9340]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9340
  [i915#9424]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9424
  [i915#9561]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9561
  [i915#9683]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9683
  [i915#9685]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9685
  [i915#9688]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9688
  [i915#9723]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9723
  [i915#9732]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9732
  [i915#9809]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9809
  [i915#9906]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9906
  [i915#9934]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9934


Build changes
-------------

  * Linux: CI_DRM_18006 -> Patchwork_161836v1

  CI-20190529: 20190529
  CI_DRM_18006: c81e41f7aca96f583296a2a875f0179484b7a81f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_8761: 8761
  Patchwork_161836v1: c81e41f7aca96f583296a2a875f0179484b7a81f @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_161836v1/index.html

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