Intel-GFX Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: "Belgaumkar, Vinay" <vinay.belgaumkar@intel.com>
To: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>,
	"Dixit, Ashutosh" <ashutosh.dixit@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 14/15] drm/i915/guc: Support OA when Wa_16011777198 is enabled
Date: Mon, 26 Sep 2022 14:17:21 -0700	[thread overview]
Message-ID: <53226382-9d11-abdf-e907-a972a8f2e535@intel.com> (raw)
In-Reply-To: <YzHtF8QESFmQOBhv@unerlige-ril>


On 9/26/2022 11:19 AM, Umesh Nerlige Ramappa wrote:
> On Mon, Sep 26, 2022 at 08:56:01AM -0700, Dixit, Ashutosh wrote:
>> On Fri, 23 Sep 2022 13:11:53 -0700, Umesh Nerlige Ramappa wrote:
>>>
>>> From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
>>
>> Hi Umesh/Vinay,
>>
>>> @@ -3254,6 +3265,24 @@ static int i915_oa_stream_init(struct 
>>> i915_perf_stream *stream,
>>>     intel_engine_pm_get(stream->engine);
>>>     intel_uncore_forcewake_get(stream->uncore, FORCEWAKE_ALL);
>>>
>>> +    /*
>>> +     * Wa_16011777198:dg2: GuC resets render as part of the Wa. 
>>> This causes
>>> +     * OA to lose the configuration state. Prevent this by 
>>> overriding GUCRC
>>> +     * mode.
>>> +     */
>>> +    if (intel_guc_slpc_is_used(&gt->uc.guc) &&
>>> +        intel_uc_uses_guc_rc(&gt->uc) &&
>>
>> Is this condition above correct? E.g. what happens when:
>>
>> a. GuCRC is used but SLPC is not used?

Currently, we have no way to separate out GuC RC and SLPC. Both are on 
when guc submission is enabled/supported. So, the above check is kind of 
redundant anyways.

Thanks,

Vinay.

>> b. GuCRC is not used. Don't we need to disable RC6 in host based RC6
>>   control?
>
> When using host based rc6, existing OA code is using forcewake and a 
> reference to engine_pm to prevent rc6. Other questions, directing to 
> @Vinay.
>
> Thanks,
> Umesh
>
>>
>> Do we need to worry about these cases?
>>
>> Or if we always expect both GuCRC and SLPC to be used on DG2 then I 
>> think
>> let's get rid of these from the if condition and add a drm_err() if 
>> we see
>> these not being used and OA is being enabled on DG2?
>>
>> Thanks.
>> -- 
>> Ashutosh
>>
>>> + (IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
>>> +         IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))) {
>>> +        ret = intel_guc_slpc_override_gucrc_mode(&gt->uc.guc.slpc,
>>> +                             SLPC_GUCRC_MODE_GUCRC_NO_RC6);
>>> +        if (ret) {
>>> +            drm_dbg(&stream->perf->i915->drm,
>>> +                "Unable to override gucrc mode\n");
>>> +            goto err_config;
>>> +        }
>>> +    }
>>> +
>>>     ret = alloc_oa_buffer(stream);
>>>     if (ret)
>>>         goto err_oa_buf_alloc;
>>> -- 
>>> 2.25.1
>>>

  reply	other threads:[~2022-09-26 21:17 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-23 20:11 [Intel-gfx] [PATCH v2 00/15] Add DG2 OA support Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 01/15] drm/i915/perf: Fix OA filtering logic for GuC mode Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 02/15] drm/i915/perf: Add OAG and OAR formats for DG2 Umesh Nerlige Ramappa
2022-09-24  4:08   ` Dixit, Ashutosh
2022-09-26 18:11     ` Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 03/15] drm/i915/perf: Fix noa wait predication " Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 04/15] drm/i915/perf: Determine gen12 oa ctx offset at runtime Umesh Nerlige Ramappa
2022-09-27 23:24   ` Dixit, Ashutosh
2022-09-30 21:42     ` Umesh Nerlige Ramappa
2022-09-30 23:09       ` Dixit, Ashutosh
2022-10-08  1:06         ` Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 05/15] drm/i915/perf: Enable commands per clock reporting in OA Umesh Nerlige Ramappa
2022-09-26 15:55   ` Dixit, Ashutosh
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 06/15] drm/i915/perf: Simply use stream->ctx Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 07/15] drm/i915/perf: Move gt-specific data from i915->perf to gt->perf Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 08/15] drm/i915/perf: Replace gt->perf.lock with stream->lock for file ops Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 09/15] drm/i915/perf: Use gt-specific ggtt for OA and noa-wait buffers Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 10/15] drm/i915/perf: Store a pointer to oa_format in oa_buffer Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 11/15] drm/i915/perf: Add Wa_1508761755:dg2 Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 12/15] drm/i915/perf: Apply Wa_18013179988 Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 13/15] drm/i915/perf: Save/restore EU flex counters across reset Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 14/15] drm/i915/guc: Support OA when Wa_16011777198 is enabled Umesh Nerlige Ramappa
2022-09-26 15:56   ` Dixit, Ashutosh
2022-09-26 18:19     ` Umesh Nerlige Ramappa
2022-09-26 21:17       ` Belgaumkar, Vinay [this message]
2022-09-26 23:28         ` Dixit, Ashutosh
2022-09-27 16:11           ` Umesh Nerlige Ramappa
2022-09-27 17:34             ` Dixit, Ashutosh
2022-09-27 17:51               ` Dixit, Ashutosh
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 15/15] drm/i915/perf: Enable OA for DG2 Umesh Nerlige Ramappa
2022-09-23 21:44 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DG2 OA support (rev3) Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=53226382-9d11-abdf-e907-a972a8f2e535@intel.com \
    --to=vinay.belgaumkar@intel.com \
    --cc=ashutosh.dixit@intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=umesh.nerlige.ramappa@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox