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From: "Dixit, Ashutosh" <ashutosh.dixit@intel.com>
To: Umesh Nerlige Ramappa <umesh.nerlige.ramappa@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 04/15] drm/i915/perf: Determine gen12 oa ctx offset at runtime
Date: Fri, 30 Sep 2022 16:09:36 -0700	[thread overview]
Message-ID: <87leq0zcgf.wl-ashutosh.dixit@intel.com> (raw)
In-Reply-To: <Yzdir5tLSvx/VKET@unerlige-ril>

On Fri, 30 Sep 2022 14:42:07 -0700, Umesh Nerlige Ramappa wrote:
>
> >> +static int __set_oa_ctx_ctrl_offset(struct intel_context *ce)
> >
> > I have seen people complain about unnecessary double underscores in front
> > of function names ;-)
>
> will remove/change to oa_*.
>
> >
> >> +{
> >> +	i915_reg_t reg = GEN12_OACTXCONTROL(ce->engine->mmio_base);
> >> +	struct i915_perf *perf = &ce->engine->i915->perf;
> >> +	u32 saved_offset = perf->ctx_oactxctrl_offset;
> >> +	u32 offset;
> >> +
> >> +	/* Do this only once. Failure is stored as offset of U32_MAX */
> >> +	if (saved_offset)
> >> +		return 0;
> >
> > But if saved_offset is U32_MAX we should be returning -ENODEV?
>
> correct, the above if block should be:
>
> if (__valid_oactxctrl_offset(offset))
>	return 0;
>
> if (saved_offset == U32_MAX)
>	return -ENODEV;

I would just do:

	u32 offset = perf->ctx_oactxctrl_offset;

	if (offset)
		goto exit;

	...
exit:
	return __valid_oactxctrl_offset(offset) ? 0 : -ENODEV;
}

>
> >
> >> +
> >> +	offset = __context_image_offset(ce, i915_mmio_reg_offset(reg));
> >> +	perf->ctx_oactxctrl_offset = offset;
> >> +
> >> +	drm_dbg(&ce->engine->i915->drm,
> >> +		"%s oa ctx control at 0x%08x dword offset\n",
> >> +		ce->engine->name, offset);
> >> +
> >> +	return __valid_oactxctrl_offset(offset) ? 0 : -ENODEV;
> >> +}
> >> +
> >> +static bool engine_supports_mi_query(struct intel_engine_cs *engine)
> >> +{
> >> +	return engine->class == RENDER_CLASS;
> >> +}
> >> +
> >>  /**
> >>   * oa_get_render_ctx_id - determine and hold ctx hw id
> >>   * @stream: An i915-perf stream opened for OA metrics
> >> @@ -1377,6 +1435,17 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
> >>	if (IS_ERR(ce))
> >>		return PTR_ERR(ce);
> >>
> >> +	if (engine_supports_mi_query(stream->engine)) {
> >> +		ret = __set_oa_ctx_ctrl_offset(ce);
> >> +		if (ret && !(stream->sample_flags & SAMPLE_OA_REPORT)) {
> >
> > This is not a problem in SAMPLE_OA_REPORT case?
>
> SAMPLE_OA_REPORT is OAG use case.
>
> Actually, I did not know how to treat this condition. The current interface
> will configure both OAR and OAG. If we have an error configuring OAR,
> should we fail or let the OAG use case work?
>
> I am now leaning towards failing this unconditionally. Thoughts?

Sorry I didn't follow. What does the oa_ctx_ctrl_offset in the context
image do or control? Looks like oa_ctx_ctrl register controls the OA HW
timer which dumps data into the OA buffer so should be programmed correctly
for OAG (and possibly also for OAR). So maybe letting this fail
unconditionally is correct? But I am not sure.

Thanks.
--
Ashutosh

  reply	other threads:[~2022-09-30 23:09 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-23 20:11 [Intel-gfx] [PATCH v2 00/15] Add DG2 OA support Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 01/15] drm/i915/perf: Fix OA filtering logic for GuC mode Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 02/15] drm/i915/perf: Add OAG and OAR formats for DG2 Umesh Nerlige Ramappa
2022-09-24  4:08   ` Dixit, Ashutosh
2022-09-26 18:11     ` Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 03/15] drm/i915/perf: Fix noa wait predication " Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 04/15] drm/i915/perf: Determine gen12 oa ctx offset at runtime Umesh Nerlige Ramappa
2022-09-27 23:24   ` Dixit, Ashutosh
2022-09-30 21:42     ` Umesh Nerlige Ramappa
2022-09-30 23:09       ` Dixit, Ashutosh [this message]
2022-10-08  1:06         ` Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 05/15] drm/i915/perf: Enable commands per clock reporting in OA Umesh Nerlige Ramappa
2022-09-26 15:55   ` Dixit, Ashutosh
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 06/15] drm/i915/perf: Simply use stream->ctx Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 07/15] drm/i915/perf: Move gt-specific data from i915->perf to gt->perf Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 08/15] drm/i915/perf: Replace gt->perf.lock with stream->lock for file ops Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 09/15] drm/i915/perf: Use gt-specific ggtt for OA and noa-wait buffers Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 10/15] drm/i915/perf: Store a pointer to oa_format in oa_buffer Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 11/15] drm/i915/perf: Add Wa_1508761755:dg2 Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 12/15] drm/i915/perf: Apply Wa_18013179988 Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 13/15] drm/i915/perf: Save/restore EU flex counters across reset Umesh Nerlige Ramappa
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 14/15] drm/i915/guc: Support OA when Wa_16011777198 is enabled Umesh Nerlige Ramappa
2022-09-26 15:56   ` Dixit, Ashutosh
2022-09-26 18:19     ` Umesh Nerlige Ramappa
2022-09-26 21:17       ` Belgaumkar, Vinay
2022-09-26 23:28         ` Dixit, Ashutosh
2022-09-27 16:11           ` Umesh Nerlige Ramappa
2022-09-27 17:34             ` Dixit, Ashutosh
2022-09-27 17:51               ` Dixit, Ashutosh
2022-09-23 20:11 ` [Intel-gfx] [PATCH v2 15/15] drm/i915/perf: Enable OA for DG2 Umesh Nerlige Ramappa
2022-09-23 21:44 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DG2 OA support (rev3) Patchwork

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