Re: [PATCH v8 4/5] drm/i915/irq: conditional HPD IRQ resets based on PME capability

["Hogander, Jouni" <jouni.hogander@intel.com>]

On Tue, 2026-09-15 at 12:25 +0300, Vinod Govindapillai wrote:
> If a device supports generating PME from HPDs, resetting HPD IRQs
> will be counter productive as HPDs itself will be lost. During
> suspend routines, all the IRQs are reset. So if the device is
> capable of generating PME rom HPDs, keep the HPD related IRQs from
> reset based on the PME capability of the device on a target power
> state. PME capability will be assessed and updated separately.
> 
> v2: change keep_hpd to reset_hpd
> 
> v3: use intel_display_rpm_pme_enabled() directly (JaniN)
> 
> v4: remove the unused include file from the previous revision
> 
> Bspec: 52979, 52980, 68857, 68867, 68970
> Assisted-by: GitHub_Copilot:claude-opus-5
> Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>

Reviewed-by: Jouni Högander <jouni.hogander@intel.com>

> ---
>  .../gpu/drm/i915/display/intel_display_irq.c   | 18 +++++++++++-----
> --
>  1 file changed, 11 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
> b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index a59b75830bd1..8ce30112de97 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -2217,8 +2217,10 @@ static void gen11_display_irq_reset(struct
> intel_display *display)
>  	enum pipe pipe;
>  	u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
>  		BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
> +	bool reset_hpd = !intel_display_rpm_pme_enabled(display);
>  
> -	intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0);
> +	if (reset_hpd)
> +		intel_de_write(display, GEN11_DISPLAY_INT_CTL, 0);
>  
>  	if (DISPLAY_VER(display) >= 12) {
>  		enum transcoder trans;
> @@ -2250,13 +2252,15 @@ static void gen11_display_irq_reset(struct
> intel_display *display)
>  	irq_reset(display, GEN8_DE_PORT_IRQ_REGS);
>  	irq_reset(display, GEN8_DE_MISC_IRQ_REGS);
>  
> -	if (DISPLAY_VER(display) >= 14)
> -		irq_reset(display, PICAINTERRUPT_IRQ_REGS);
> -	else
> -		irq_reset(display, GEN11_DE_HPD_IRQ_REGS);
> +	if (reset_hpd) {
> +		if (DISPLAY_VER(display) >= 14)
> +			irq_reset(display, PICAINTERRUPT_IRQ_REGS);
> +		else
> +			irq_reset(display, GEN11_DE_HPD_IRQ_REGS);
>  
> -	if (INTEL_PCH_TYPE(display) >= PCH_ICP)
> -		irq_reset(display, SDE_IRQ_REGS);
> +		if (INTEL_PCH_TYPE(display) >= PCH_ICP)
> +			irq_reset(display, SDE_IRQ_REGS);
> +	}
>  }
>  
>  void gen8_irq_power_well_post_enable(struct intel_display *display,