* [PATCH] drm/i915: Read power well status before other registers for drpc info
@ 2014-11-19 18:07 ville.syrjala
2014-11-21 3:26 ` Deepak S
2014-11-21 4:58 ` [PATCH] drm/i915: Read power well status before other shuang.he
0 siblings, 2 replies; 4+ messages in thread
From: ville.syrjala @ 2014-11-19 18:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Deepak S
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Trying to read the status of the power wells right after taking forcewake
for the other register reads makes little sense. Most of the time the
power wells will still be up due to the recent forcewake. Instead do the
power well status read first, and only then read the register needing
forcewake. This way the reported power well status can actually reflect
what's going on in the system.
Cc: Deepak S <deepak.s@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 9 ++++-----
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 319da61..2d4f870 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1240,11 +1240,12 @@ static int vlv_drpc_info(struct seq_file *m)
struct drm_info_node *node = m->private;
struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- u32 rpmodectl1, rcctl1;
+ u32 rpmodectl1, rcctl1, pw_status;
unsigned fw_rendercount = 0, fw_mediacount = 0;
intel_runtime_pm_get(dev_priv);
+ pw_status = I915_READ(VLV_GTLC_PW_STATUS);
rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
rcctl1 = I915_READ(GEN6_RC_CONTROL);
@@ -1263,11 +1264,9 @@ static int vlv_drpc_info(struct seq_file *m)
yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
GEN6_RC_CTL_EI_MODE(1))));
seq_printf(m, "Render Power Well: %s\n",
- (I915_READ(VLV_GTLC_PW_STATUS) &
- VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
+ (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
seq_printf(m, "Media Power Well: %s\n",
- (I915_READ(VLV_GTLC_PW_STATUS) &
- VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
+ (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
seq_printf(m, "Render RC6 residency since boot: %u\n",
I915_READ(VLV_GT_RENDER_RC6));
--
2.0.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915: Read power well status before other registers for drpc info
2014-11-21 3:26 ` Deepak S
@ 2014-11-20 9:26 ` Daniel Vetter
0 siblings, 0 replies; 4+ messages in thread
From: Daniel Vetter @ 2014-11-20 9:26 UTC (permalink / raw)
To: Deepak S; +Cc: intel-gfx
On Fri, Nov 21, 2014 at 08:56:02AM +0530, Deepak S wrote:
>
> On Wednesday 19 November 2014 11:37 PM, ville.syrjala@linux.intel.com wrote:
> >From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> >Trying to read the status of the power wells right after taking forcewake
> >for the other register reads makes little sense. Most of the time the
> >power wells will still be up due to the recent forcewake. Instead do the
> >power well status read first, and only then read the register needing
> >forcewake. This way the reported power well status can actually reflect
> >what's going on in the system.
> >
> >Cc: Deepak S <deepak.s@intel.com>
> >Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >---
> > drivers/gpu/drm/i915/i915_debugfs.c | 9 ++++-----
> > 1 file changed, 4 insertions(+), 5 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> >index 319da61..2d4f870 100644
> >--- a/drivers/gpu/drm/i915/i915_debugfs.c
> >+++ b/drivers/gpu/drm/i915/i915_debugfs.c
> >@@ -1240,11 +1240,12 @@ static int vlv_drpc_info(struct seq_file *m)
> > struct drm_info_node *node = m->private;
> > struct drm_device *dev = node->minor->dev;
> > struct drm_i915_private *dev_priv = dev->dev_private;
> >- u32 rpmodectl1, rcctl1;
> >+ u32 rpmodectl1, rcctl1, pw_status;
> > unsigned fw_rendercount = 0, fw_mediacount = 0;
> > intel_runtime_pm_get(dev_priv);
> >+ pw_status = I915_READ(VLV_GTLC_PW_STATUS);
> > rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
> > rcctl1 = I915_READ(GEN6_RC_CONTROL);
> >@@ -1263,11 +1264,9 @@ static int vlv_drpc_info(struct seq_file *m)
> > yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
> > GEN6_RC_CTL_EI_MODE(1))));
> > seq_printf(m, "Render Power Well: %s\n",
> >- (I915_READ(VLV_GTLC_PW_STATUS) &
> >- VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
> >+ (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
> > seq_printf(m, "Media Power Well: %s\n",
> >- (I915_READ(VLV_GTLC_PW_STATUS) &
> >- VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
> >+ (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
> > seq_printf(m, "Render RC6 residency since boot: %u\n",
> > I915_READ(VLV_GT_RENDER_RC6));
>
> Reviewed-by: Deepak S<deepak.s@linux.intel.com>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915: Read power well status before other registers for drpc info
2014-11-19 18:07 [PATCH] drm/i915: Read power well status before other registers for drpc info ville.syrjala
@ 2014-11-21 3:26 ` Deepak S
2014-11-20 9:26 ` Daniel Vetter
2014-11-21 4:58 ` [PATCH] drm/i915: Read power well status before other shuang.he
1 sibling, 1 reply; 4+ messages in thread
From: Deepak S @ 2014-11-21 3:26 UTC (permalink / raw)
To: intel-gfx
On Wednesday 19 November 2014 11:37 PM, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Trying to read the status of the power wells right after taking forcewake
> for the other register reads makes little sense. Most of the time the
> power wells will still be up due to the recent forcewake. Instead do the
> power well status read first, and only then read the register needing
> forcewake. This way the reported power well status can actually reflect
> what's going on in the system.
>
> Cc: Deepak S <deepak.s@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 9 ++++-----
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 319da61..2d4f870 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1240,11 +1240,12 @@ static int vlv_drpc_info(struct seq_file *m)
> struct drm_info_node *node = m->private;
> struct drm_device *dev = node->minor->dev;
> struct drm_i915_private *dev_priv = dev->dev_private;
> - u32 rpmodectl1, rcctl1;
> + u32 rpmodectl1, rcctl1, pw_status;
> unsigned fw_rendercount = 0, fw_mediacount = 0;
>
> intel_runtime_pm_get(dev_priv);
>
> + pw_status = I915_READ(VLV_GTLC_PW_STATUS);
> rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
> rcctl1 = I915_READ(GEN6_RC_CONTROL);
>
> @@ -1263,11 +1264,9 @@ static int vlv_drpc_info(struct seq_file *m)
> yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
> GEN6_RC_CTL_EI_MODE(1))));
> seq_printf(m, "Render Power Well: %s\n",
> - (I915_READ(VLV_GTLC_PW_STATUS) &
> - VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
> + (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
> seq_printf(m, "Media Power Well: %s\n",
> - (I915_READ(VLV_GTLC_PW_STATUS) &
> - VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
> + (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
>
> seq_printf(m, "Render RC6 residency since boot: %u\n",
> I915_READ(VLV_GT_RENDER_RC6));
Reviewed-by: Deepak S<deepak.s@linux.intel.com>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] drm/i915: Read power well status before other
2014-11-19 18:07 [PATCH] drm/i915: Read power well status before other registers for drpc info ville.syrjala
2014-11-21 3:26 ` Deepak S
@ 2014-11-21 4:58 ` shuang.he
1 sibling, 0 replies; 4+ messages in thread
From: shuang.he @ 2014-11-21 4:58 UTC (permalink / raw)
To: shuang.he, intel-gfx, ville.syrjala
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV -3 369/369 366/369
ILK +14-12 361/378 363/378
SNB -9 459/459 450/459
IVB -32 535/545 503/545
BYT -1 290/290 289/290
HSW -20 338/338 318/338
BDW -20 302/302 282/302
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
PNV igt_drv_hangman_error-state-capture-render TIMEOUT(27, M25M7M23)PASS(4, M23) TIMEOUT(1, M23)
PNV igt_drv_missed_irq_hang TIMEOUT(30, M23M25M7)PASS(1, M23) TIMEOUT(1, M23)
PNV igt_gen3_mixed_blits PASS(1, M23) CRASH(1, M23)
ILK igt_drv_hangman_error-state-basic TIMEOUT(12, M37M26)PASS(4, M26) TIMEOUT(1, M37)PASS(3, M37)
ILK igt_drv_hangman_error-state-capture-bsd TIMEOUT(2, M26M37)PASS(1, M26) TIMEOUT(1, M37)PASS(3, M37)
ILK igt_drv_hangman_error-state-capture-render PASS(1, M26) TIMEOUT(1, M37)PASS(3, M37)
ILK igt_drv_missed_irq_hang PASS(1, M26) TIMEOUT(1, M37)PASS(3, M37)
ILK igt_gem_reset_stats_ban-render PASS(4, M26) TIMEOUT(1, M37)PASS(3, M37)
ILK igt_gem_reset_stats_close-pending-fork-render PASS(1, M26) TIMEOUT(1, M37)PASS(3, M37)
ILK igt_gem_reset_stats_close-pending-fork-reverse-render PASS(1, M26) TIMEOUT(1, M37)PASS(3, M37)
ILK igt_gem_reset_stats_close-pending-render PASS(1, M26) TIMEOUT(1, M37)PASS(3, M37)
ILK igt_gem_reset_stats_reset-count-render PASS(1, M26) TIMEOUT(1, M37)PASS(3, M37)
ILK igt_gem_reset_stats_reset-stats-render PASS(1, M26) TIMEOUT(1, M37)PASS(3, M37)
ILK igt_gem_workarounds_reset PASS(1, M26) TIMEOUT(1, M37)PASS(3, M37)
ILK igt_kms_flip_bcs-wf_vblank-vs-dpms DMESG_WARN(2, M26)PASS(2, M26) PASS(4, M37)
ILK igt_kms_flip_bcs-wf_vblank-vs-dpms-interruptible DMESG_WARN(1, M26) PASS(4, M37)
ILK igt_kms_flip_bcs-wf_vblank-vs-modeset-interruptible DMESG_WARN(1, M26)PASS(3, M26) PASS(4, M37)
ILK igt_kms_flip_blocking-wf_vblank DMESG_WARN(1, M26)PASS(3, M26) PASS(4, M37)
ILK igt_kms_flip_flip-vs-absolute-wf_vblank DMESG_WARN(1, M26) PASS(4, M37)
ILK igt_kms_flip_flip-vs-absolute-wf_vblank-interruptible DMESG_WARN(1, M26)PASS(3, M26) PASS(4, M37)
ILK igt_kms_flip_flip-vs-dpms-off-vs-modeset-interruptible DMESG_WARN(2, M26)PASS(2, M26) PASS(4, M37)
ILK igt_kms_flip_flip-vs-expired-vblank-interruptible DMESG_WARN(2, M26)PASS(2, M26) PASS(4, M37)
ILK igt_kms_flip_flip-vs-modeset-vs-hang DMESG_WARN(2, M26)PASS(2, M26) TIMEOUT(1, M37)PASS(3, M37)
ILK igt_kms_flip_flip-vs-modeset-vs-hang-interruptible DMESG_WARN(1, M26)PASS(3, M26) TIMEOUT(1, M37)PASS(3, M37)
ILK igt_kms_flip_flip-vs-panning NSPT(1, M26) PASS(4, M37)
ILK igt_kms_flip_flip-vs-panning-vs-hang-interruptible DMESG_WARN(1, M26)PASS(3, M26) TIMEOUT(1, M37)PASS(3, M37)
ILK igt_kms_flip_flip-vs-wf_vblank DMESG_WARN(1, M26)PASS(3, M26) PASS(4, M37)
ILK igt_kms_flip_nonexisting-fb DMESG_WARN(1, M26) PASS(4, M37)
ILK igt_kms_flip_nonexisting-fb-interruptible DMESG_WARN(1, M26)PASS(3, M26) PASS(4, M37)
ILK igt_kms_flip_plain-flip-interruptible DMESG_WARN(1, M26)PASS(3, M26) PASS(4, M37)
ILK igt_kms_flip_single-buffer-flip-vs-dpms-off-vs-modeset DMESG_WARN(1, M26) PASS(4, M37)
ILK igt_kms_flip_vblank-vs-hang PASS(1, M26) TIMEOUT(1, M37)PASS(3, M37)
SNB igt_drv_hangman_error-state-basic TIMEOUT(24, M35M22)PASS(1, M35) TIMEOUT(1, M22)PASS(3, M22)
SNB igt_drv_hangman_error-state-capture-bsd TIMEOUT(24, M35M22)PASS(1, M35) TIMEOUT(1, M22)PASS(3, M22)
SNB igt_drv_hangman_error-state-capture-render TIMEOUT(8, M35M22)PASS(1, M35) TIMEOUT(1, M22)PASS(3, M22)
SNB igt_drv_missed_irq_hang PASS(1, M35) TIMEOUT(1, M22)PASS(3, M22)
SNB igt_gem_reset_stats_reset-count-render PASS(1, M35) TIMEOUT(1, M22)PASS(3, M22)
SNB igt_gem_reset_stats_unrelated-ctx-render PASS(1, M35) TIMEOUT(1, M22)PASS(3, M22)
SNB igt_kms_pipe_crc_basic_hang-read-crc-pipe-A PASS(4, M35) TIMEOUT(1, M22)PASS(3, M22)
SNB igt_kms_pipe_crc_basic_hang-read-crc-pipe-B PASS(1, M35) TIMEOUT(1, M22)PASS(3, M22)
SNB igt_pm_rps_min-max-config-idle PASS(1, M35) FAIL(1, M22)PASS(3, M22)
IVB igt_drv_hangman_error-state-basic TIMEOUT(15, M34M21M4)PASS(4, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_drv_hangman_error-state-capture-blt TIMEOUT(15, M34M21M4)PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_drv_hangman_error-state-capture-bsd TIMEOUT(1, M34)PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_drv_hangman_error-state-capture-render PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_drv_missed_irq_hang PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_bad_reloc_negative-reloc PASS(1, M21) NSPT(1, M4)PASS(3, M4)
IVB igt_gem_reset_stats_ban-ctx-render DMESG_WARN(2, M21)PASS(2, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_reset_stats_ban-render DMESG_WARN(2, M21)PASS(2, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_reset_stats_close-pending-blt PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_reset_stats_close-pending-bsd PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_reset_stats_close-pending-ctx-render PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_reset_stats_close-pending-fork-blt PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_reset_stats_close-pending-fork-bsd PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_reset_stats_close-pending-fork-render PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_reset_stats_close-pending-fork-reverse-blt PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_reset_stats_close-pending-fork-reverse-bsd PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_reset_stats_close-pending-fork-reverse-render PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_reset_stats_close-pending-render PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_reset_stats_reset-count-blt PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_reset_stats_reset-count-bsd PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_reset_stats_reset-count-ctx-render PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_reset_stats_reset-count-render PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_reset_stats_reset-stats-blt PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_reset_stats_reset-stats-bsd PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_reset_stats_reset-stats-ctx-render PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_reset_stats_reset-stats-render PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_reset_stats_unrelated-ctx-render PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_gem_workarounds_reset PASS(4, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_kms_pipe_crc_basic_hang-read-crc-pipe-A PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_kms_pipe_crc_basic_hang-read-crc-pipe-B PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_kms_pipe_crc_basic_hang-read-crc-pipe-C PASS(1, M21) TIMEOUT(1, M4)PASS(3, M4)
IVB igt_pm_rps_min-max-config-idle PASS(1, M21) FAIL(1, M4)PASS(3, M4)
BYT igt_drv_missed_irq_hang TIMEOUT(35, M36M31)PASS(2, M36M31) TIMEOUT(1, M36)PASS(3, M36)
HSW igt_drv_hangman_error-state-basic TIMEOUT(11, M20M40)PASS(4, M19M40) TIMEOUT(1, M40)PASS(3, M40)
HSW igt_drv_hangman_error-state-capture-blt TIMEOUT(7, M20M40)PASS(1, M19) TIMEOUT(1, M40)PASS(3, M40)
HSW igt_drv_hangman_error-state-capture-bsd PASS(1, M19) TIMEOUT(1, M40)PASS(3, M40)
HSW igt_drv_hangman_error-state-capture-render PASS(1, M19) TIMEOUT(1, M40)PASS(3, M40)
HSW igt_drv_hangman_error-state-capture-vebox PASS(1, M19) TIMEOUT(1, M40)PASS(3, M40)
HSW igt_drv_missed_irq_hang PASS(1, M19) TIMEOUT(1, M40)PASS(3, M40)
HSW igt_gem_reset_stats_ban-bsd PASS(4, M19M40) TIMEOUT(1, M40)PASS(3, M40)
HSW igt_gem_reset_stats_ban-ctx-render PASS(1, M19) TIMEOUT(1, M40)PASS(3, M40)
HSW igt_gem_reset_stats_ban-render PASS(1, M19) TIMEOUT(1, M40)PASS(3, M40)
HSW igt_gem_reset_stats_ban-vebox PASS(1, M19) TIMEOUT(1, M40)PASS(3, M40)
HSW igt_gem_reset_stats_close-pending-blt PASS(1, M19) TIMEOUT(1, M40)PASS(3, M40)
HSW igt_gem_reset_stats_close-pending-bsd PASS(1, M19) TIMEOUT(1, M40)PASS(3, M40)
HSW igt_gem_reset_stats_close-pending-ctx-render PASS(1, M19) TIMEOUT(1, M40)PASS(3, M40)
HSW igt_gem_reset_stats_close-pending-fork-blt PASS(1, M19) TIMEOUT(1, M40)PASS(3, M40)
HSW igt_gem_reset_stats_close-pending-fork-bsd PASS(1, M19) TIMEOUT(1, M40)PASS(3, M40)
HSW igt_gem_reset_stats_close-pending-fork-render PASS(1, M19) TIMEOUT(1, M40)PASS(3, M40)
HSW igt_gem_reset_stats_close-pending-fork-reverse-blt PASS(1, M19) TIMEOUT(1, M40)PASS(3, M40)
HSW igt_gem_reset_stats_close-pending-fork-reverse-bsd PASS(1, M19) TIMEOUT(1, M40)PASS(3, M40)
HSW igt_gem_reset_stats_close-pending-fork-reverse-render PASS(1, M19) TIMEOUT(1, M40)PASS(3, M40)
HSW igt_gem_reset_stats_close-pending-fork-reverse-vebox PASS(1, M19) TIMEOUT(1, M40)PASS(3, M40)
BDW igt_drv_hangman_error-state-basic TIMEOUT(18, M28M30)PASS(4, M28M30) TIMEOUT(1, M30)PASS(3, M30)
BDW igt_drv_hangman_error-state-capture-blt TIMEOUT(17, M28M30)PASS(1, M28) TIMEOUT(1, M30)PASS(3, M30)
BDW igt_drv_hangman_error-state-capture-bsd TIMEOUT(1, M28)PASS(1, M28) TIMEOUT(1, M30)PASS(3, M30)
BDW igt_drv_hangman_error-state-capture-render PASS(1, M28) TIMEOUT(1, M30)PASS(3, M30)
BDW igt_drv_hangman_error-state-capture-vebox PASS(1, M28) TIMEOUT(1, M30)PASS(3, M30)
BDW igt_gem_reset_stats_ban-blt PASS(1, M28) TIMEOUT(1, M30)PASS(3, M30)
BDW igt_gem_reset_stats_ban-bsd PASS(1, M28) TIMEOUT(1, M30)PASS(3, M30)
BDW igt_gem_reset_stats_ban-ctx-render PASS(1, M28) TIMEOUT(1, M30)PASS(3, M30)
BDW igt_gem_reset_stats_ban-render PASS(1, M28) TIMEOUT(1, M30)PASS(3, M30)
BDW igt_gem_reset_stats_ban-vebox PASS(1, M28) TIMEOUT(1, M30)PASS(3, M30)
BDW igt_gem_reset_stats_close-pending-blt PASS(1, M28) TIMEOUT(1, M30)PASS(3, M30)
BDW igt_gem_reset_stats_close-pending-bsd PASS(1, M28) TIMEOUT(1, M30)PASS(3, M30)
BDW igt_gem_reset_stats_close-pending-ctx-render PASS(1, M28) TIMEOUT(1, M30)PASS(3, M30)
BDW igt_gem_reset_stats_close-pending-fork-blt PASS(1, M28) TIMEOUT(1, M30)PASS(3, M30)
BDW igt_gem_reset_stats_close-pending-fork-bsd PASS(1, M28) TIMEOUT(1, M30)PASS(3, M30)
BDW igt_gem_reset_stats_close-pending-fork-render PASS(1, M28) TIMEOUT(1, M30)PASS(3, M30)
BDW igt_gem_reset_stats_close-pending-fork-reverse-blt PASS(1, M28) TIMEOUT(1, M30)PASS(3, M30)
BDW igt_gem_reset_stats_close-pending-fork-reverse-bsd PASS(1, M28) TIMEOUT(1, M30)PASS(3, M30)
BDW igt_gem_reset_stats_close-pending-fork-reverse-render PASS(1, M28) TIMEOUT(1, M30)PASS(3, M30)
BDW igt_gem_reset_stats_close-pending-fork-reverse-vebox PASS(1, M28) TIMEOUT(1, M30)PASS(3, M30)
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2014-11-19 18:07 [PATCH] drm/i915: Read power well status before other registers for drpc info ville.syrjala
2014-11-21 3:26 ` Deepak S
2014-11-20 9:26 ` Daniel Vetter
2014-11-21 4:58 ` [PATCH] drm/i915: Read power well status before other shuang.he
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