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From: "M, Satheeshakrishna" <satheeshakrishna.m@intel.com>
To: sonika.jindal@intel.com, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/skl: Correcting the flushing of pipe
Date: Mon, 15 Dec 2014 15:35:30 +0530	[thread overview]
Message-ID: <548EB26A.4050905@intel.com> (raw)
In-Reply-To: <1418300895-17021-1-git-send-email-sonika.jindal@intel.com>

On 12/11/2014 5:58 PM, sonika.jindal@intel.com wrote:
> From: Sonika Jindal <sonika.jindal@intel.com>
>
> We were incorreectly bypassing the flush everytime which led to fifo
> underrun when more than one plane is enabled.
>
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> ---
>   drivers/gpu/drm/i915/intel_pm.c |    3 +--
>   1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5748bf9..8cd045a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3633,9 +3633,8 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
>   		    skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
>   			skl_wm_flush_pipe(dev_priv, pipe, 2);
>   			intel_wait_for_vblank(dev, pipe);
> +			reallocated[pipe] = true;
>   		}
> -
> -		reallocated[pipe] = true;
>   	}
>   
>   	/*
Reviewed-by: Satheeshakrishna M<satheeshakrishna.m@intel.com>
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      parent reply	other threads:[~2014-12-15 10:05 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-12-11 12:28 [PATCH] drm/i915/skl: Correcting the flushing of pipe sonika.jindal
2014-12-11 15:20 ` Tvrtko Ursulin
2014-12-15 10:12   ` Daniel Vetter
2014-12-11 19:39 ` shuang.he
2014-12-15 10:05 ` M, Satheeshakrishna [this message]

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