* [PATCH] drm/i915/skl: Correcting the flushing of pipe
@ 2014-12-11 12:28 sonika.jindal
2014-12-11 15:20 ` Tvrtko Ursulin
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: sonika.jindal @ 2014-12-11 12:28 UTC (permalink / raw)
To: intel-gfx
From: Sonika Jindal <sonika.jindal@intel.com>
We were incorreectly bypassing the flush everytime which led to fifo
underrun when more than one plane is enabled.
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5748bf9..8cd045a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3633,9 +3633,8 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
skl_wm_flush_pipe(dev_priv, pipe, 2);
intel_wait_for_vblank(dev, pipe);
+ reallocated[pipe] = true;
}
-
- reallocated[pipe] = true;
}
/*
--
1.7.10.4
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^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] drm/i915/skl: Correcting the flushing of pipe
2014-12-11 12:28 [PATCH] drm/i915/skl: Correcting the flushing of pipe sonika.jindal
@ 2014-12-11 15:20 ` Tvrtko Ursulin
2014-12-15 10:12 ` Daniel Vetter
2014-12-11 19:39 ` shuang.he
2014-12-15 10:05 ` M, Satheeshakrishna
2 siblings, 1 reply; 5+ messages in thread
From: Tvrtko Ursulin @ 2014-12-11 15:20 UTC (permalink / raw)
To: sonika.jindal, intel-gfx
On 12/11/2014 12:28 PM, sonika.jindal@intel.com wrote:
> From: Sonika Jindal <sonika.jindal@intel.com>
>
> We were incorreectly bypassing the flush everytime which led to fifo
> underrun when more than one plane is enabled.
>
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5748bf9..8cd045a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3633,9 +3633,8 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
> skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
> skl_wm_flush_pipe(dev_priv, pipe, 2);
> intel_wait_for_vblank(dev, pipe);
> + reallocated[pipe] = true;
> }
> -
> - reallocated[pipe] = true;
> }
>
> /*
Works like a charm now!
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
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^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH] drm/i915/skl: Correcting the flushing of pipe
2014-12-11 15:20 ` Tvrtko Ursulin
@ 2014-12-15 10:12 ` Daniel Vetter
0 siblings, 0 replies; 5+ messages in thread
From: Daniel Vetter @ 2014-12-15 10:12 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
On Thu, Dec 11, 2014 at 03:20:39PM +0000, Tvrtko Ursulin wrote:
>
> On 12/11/2014 12:28 PM, sonika.jindal@intel.com wrote:
> >From: Sonika Jindal <sonika.jindal@intel.com>
> >
> >We were incorreectly bypassing the flush everytime which led to fifo
> >underrun when more than one plane is enabled.
> >
> >Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> >---
> > drivers/gpu/drm/i915/intel_pm.c | 3 +--
> > 1 file changed, 1 insertion(+), 2 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> >index 5748bf9..8cd045a 100644
> >--- a/drivers/gpu/drm/i915/intel_pm.c
> >+++ b/drivers/gpu/drm/i915/intel_pm.c
> >@@ -3633,9 +3633,8 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
> > skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
> > skl_wm_flush_pipe(dev_priv, pipe, 2);
> > intel_wait_for_vblank(dev, pipe);
> >+ reallocated[pipe] = true;
> > }
> >-
> >- reallocated[pipe] = true;
> > }
> >
> > /*
>
> Works like a charm now!
>
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/skl: Correcting the flushing of pipe
2014-12-11 12:28 [PATCH] drm/i915/skl: Correcting the flushing of pipe sonika.jindal
2014-12-11 15:20 ` Tvrtko Ursulin
@ 2014-12-11 19:39 ` shuang.he
2014-12-15 10:05 ` M, Satheeshakrishna
2 siblings, 0 replies; 5+ messages in thread
From: shuang.he @ 2014-12-11 19:39 UTC (permalink / raw)
To: shuang.he, intel-gfx, sonika.jindal
Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
PNV 364/364 364/364
ILK +1-2 364/366 363/366
SNB 448/450 448/450
IVB 497/498 497/498
BYT 289/289 289/289
HSW 563/564 563/564
BDW 417/417 417/417
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
ILK igt_kms_flip_blocking-absolute-wf_vblank-interruptible DMESG_WARN(1, M26)PASS(8, M26) DMESG_WARN(1, M26)
ILK igt_kms_flip_flip-vs-rmfb-interruptible NSPT(1, M26)PASS(6, M26) NSPT(1, M26)
ILK igt_kms_flip_wf_vblank-ts-check DMESG_WARN(7, M26)PASS(24, M26M37) PASS(1, M26)
Note: You need to pay more attention to line start with '*'
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^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/skl: Correcting the flushing of pipe
2014-12-11 12:28 [PATCH] drm/i915/skl: Correcting the flushing of pipe sonika.jindal
2014-12-11 15:20 ` Tvrtko Ursulin
2014-12-11 19:39 ` shuang.he
@ 2014-12-15 10:05 ` M, Satheeshakrishna
2 siblings, 0 replies; 5+ messages in thread
From: M, Satheeshakrishna @ 2014-12-15 10:05 UTC (permalink / raw)
To: sonika.jindal, intel-gfx
On 12/11/2014 5:58 PM, sonika.jindal@intel.com wrote:
> From: Sonika Jindal <sonika.jindal@intel.com>
>
> We were incorreectly bypassing the flush everytime which led to fifo
> underrun when more than one plane is enabled.
>
> Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 5748bf9..8cd045a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3633,9 +3633,8 @@ static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
> skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
> skl_wm_flush_pipe(dev_priv, pipe, 2);
> intel_wait_for_vblank(dev, pipe);
> + reallocated[pipe] = true;
> }
> -
> - reallocated[pipe] = true;
> }
>
> /*
Reviewed-by: Satheeshakrishna M<satheeshakrishna.m@intel.com>
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^ permalink raw reply [flat|nested] 5+ messages in thread
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2014-12-11 12:28 [PATCH] drm/i915/skl: Correcting the flushing of pipe sonika.jindal
2014-12-11 15:20 ` Tvrtko Ursulin
2014-12-15 10:12 ` Daniel Vetter
2014-12-11 19:39 ` shuang.he
2014-12-15 10:05 ` M, Satheeshakrishna
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