Re: [Intel-gfx] [PATCH 5/9] drm/i915/userptr: add paranoid flush-on-acquire

["Thomas Hellström" <thomas.hellstrom@linux.intel.com>]

On 10/18/21 19:45, Matthew Auld wrote:
> Even though userptr objects are always coherent with the GPU, with no
> way for userspace to change this with the set_caching ioctl, even on
> non-LLC platforms, there is still the 'Bypass LCC' mocs setting, which
> might permit reading the contents of main memory directly.
>
> Signed-off-by: Matthew Auld <matthew.auld@intel.com>
> Cc: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/gem/i915_gem_userptr.c | 5 ++++-
>   1 file changed, 4 insertions(+), 1 deletion(-)

Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>


> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> index 887aca9e8dd2..3173c9f9a040 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_userptr.c
> @@ -165,8 +165,11 @@ static int i915_gem_userptr_get_pages(struct drm_i915_gem_object *obj)
>   		goto err;
>   	}
>   
> -	sg_page_sizes = i915_sg_dma_sizes(st->sgl);
> +	WARN_ON_ONCE(!(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE));
> +	if (i915_gem_object_can_bypass_llc(obj))
> +		obj->cache_dirty = true;
>   
> +	sg_page_sizes = i915_sg_dma_sizes(st->sgl);
>   	__i915_gem_object_set_pages(obj, st, sg_page_sizes);
>   
>   	return 0;