From: "Ceraolo Spurio, Daniele" <daniele.ceraolospurio@intel.com>
To: "Teres Alexis, Alan Previn" <alan.previn.teres.alexis@intel.com>,
"intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>
Cc: "Vivi, Rodrigo" <rodrigo.vivi@intel.com>,
"dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH v7 5/8] drm/i915/pxp: Add ARB session creation and cleanup
Date: Mon, 17 Apr 2023 12:15:42 -0700 [thread overview]
Message-ID: <55584390-8086-df81-5649-76e45039e306@intel.com> (raw)
In-Reply-To: <9bb67b2ed9ae681388c0f39dba29532083b323ba.camel@intel.com>
On 4/17/2023 11:21 AM, Teres Alexis, Alan Previn wrote:
> On Mon, 2023-04-10 at 10:14 -0700, Ceraolo Spurio, Daniele wrote:
>>
>>
> alan:snip
>
>>> @@ -354,8 +368,14 @@ int intel_pxp_start(struct intel_pxp *pxp)
>>> if (!intel_pxp_is_enabled(pxp))
>>> return -ENODEV;
>>>
>>> - if (wait_for(pxp_component_bound(pxp), 250))
>>> - return -ENXIO;
>>> + if (HAS_ENGINE(pxp->ctrl_gt, GSC0)) {
>>> + /* Use a larger 1 second timeout considering all the dependencies. */
>>> + if (wait_for(intel_pxp_gsccs_is_ready_for_sessions(pxp), 1000))
>>> + return -ENXIO;
>> This needs a comment to explain that we expect userspace to retry later
>> if we return -ENXIO and therefore the timeout is smaller that what would
>> be required to guarantee that the init can complete. It also needs an
>> ack from the userspace drivers for this behavior.
>>
> alan: I agree with a requirement to comment this down. However, i believe its better
> to put this int the UAPI header file comment-documentation since it applies to both
> current MTL as well as previous ADL cases (this is not new behavior being introduced
> in MTL but it is fixing of the spec of existing behavior).
> That said, your feedback is already being addressed by patch #6 but i will ammend
> patch #6 to add the detail you highlighted WRT ~"timeout is not larger than the completion-guarantee...".
Can you move that comment update for the context getparam from the next
patch to this one? that way it's all nicely self-contained in this patch.
> alan:snip
>>> +fw_err_to_string(u32 type)
>>> +{
>>> + switch (type) {
>>> + case PXP_STATUS_ERROR_API_VERSION:
>>> + return "ERR_API_VERSION";
>>> + case PXP_STATUS_NOT_READY:
>>> + return "ERR_NOT_READY";
>>> + case PXP_STATUS_PLATFCONFIG_KF1_NOVERIF:
>>> + case PXP_STATUS_PLATFCONFIG_KF1_BAD:
>>> + return "ERR_PLATFORM_CONFIG";
>>> + default:
>>> + break;
>>> + }
>>> + return NULL;
>>> +}
>>> +
>> There is a lot of replication for this error handling, I'm wondering if
>> it's worth adding a common function to handle this. Something like:
>>
>> intel_pxp_header_error(u32 header, const char *op, u32 id)
>> {
>> if (is_fw_err_platform_config(header.status)) {
>> drm_info_once(&i915->drm,
>> "PXP %s-%d failed due to BIOS/SOC:0x%08x:%s\n",
>> op, id, header.status,
>> fw_err_to_string(header.status));
>> } else {
>> drm_dbg(&i915->drm, "PXP %s-%d failed 0x%08x:%st:\n",
>> op, id, header.status,
>> fw_err_to_string(header.status));
>> drm_dbg(&i915->drm, " cmd-detail: ID=[0x%08x],API-Ver-[0x%08x]\n",
>> header.command_id, header.api_version);
>> }
>> }
>>
>>
>> Not a blocker.
> alan: Thanks - i will have to address as a stand alone patch since i have to
> think about moving this to a comment helper layer (common to both ADL-mei-comp and MTL-gsccs)
> while potentially have different set of error codes that can mean different reporting levels
> (i.e. notice once coz its a platform limit vs always err out if its runtime related).
> Once this series gets merged it will be easier to work on that patch (which would require both
> backends to be present in the baseline).
> alan:snip
>>> +++ b/drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h
>>> @@ -10,14 +10,18 @@
>>>
>>> struct intel_pxp;
>>>
>>> -#define GSC_REPLY_LATENCY_MS 200
>>> +#define GSC_REPLY_LATENCY_MS 210
>> why move from 200 to 210? not a problem, I just want to understand why
>> this is required.
>>
>> Daniele
> alan: so 200 is based on the fw spec - and from real testing i observed the occasional highs touching ~185ms.
> However, the spec gives this number as the expected max time the firmware is going to take to process the request
> and post a reply. Therefore it doesn't include the additional overhead for the request creation, emision,
> submission via guc and the completion pipeline completion indication. All of these contribute additional layers
> of possible delay. Since arb-session creation and invalidation are not common events,
> I believe a slightly wider overhead of 10 milisec will not hurt.
Agreed. Can you add a comment? something like "Max FW response time is
200ms, to which we add 10ms to account for overhead".
With those 2 nits addressed:
Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Daniele
>
next prev parent reply other threads:[~2023-04-17 19:15 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-06 17:44 [Intel-gfx] [PATCH v7 0/8] drm/i915/pxp: Add MTL PXP Support Alan Previn
2023-04-06 17:44 ` [Intel-gfx] [PATCH v7 1/8] drm/i915/pxp: Add GSC-CS back-end resource init and cleanup Alan Previn
2023-04-06 17:44 ` [Intel-gfx] [PATCH v7 2/8] drm/i915/pxp: Add MTL hw-plumbing enabling for KCR operation Alan Previn
2023-04-06 17:44 ` [Intel-gfx] [PATCH v7 3/8] drm/i915/pxp: Add MTL helpers to submit Heci-Cmd-Packet to GSC Alan Previn
2023-04-10 16:10 ` Ceraolo Spurio, Daniele
2023-04-17 17:56 ` Teres Alexis, Alan Previn
2023-04-20 23:39 ` Ceraolo Spurio, Daniele
2023-04-06 17:44 ` [Intel-gfx] [PATCH v7 4/8] drm/i915/pxp: Add GSC-CS backend to send GSC fw messages Alan Previn
2023-04-10 16:28 ` Ceraolo Spurio, Daniele
2023-04-17 18:03 ` Teres Alexis, Alan Previn
2023-04-06 17:44 ` [Intel-gfx] [PATCH v7 5/8] drm/i915/pxp: Add ARB session creation and cleanup Alan Previn
2023-04-10 17:14 ` Ceraolo Spurio, Daniele
2023-04-17 18:21 ` Teres Alexis, Alan Previn
2023-04-17 19:15 ` Ceraolo Spurio, Daniele [this message]
2023-04-17 19:27 ` Teres Alexis, Alan Previn
2023-04-06 17:44 ` [Intel-gfx] [PATCH v7 6/8] drm/i915/uapi/pxp: Fix UAPI spec comments and add GET_PARAM for PXP Alan Previn
2023-04-10 17:22 ` Ceraolo Spurio, Daniele
2023-04-14 15:17 ` Teres Alexis, Alan Previn
2023-04-18 18:06 ` Lionel Landwerlin
2023-04-18 18:37 ` Teres Alexis, Alan Previn
2023-04-06 17:44 ` [Intel-gfx] [PATCH v7 7/8] drm/i915/pxp: On MTL, KCR enabling doesn't wait on tee component Alan Previn
2023-04-06 17:44 ` [Intel-gfx] [PATCH v7 8/8] drm/i915/pxp: Enable PXP with MTL-GSC-CS Alan Previn
2023-04-06 18:46 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/pxp: Add MTL PXP Support (rev7) Patchwork
2023-04-06 18:46 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-04-06 18:55 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-04-07 9:53 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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