From: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>
To: Ville Syrjala <ville.syrjala@linux.intel.com>,
<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 02/11] drm/i915: Use _MMIO_PIPE() for SKL_BOTTOM_COLOR
Date: Thu, 3 Nov 2022 11:08:20 +0530 [thread overview]
Message-ID: <56232718-9188-4f4e-e024-3dc1db8887b9@intel.com> (raw)
In-Reply-To: <20221026113906.10551-3-ville.syrjala@linux.intel.com>
Makes sense.
LGTM.
Reviewed-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
On 10/26/2022 5:08 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> No need to use _MMIO_PIPE2() for SKL_BOTTOM_COLOR
> since all pipe registers are evenly spread on skl+.
> Switch to _MMIO_PIPE() and thus avoid the hidden dev_priv.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 99a853519395..89ad893bbf07 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3758,9 +3758,10 @@
>
> /* Skylake+ pipe bottom (background) color */
> #define _SKL_BOTTOM_COLOR_A 0x70034
> +#define _SKL_BOTTOM_COLOR_B 0x71034
> #define SKL_BOTTOM_COLOR_GAMMA_ENABLE REG_BIT(31)
> #define SKL_BOTTOM_COLOR_CSC_ENABLE REG_BIT(30)
> -#define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE2(pipe, _SKL_BOTTOM_COLOR_A)
> +#define SKL_BOTTOM_COLOR(pipe) _MMIO_PIPE(pipe, _SKL_BOTTOM_COLOR_A, _SKL_BOTTOM_COLOR_B)
>
> #define _ICL_PIPE_A_STATUS 0x70058
> #define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS)
next prev parent reply other threads:[~2022-11-03 5:38 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-26 11:38 [Intel-gfx] [PATCH 00/11] drm/i915: More gamma work Ville Syrjala
2022-10-26 11:38 ` [Intel-gfx] [PATCH 01/11] drm/i915: Use sizeof(variable) instead sizeof(type) Ville Syrjala
2022-11-03 5:29 ` Nautiyal, Ankit K
2022-10-26 11:38 ` [Intel-gfx] [PATCH 02/11] drm/i915: Use _MMIO_PIPE() for SKL_BOTTOM_COLOR Ville Syrjala
2022-11-03 5:38 ` Nautiyal, Ankit K [this message]
2022-10-26 11:38 ` [Intel-gfx] [PATCH 03/11] drm/i915: s/dev_priv/i915/ in intel_color.c Ville Syrjala
2022-11-03 5:52 ` Nautiyal, Ankit K
2022-10-26 11:38 ` [Intel-gfx] [PATCH 04/11] drm/i915: s/icl_load_gcmax/ivb_load_lut_max/ Ville Syrjala
2022-11-03 6:19 ` Nautiyal, Ankit K
2022-11-03 9:34 ` Ville Syrjälä
2022-11-03 10:28 ` Nautiyal, Ankit K
2022-10-26 11:39 ` [Intel-gfx] [PATCH 05/11] drm/i915: Split ivb_load_lut_ext_max() into two parts Ville Syrjala
2022-11-03 6:31 ` Nautiyal, Ankit K
2022-10-26 11:39 ` [Intel-gfx] [PATCH 06/11] drm/i915: Deconfuse the ilk+ 12.4 LUT entry functions Ville Syrjala
2022-11-03 7:37 ` Nautiyal, Ankit K
2022-11-03 9:37 ` Ville Syrjälä
2022-10-26 11:39 ` [Intel-gfx] [PATCH 07/11] drm/i915: Pass limited_range explicitly to ilk_csc_convert_ctm() Ville Syrjala
2022-11-03 10:04 ` Nautiyal, Ankit K
2022-10-26 11:39 ` [Intel-gfx] [PATCH 08/11] drm/i915: Reuse ilk_gamma_mode() on ivb+ Ville Syrjala
2022-11-03 10:09 ` Nautiyal, Ankit K
2022-10-26 11:39 ` [Intel-gfx] [PATCH 09/11] drm/i915: Reject YCbCr output with degamma+gamma on pre-icl Ville Syrjala
2022-11-03 10:14 ` Nautiyal, Ankit K
2022-10-26 11:39 ` [Intel-gfx] [PATCH 10/11] drm/i915: Share {csc, gamma}_enable calculation for ilk/snb vs. ivb+ Ville Syrjala
2022-11-03 10:25 ` Nautiyal, Ankit K
2022-10-26 11:39 ` [Intel-gfx] [PATCH 11/11] drm/i915: Create resized LUTs for ivb+ split gamma mode Ville Syrjala
2022-11-04 5:19 ` Nautiyal, Ankit K
2022-11-04 9:42 ` Ville Syrjälä
2022-11-10 4:05 ` Nautiyal, Ankit K
2022-11-10 7:23 ` Ville Syrjälä
2022-10-26 12:27 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: More gamma work Patchwork
2022-10-26 12:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-26 23:25 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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