From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Nautiyal, Ankit K" <ankit.k.nautiyal@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 11/11] drm/i915: Create resized LUTs for ivb+ split gamma mode
Date: Fri, 4 Nov 2022 11:42:50 +0200 [thread overview]
Message-ID: <Y2Temsw9pX+KEy2E@intel.com> (raw)
In-Reply-To: <ae278ba0-f13a-8218-3b82-76b634deadb0@intel.com>
On Fri, Nov 04, 2022 at 10:49:39AM +0530, Nautiyal, Ankit K wrote:
> Patch looks good to me.
>
> Minor suggestions inline:
>
> On 10/26/2022 5:09 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Currently when opeating in split gamma mode we do the
> nitpick: 'operating' typo.
> > "skip ever other sw LUT entry" trick in the low level
> > LUT programming/readout functions. That is very annoying
> > and a big hinderance to revamping the color management
> > uapi.
> >
> > Let's get rid of that problem by making half sized copies
> > of the software LUTs and plugging those into the internal
> > {pre,post}_csc_lut attachment points (instead of the sticking
> > the uapi provide sw LUTs there directly).
> >
> > With this the low level stuff will operate purely in terms
> > the hardware LUT sizes, and all uapi nonsense is contained
> > to the atomic check phase. The one thing we do lose is
> > intel_color_assert_luts() since we no longer have a way to
> > check that the uapi LUTs were correctly used when generating
> > the internal copies. But that seems like a price worth paying.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_color.c | 81 +++++++++++++++++-----
> > 1 file changed, 64 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> > index 33871bfacee7..d48904f90e3a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -597,6 +597,30 @@ create_linear_lut(struct drm_i915_private *i915, int lut_size)
> > return blob;
> > }
> >
> > +static struct drm_property_blob *
> > +create_resized_lut(struct drm_i915_private *i915,
> > + const struct drm_property_blob *blob_in, int lut_out_size)
> > +{
> > + int i, lut_in_size = drm_color_lut_size(blob_in);
> > + struct drm_property_blob *blob_out;
> > + const struct drm_color_lut *lut_in;
> > + struct drm_color_lut *lut_out;
> > +
> > + blob_out = drm_property_create_blob(&i915->drm,
> > + sizeof(lut_out[0]) * lut_out_size,
> > + NULL);
> > + if (IS_ERR(blob_out))
> > + return blob_out;
> > +
> > + lut_in = blob_in->data;
> > + lut_out = blob_out->data;
> > +
> > + for (i = 0; i < lut_out_size; i++)
> > + lut_out[i] = lut_in[i * (lut_in_size - 1) / (lut_out_size - 1)];
> > +
> > + return blob_out;
> > +}
> > +
> > static void i9xx_load_lut_8(struct intel_crtc *crtc,
> > const struct drm_property_blob *blob)
> > {
> > @@ -723,19 +747,14 @@ static void ivb_load_lut_10(struct intel_crtc *crtc,
> > u32 prec_index)
> > {
> > struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > - int hw_lut_size = ivb_lut_10_size(prec_index);
> > const struct drm_color_lut *lut = blob->data;
> > int i, lut_size = drm_color_lut_size(blob);
> > enum pipe pipe = crtc->pipe;
> >
> > - for (i = 0; i < hw_lut_size; i++) {
> > - /* We discard half the user entries in split gamma mode */
> > - const struct drm_color_lut *entry =
> > - &lut[i * (lut_size - 1) / (hw_lut_size - 1)];
> > -
> > + for (i = 0; i < lut_size; i++) {
> > intel_de_write_fw(i915, PREC_PAL_INDEX(pipe), prec_index++);
> > intel_de_write_fw(i915, PREC_PAL_DATA(pipe),
> > - ilk_lut_10(entry));
> > + ilk_lut_10(&lut[i]));
> > }
> >
> > /*
> > @@ -751,7 +770,6 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
> > u32 prec_index)
> > {
> > struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > - int hw_lut_size = ivb_lut_10_size(prec_index);
> > const struct drm_color_lut *lut = blob->data;
> > int i, lut_size = drm_color_lut_size(blob);
> > enum pipe pipe = crtc->pipe;
> > @@ -759,14 +777,9 @@ static void bdw_load_lut_10(struct intel_crtc *crtc,
> > intel_de_write_fw(i915, PREC_PAL_INDEX(pipe),
> > prec_index | PAL_PREC_AUTO_INCREMENT);
> >
> > - for (i = 0; i < hw_lut_size; i++) {
> > - /* We discard half the user entries in split gamma mode */
> > - const struct drm_color_lut *entry =
> > - &lut[i * (lut_size - 1) / (hw_lut_size - 1)];
> > -
> > + for (i = 0; i < lut_size; i++)
> > intel_de_write_fw(i915, PREC_PAL_DATA(pipe),
> > - ilk_lut_10(entry));
> > - }
> > + ilk_lut_10(&lut[i]));
> >
> > /*
> > * Reset the index, otherwise it prevents the legacy palette to be
> > @@ -1343,7 +1356,7 @@ void intel_color_assert_luts(const struct intel_crtc_state *crtc_state)
> > crtc_state->pre_csc_lut != i915->display.color.glk_linear_degamma_lut);
> > drm_WARN_ON(&i915->drm,
> > crtc_state->post_csc_lut != crtc_state->hw.gamma_lut);
> > - } else {
> > + } else if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) {
> > drm_WARN_ON(&i915->drm,
> > crtc_state->pre_csc_lut != crtc_state->hw.degamma_lut &&
> > crtc_state->pre_csc_lut != crtc_state->hw.gamma_lut);
> > @@ -1564,6 +1577,38 @@ static u32 ivb_csc_mode(const struct intel_crtc_state *crtc_state)
> > return CSC_POSITION_BEFORE_GAMMA;
> > }
> >
> > +static int ivb_assign_luts(struct intel_crtc_state *crtc_state)
> > +{
> > + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> > + struct drm_property_blob *degamma_lut, *gamma_lut;
> > +
> > + if (crtc_state->gamma_mode != GAMMA_MODE_MODE_SPLIT) {
> > + ilk_assign_luts(crtc_state);
> > + return 0;
> > + }
> > +
> > + drm_WARN_ON(&i915->drm, drm_color_lut_size(crtc_state->hw.degamma_lut) != 1024);
> > + drm_WARN_ON(&i915->drm, drm_color_lut_size(crtc_state->hw.gamma_lut) != 1024);
>
> Does it make sense to use some macro for LUT size for split gamma case
> and regular case?
>
> Same thing perhaps can be used in ivb_lut_10_size?
I don't think macros would be really helpful. I guess I
could have used ivb_lut_10_size() for the create_resized_lut()
calls below. And these WARNs I guess could have just used
device info stuff instead. Or I could just drop them entirely
since they aren't really checking anything super important, and
the create_resized_lut() would work with any input LUT size anyway.
Thinking a bit further we could certainly consider extending
the ivb_lut_10_size()/glk_degamma_lut_size() approach to cover
all the gamma modes. Though I think it would probably make sense
to implement that as some kind of struct based approach where we
describe each LUT format in a struct. Would also be more in line
with what we've been thinking for the uapi revamp.
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2022-11-04 9:42 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-26 11:38 [Intel-gfx] [PATCH 00/11] drm/i915: More gamma work Ville Syrjala
2022-10-26 11:38 ` [Intel-gfx] [PATCH 01/11] drm/i915: Use sizeof(variable) instead sizeof(type) Ville Syrjala
2022-11-03 5:29 ` Nautiyal, Ankit K
2022-10-26 11:38 ` [Intel-gfx] [PATCH 02/11] drm/i915: Use _MMIO_PIPE() for SKL_BOTTOM_COLOR Ville Syrjala
2022-11-03 5:38 ` Nautiyal, Ankit K
2022-10-26 11:38 ` [Intel-gfx] [PATCH 03/11] drm/i915: s/dev_priv/i915/ in intel_color.c Ville Syrjala
2022-11-03 5:52 ` Nautiyal, Ankit K
2022-10-26 11:38 ` [Intel-gfx] [PATCH 04/11] drm/i915: s/icl_load_gcmax/ivb_load_lut_max/ Ville Syrjala
2022-11-03 6:19 ` Nautiyal, Ankit K
2022-11-03 9:34 ` Ville Syrjälä
2022-11-03 10:28 ` Nautiyal, Ankit K
2022-10-26 11:39 ` [Intel-gfx] [PATCH 05/11] drm/i915: Split ivb_load_lut_ext_max() into two parts Ville Syrjala
2022-11-03 6:31 ` Nautiyal, Ankit K
2022-10-26 11:39 ` [Intel-gfx] [PATCH 06/11] drm/i915: Deconfuse the ilk+ 12.4 LUT entry functions Ville Syrjala
2022-11-03 7:37 ` Nautiyal, Ankit K
2022-11-03 9:37 ` Ville Syrjälä
2022-10-26 11:39 ` [Intel-gfx] [PATCH 07/11] drm/i915: Pass limited_range explicitly to ilk_csc_convert_ctm() Ville Syrjala
2022-11-03 10:04 ` Nautiyal, Ankit K
2022-10-26 11:39 ` [Intel-gfx] [PATCH 08/11] drm/i915: Reuse ilk_gamma_mode() on ivb+ Ville Syrjala
2022-11-03 10:09 ` Nautiyal, Ankit K
2022-10-26 11:39 ` [Intel-gfx] [PATCH 09/11] drm/i915: Reject YCbCr output with degamma+gamma on pre-icl Ville Syrjala
2022-11-03 10:14 ` Nautiyal, Ankit K
2022-10-26 11:39 ` [Intel-gfx] [PATCH 10/11] drm/i915: Share {csc, gamma}_enable calculation for ilk/snb vs. ivb+ Ville Syrjala
2022-11-03 10:25 ` Nautiyal, Ankit K
2022-10-26 11:39 ` [Intel-gfx] [PATCH 11/11] drm/i915: Create resized LUTs for ivb+ split gamma mode Ville Syrjala
2022-11-04 5:19 ` Nautiyal, Ankit K
2022-11-04 9:42 ` Ville Syrjälä [this message]
2022-11-10 4:05 ` Nautiyal, Ankit K
2022-11-10 7:23 ` Ville Syrjälä
2022-10-26 12:27 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: More gamma work Patchwork
2022-10-26 12:50 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-10-26 23:25 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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