* [Intel-gfx] [PATCH v3 0/5] Asynchronous flip implementation for i915
@ 2020-05-28 5:39 Karthik B S
2020-05-28 5:39 ` [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler Karthik B S
` (9 more replies)
0 siblings, 10 replies; 22+ messages in thread
From: Karthik B S @ 2020-05-28 5:39 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni
Without async flip support in the kernel, fullscreen apps where game
resolution is equal to the screen resolution, must perform an extra blit
per frame prior to flipping.
Asynchronous page flips will also boost the FPS of Mesa benchmarks.
v2: Few patches have been squashed and patches have been shuffled as
per the reviews on the previous version.
v3: Few patches have been squashed and patches have been shuffled as
per the reviews on the previous version.
Karthik B S (5):
drm/i915: Add enable/disable flip done and flip done handler
drm/i915: Add support for async flips in I915
drm/i915: Add checks specific to async flips
drm/i915: Do not call drm_crtc_arm_vblank_event in async flips
drm/i915: Enable async flips in i915
drivers/gpu/drm/i915/display/intel_display.c | 71 ++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_sprite.c | 8 ++-
drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++
drivers/gpu/drm/i915/i915_irq.h | 2 +
drivers/gpu/drm/i915/i915_reg.h | 1 +
5 files changed, 133 insertions(+), 1 deletion(-)
--
2.17.1
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler
2020-05-28 5:39 [Intel-gfx] [PATCH v3 0/5] Asynchronous flip implementation for i915 Karthik B S
@ 2020-05-28 5:39 ` Karthik B S
2020-06-10 22:33 ` Paulo Zanoni
2020-05-28 5:39 ` [Intel-gfx] [PATCH v3 2/5] drm/i915: Add support for async flips in I915 Karthik B S
` (8 subsequent siblings)
9 siblings, 1 reply; 22+ messages in thread
From: Karthik B S @ 2020-05-28 5:39 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni
Add enable/disable flip done functions and the flip done handler
function which handles the flip done interrupt.
Enable the flip done interrupt in IER.
Enable flip done function is called before writing the
surface address register as the write to this register triggers
the flip done interrupt
Flip done handler is used to send the page flip event as soon as the
surface address is written as per the requirement of async flips.
The interrupt is disabled after the event is sent.
v2: -Change function name from icl_* to skl_* (Paulo)
-Move flip handler to this patch (Paulo)
-Remove vblank_put() (Paulo)
-Enable flip done interrupt for gen9+ only (Paulo)
-Enable flip done interrupt in power_well_post_enable hook (Paulo)
-Removed the event check in flip done handler to handle async
flips without pageflip events.
v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
-Make the pending vblank event NULL in the begining of
flip_done_handler to remove sporadic WARN_ON that is seen.
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++++
drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++++++++
drivers/gpu/drm/i915/i915_irq.h | 2 +
3 files changed, 64 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index f40b909952cc..48cc1fc9bc5a 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -15530,6 +15530,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
intel_dbuf_pre_plane_update(state);
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ if (new_crtc_state->uapi.async_flip) {
+ skl_enable_flip_done(&crtc->base);
+ break;
+ }
+ }
+
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
dev_priv->display.commit_modeset_enables(state);
@@ -15551,6 +15558,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
drm_atomic_helper_wait_for_flip_done(dev, &state->base);
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ if (new_crtc_state->uapi.async_flip)
+ skl_disable_flip_done(&crtc->base);
+
if (new_crtc_state->hw.active &&
!needs_modeset(new_crtc_state) &&
!new_crtc_state->preload_luts &&
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index efdd4c7b8e92..632e7b1deb87 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1295,6 +1295,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
u32 crc4) {}
#endif
+static void flip_done_handler(struct drm_i915_private *dev_priv,
+ unsigned int pipe)
+{
+ struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
+ struct drm_crtc_state *crtc_state = crtc->base.state;
+ struct drm_pending_vblank_event *e = crtc_state->event;
+ struct drm_device *dev = &dev_priv->drm;
+ unsigned long irqflags;
+
+ crtc_state->event = NULL;
+
+ spin_lock_irqsave(&dev->event_lock, irqflags);
+
+ drm_crtc_send_vblank_event(&crtc->base, e);
+
+ spin_unlock_irqrestore(&dev->event_lock, irqflags);
+}
static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
enum pipe pipe)
@@ -2388,6 +2405,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
if (iir & GEN8_PIPE_VBLANK)
intel_handle_vblank(dev_priv, pipe);
+ if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
+ flip_done_handler(dev_priv, pipe);
+
if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
hsw_pipe_crc_irq_handler(dev_priv, pipe);
@@ -2669,6 +2689,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
return 0;
}
+void skl_enable_flip_done(struct drm_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+
+ bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
+
+ spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+
/* Called from drm generic code, passed 'crtc' which
* we use as a pipe index
*/
@@ -2729,6 +2762,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
+void skl_disable_flip_done(struct drm_crtc *crtc)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+ enum pipe pipe = to_intel_crtc(crtc)->pipe;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+
+ bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
+
+ spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+
static void ibx_irq_reset(struct drm_i915_private *dev_priv)
{
struct intel_uncore *uncore = &dev_priv->uncore;
@@ -2936,6 +2982,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
enum pipe pipe;
+ if (INTEL_GEN(dev_priv) >= 9)
+ extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
+
spin_lock_irq(&dev_priv->irq_lock);
if (!intel_irqs_enabled(dev_priv)) {
@@ -3410,6 +3459,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
GEN8_PIPE_FIFO_UNDERRUN;
+ if (INTEL_GEN(dev_priv) >= 9)
+ de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
+
de_port_enables = de_port_masked;
if (IS_GEN9_LP(dev_priv))
de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
index 25f25cd95818..2f10c8135116 100644
--- a/drivers/gpu/drm/i915/i915_irq.h
+++ b/drivers/gpu/drm/i915/i915_irq.h
@@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc);
int i965_enable_vblank(struct drm_crtc *crtc);
int ilk_enable_vblank(struct drm_crtc *crtc);
int bdw_enable_vblank(struct drm_crtc *crtc);
+void skl_enable_flip_done(struct drm_crtc *crtc);
void i8xx_disable_vblank(struct drm_crtc *crtc);
void i915gm_disable_vblank(struct drm_crtc *crtc);
void i965_disable_vblank(struct drm_crtc *crtc);
void ilk_disable_vblank(struct drm_crtc *crtc);
void bdw_disable_vblank(struct drm_crtc *crtc);
+void skl_disable_flip_done(struct drm_crtc *crtc);
void gen2_irq_reset(struct intel_uncore *uncore);
void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
--
2.17.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v3 2/5] drm/i915: Add support for async flips in I915
2020-05-28 5:39 [Intel-gfx] [PATCH v3 0/5] Asynchronous flip implementation for i915 Karthik B S
2020-05-28 5:39 ` [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler Karthik B S
@ 2020-05-28 5:39 ` Karthik B S
2020-05-28 5:39 ` [Intel-gfx] [PATCH v3 3/5] drm/i915: Add checks specific to async flips Karthik B S
` (7 subsequent siblings)
9 siblings, 0 replies; 22+ messages in thread
From: Karthik B S @ 2020-05-28 5:39 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni
Set the Async Address Update Enable bit in plane ctl
when async flip is requested.
v2: -Move the Async flip enablement to individual patch (Paulo)
v3: -Rebased.
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
drivers/gpu/drm/i915/i915_reg.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 48cc1fc9bc5a..eb1c360431ae 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4766,6 +4766,9 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
plane_ctl |= PLANE_CTL_YUV_RANGE_CORRECTION_DISABLE;
}
+ if (crtc_state->uapi.async_flip)
+ plane_ctl |= PLANE_CTL_ASYNC_FLIP;
+
plane_ctl |= skl_plane_ctl_format(fb->format->format);
plane_ctl |= skl_plane_ctl_tiling(fb->modifier);
plane_ctl |= skl_plane_ctl_rotate(rotation & DRM_MODE_ROTATE_MASK);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index e9d50fe0f375..f01258bb6154 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6871,6 +6871,7 @@ enum {
#define PLANE_CTL_TILED_X (1 << 10)
#define PLANE_CTL_TILED_Y (4 << 10)
#define PLANE_CTL_TILED_YF (5 << 10)
+#define PLANE_CTL_ASYNC_FLIP (1 << 9)
#define PLANE_CTL_FLIP_HORIZONTAL (1 << 8)
#define PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE (1 << 4) /* TGL+ */
#define PLANE_CTL_ALPHA_MASK (0x3 << 4) /* Pre-GLK */
--
2.17.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v3 3/5] drm/i915: Add checks specific to async flips
2020-05-28 5:39 [Intel-gfx] [PATCH v3 0/5] Asynchronous flip implementation for i915 Karthik B S
2020-05-28 5:39 ` [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler Karthik B S
2020-05-28 5:39 ` [Intel-gfx] [PATCH v3 2/5] drm/i915: Add support for async flips in I915 Karthik B S
@ 2020-05-28 5:39 ` Karthik B S
2020-06-17 15:57 ` Ville Syrjälä
2020-05-28 5:39 ` [Intel-gfx] [PATCH v3 4/5] drm/i915: Do not call drm_crtc_arm_vblank_event in " Karthik B S
` (6 subsequent siblings)
9 siblings, 1 reply; 22+ messages in thread
From: Karthik B S @ 2020-05-28 5:39 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni
Support added only for async flips on primary plane.
If flip is requested on any other plane, reject it.
Make sure there is no change in fbc, offset and framebuffer modifiers
when async flip is requested.
If any of these are modified, reject async flip.
v2: -Replace DRM_ERROR (Paulo)
-Add check for changes in OFFSET, FBC, RC(Paulo)
v3: -Removed TODO as benchmarking tests have been run now.
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 55 ++++++++++++++++++++
1 file changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index eb1c360431ae..2307f924732c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14798,6 +14798,53 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
return false;
}
+static int intel_atomic_check_async(struct intel_atomic_state *state)
+{
+ struct drm_plane *plane;
+ struct drm_plane_state *plane_state;
+ struct intel_crtc_state *old_crtc_state, *new_crtc_state;
+ struct intel_plane_state *new_plane_state, *old_plane_state;
+ struct intel_crtc *crtc;
+ struct intel_plane *intel_plane;
+ int i, j;
+
+ /*FIXME: Async flip is only supported for primary plane currently
+ * Support for overlays to be added.
+ */
+ for_each_new_plane_in_state(&state->base, plane, plane_state, j) {
+ if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
+ DRM_DEBUG_KMS("Async flips is NOT supported for non-primary plane\n");
+ return -EINVAL;
+ }
+ }
+
+ for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+ new_crtc_state, i) {
+ if (old_crtc_state->enable_fbc != new_crtc_state->enable_fbc) {
+ DRM_DEBUG_KMS("FBC status cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+ }
+
+ for_each_oldnew_intel_plane_in_state(state, intel_plane, old_plane_state,
+ new_plane_state, i) {
+ if ((old_plane_state->color_plane[0].x !=
+ new_plane_state->color_plane[0].x) ||
+ (old_plane_state->color_plane[0].y !=
+ new_plane_state->color_plane[0].y)) {
+ DRM_DEBUG_KMS("Offsets cannot be changed in async\n");
+ return -EINVAL;
+ }
+
+ if (old_plane_state->uapi.fb->modifier !=
+ new_plane_state->uapi.fb->modifier) {
+ DRM_DEBUG_KMS("Framebuffer modifiers cannot be changed in async flip\n");
+ return -EINVAL;
+ }
+ }
+ return 0;
+}
+
/**
* intel_atomic_check - validate state object
* @dev: drm device
@@ -14825,6 +14872,14 @@ static int intel_atomic_check(struct drm_device *dev,
if (ret)
goto fail;
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ if (new_crtc_state->uapi.async_flip) {
+ ret = intel_atomic_check_async(state);
+ if (ret)
+ goto fail;
+ }
+ }
+
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
if (!needs_modeset(new_crtc_state)) {
--
2.17.1
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v3 4/5] drm/i915: Do not call drm_crtc_arm_vblank_event in async flips
2020-05-28 5:39 [Intel-gfx] [PATCH v3 0/5] Asynchronous flip implementation for i915 Karthik B S
` (2 preceding siblings ...)
2020-05-28 5:39 ` [Intel-gfx] [PATCH v3 3/5] drm/i915: Add checks specific to async flips Karthik B S
@ 2020-05-28 5:39 ` Karthik B S
2020-05-28 5:39 ` [Intel-gfx] [PATCH v3 5/5] drm/i915: Enable async flips in i915 Karthik B S
` (5 subsequent siblings)
9 siblings, 0 replies; 22+ messages in thread
From: Karthik B S @ 2020-05-28 5:39 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni
Since the flip done event will be sent in the flip_done_handler,
no need to add the event to the list and delay it for later.
v2: -Moved the async check above vblank_get as it
was causing issues for PSR.
v3: -No need to wait for vblank to pass, as this wait was causing a
16ms delay once every few flips.
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
---
drivers/gpu/drm/i915/display/intel_sprite.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c
index 571c36f929bd..a67621887c42 100644
--- a/drivers/gpu/drm/i915/display/intel_sprite.c
+++ b/drivers/gpu/drm/i915/display/intel_sprite.c
@@ -92,6 +92,9 @@ void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
DEFINE_WAIT(wait);
u32 psr_status;
+ if (new_crtc_state->uapi.async_flip)
+ goto irq_disable;
+
vblank_start = adjusted_mode->crtc_vblank_start;
if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
vblank_start = DIV_ROUND_UP(vblank_start, 2);
@@ -205,7 +208,7 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
* Would be slightly nice to just grab the vblank count and arm the
* event outside of the critical section - the spinlock might spin for a
* while ... */
- if (new_crtc_state->uapi.event) {
+ if (new_crtc_state->uapi.event && !new_crtc_state->uapi.async_flip) {
drm_WARN_ON(&dev_priv->drm,
drm_crtc_vblank_get(&crtc->base) != 0);
@@ -219,6 +222,9 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
local_irq_enable();
+ if (new_crtc_state->uapi.async_flip)
+ return;
+
if (intel_vgpu_active(dev_priv))
return;
--
2.17.1
_______________________________________________
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^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] [PATCH v3 5/5] drm/i915: Enable async flips in i915
2020-05-28 5:39 [Intel-gfx] [PATCH v3 0/5] Asynchronous flip implementation for i915 Karthik B S
` (3 preceding siblings ...)
2020-05-28 5:39 ` [Intel-gfx] [PATCH v3 4/5] drm/i915: Do not call drm_crtc_arm_vblank_event in " Karthik B S
@ 2020-05-28 5:39 ` Karthik B S
2020-05-28 6:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Asynchronous flip implementation for i915 (rev3) Patchwork
` (4 subsequent siblings)
9 siblings, 0 replies; 22+ messages in thread
From: Karthik B S @ 2020-05-28 5:39 UTC (permalink / raw)
To: intel-gfx; +Cc: paulo.r.zanoni
Enable asynchronous flips in i915 for gen9+ platforms.
v2: -Async flip enablement should be a stand alone patch (Paulo)
v3: -Move the patch to the end of the serires (Paulo)
Signed-off-by: Karthik B S <karthik.b.s@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2307f924732c..05720ce613c6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17787,6 +17787,9 @@ static void intel_mode_config_init(struct drm_i915_private *i915)
mode_config->funcs = &intel_mode_funcs;
+ if (INTEL_GEN(i915) >= 9)
+ mode_config->async_page_flip = true;
+
/*
* Maximum framebuffer dimensions, chosen to match
* the maximum render engine surface size on gen4+.
--
2.17.1
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^ permalink raw reply related [flat|nested] 22+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Asynchronous flip implementation for i915 (rev3)
2020-05-28 5:39 [Intel-gfx] [PATCH v3 0/5] Asynchronous flip implementation for i915 Karthik B S
` (4 preceding siblings ...)
2020-05-28 5:39 ` [Intel-gfx] [PATCH v3 5/5] drm/i915: Enable async flips in i915 Karthik B S
@ 2020-05-28 6:35 ` Patchwork
2020-05-28 6:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
9 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2020-05-28 6:35 UTC (permalink / raw)
To: Karthik B S; +Cc: intel-gfx
== Series Details ==
Series: Asynchronous flip implementation for i915 (rev3)
URL : https://patchwork.freedesktop.org/series/74386/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
239c9f562cbf drm/i915: Add enable/disable flip done and flip done handler
-:28: WARNING:TYPO_SPELLING: 'begining' may be misspelled - perhaps 'beginning'?
#28:
-Make the pending vblank event NULL in the begining of
total: 0 errors, 1 warnings, 0 checks, 123 lines checked
54febd5358c0 drm/i915: Add support for async flips in I915
85045ff08f4f drm/i915: Add checks specific to async flips
-:59: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'old_plane_state->color_plane[0].x !=
new_plane_state->color_plane[0].x'
#59: FILE: drivers/gpu/drm/i915/display/intel_display.c:14830:
+ if ((old_plane_state->color_plane[0].x !=
+ new_plane_state->color_plane[0].x) ||
+ (old_plane_state->color_plane[0].y !=
+ new_plane_state->color_plane[0].y)) {
-:59: CHECK:UNNECESSARY_PARENTHESES: Unnecessary parentheses around 'old_plane_state->color_plane[0].y !=
new_plane_state->color_plane[0].y'
#59: FILE: drivers/gpu/drm/i915/display/intel_display.c:14830:
+ if ((old_plane_state->color_plane[0].x !=
+ new_plane_state->color_plane[0].x) ||
+ (old_plane_state->color_plane[0].y !=
+ new_plane_state->color_plane[0].y)) {
total: 0 errors, 0 warnings, 2 checks, 67 lines checked
35ffa8ae0d13 drm/i915: Do not call drm_crtc_arm_vblank_event in async flips
f13f002114a6 drm/i915: Enable async flips in i915
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Asynchronous flip implementation for i915 (rev3)
2020-05-28 5:39 [Intel-gfx] [PATCH v3 0/5] Asynchronous flip implementation for i915 Karthik B S
` (5 preceding siblings ...)
2020-05-28 6:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Asynchronous flip implementation for i915 (rev3) Patchwork
@ 2020-05-28 6:36 ` Patchwork
2020-05-28 6:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
9 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2020-05-28 6:36 UTC (permalink / raw)
To: Karthik B S; +Cc: intel-gfx
== Series Details ==
Series: Asynchronous flip implementation for i915 (rev3)
URL : https://patchwork.freedesktop.org/series/74386/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.0
Fast mode used, each commit won't be checked separately.
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2274:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2275:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2276:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2277:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2278:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gem/i915_gem_context.c:2279:17: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/intel_reset.c:1310:5: warning: context imbalance in 'intel_gt_reset_trylock' - different lock contexts for basic block
+drivers/gpu/drm/i915/gt/sysfs_engines.c:61:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:62:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gt/sysfs_engines.c:66:10: error: bad integer constant expression
+drivers/gpu/drm/i915/gvt/mmio.c:287:23: warning: memcpy with byte count of 279040
+drivers/gpu/drm/i915/i915_perf.c:1425:15: warning: memset with byte count of 16777216
+drivers/gpu/drm/i915/i915_perf.c:1479:15: warning: memset with byte count of 16777216
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen11_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen12_fwtable_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read64' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_read8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen6_write8' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write16' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write32' - different lock contexts for basic block
+./include/linux/spinlock.h:408:9: warning: context imbalance in 'gen8_write8' - different lock contexts for basic block
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Asynchronous flip implementation for i915 (rev3)
2020-05-28 5:39 [Intel-gfx] [PATCH v3 0/5] Asynchronous flip implementation for i915 Karthik B S
` (6 preceding siblings ...)
2020-05-28 6:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2020-05-28 6:56 ` Patchwork
2020-05-28 8:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-05-28 17:47 ` [Intel-gfx] [PATCH v3 0/5] Asynchronous flip implementation for i915 Paulo Zanoni
9 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2020-05-28 6:56 UTC (permalink / raw)
To: Karthik B S; +Cc: intel-gfx
== Series Details ==
Series: Asynchronous flip implementation for i915 (rev3)
URL : https://patchwork.freedesktop.org/series/74386/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8544 -> Patchwork_17799
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/index.html
Known issues
------------
Here are the changes found in Patchwork_17799 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@active:
- fi-icl-u2: [PASS][1] -> [DMESG-FAIL][2] ([i915#765])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/fi-icl-u2/igt@i915_selftest@live@active.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/fi-icl-u2/igt@i915_selftest@live@active.html
#### Possible fixes ####
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-u2: [FAIL][3] ([i915#262]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
[i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262
[i915#765]: https://gitlab.freedesktop.org/drm/intel/issues/765
Participating hosts (49 -> 42)
------------------------------
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_8544 -> Patchwork_17799
CI-20190529: 20190529
CI_DRM_8544: c6c0a18e985d7a3fd4451e0e786e6522371ea9ee @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5680: f7e3772175c53f0c910f4513831791cb5bdcab04 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17799: f13f002114a6588ceb737ef377b3a4cfaaf373bb @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f13f002114a6 drm/i915: Enable async flips in i915
35ffa8ae0d13 drm/i915: Do not call drm_crtc_arm_vblank_event in async flips
85045ff08f4f drm/i915: Add checks specific to async flips
54febd5358c0 drm/i915: Add support for async flips in I915
239c9f562cbf drm/i915: Add enable/disable flip done and flip done handler
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Asynchronous flip implementation for i915 (rev3)
2020-05-28 5:39 [Intel-gfx] [PATCH v3 0/5] Asynchronous flip implementation for i915 Karthik B S
` (7 preceding siblings ...)
2020-05-28 6:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-05-28 8:57 ` Patchwork
2020-05-28 17:47 ` [Intel-gfx] [PATCH v3 0/5] Asynchronous flip implementation for i915 Paulo Zanoni
9 siblings, 0 replies; 22+ messages in thread
From: Patchwork @ 2020-05-28 8:57 UTC (permalink / raw)
To: Karthik B S; +Cc: intel-gfx
== Series Details ==
Series: Asynchronous flip implementation for i915 (rev3)
URL : https://patchwork.freedesktop.org/series/74386/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8544_full -> Patchwork_17799_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_17799_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_workarounds@suspend-resume:
- shard-apl: [PASS][1] -> [DMESG-WARN][2] ([i915#180]) +2 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-apl7/igt@gem_workarounds@suspend-resume.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-apl8/igt@gem_workarounds@suspend-resume.html
* igt@i915_pm_rpm@system-suspend:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#151] / [i915#69])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-skl2/igt@i915_pm_rpm@system-suspend.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-skl3/igt@i915_pm_rpm@system-suspend.html
* igt@i915_suspend@debugfs-reader:
- shard-skl: [PASS][5] -> [INCOMPLETE][6] ([i915#69])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-skl6/igt@i915_suspend@debugfs-reader.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-skl10/igt@i915_suspend@debugfs-reader.html
* igt@kms_busy@basic-flip-pipe-a:
- shard-snb: [PASS][7] -> [SKIP][8] ([fdo#109271]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-snb4/igt@kms_busy@basic-flip-pipe-a.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-snb6/igt@kms_busy@basic-flip-pipe-a.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
- shard-glk: [PASS][9] -> [FAIL][10] ([i915#72])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#109349])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-iclb1/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][13] -> [FAIL][14] ([i915#1188])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-skl1/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][15] -> [FAIL][16] ([fdo#108145] / [i915#265]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-skl4/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +2 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-iclb1/igt@kms_psr@psr2_cursor_render.html
#### Possible fixes ####
* {igt@gem_exec_reloc@basic-concurrent0}:
- shard-glk: [FAIL][19] ([i915#1930]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-glk7/igt@gem_exec_reloc@basic-concurrent0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-glk4/igt@gem_exec_reloc@basic-concurrent0.html
* igt@i915_suspend@forcewake:
- shard-skl: [INCOMPLETE][21] ([i915#636] / [i915#69]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-skl5/igt@i915_suspend@forcewake.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-skl1/igt@i915_suspend@forcewake.html
* igt@kms_big_fb@linear-64bpp-rotate-180:
- shard-glk: [FAIL][23] ([i915#1119] / [i915#118] / [i915#95]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-glk8/igt@kms_big_fb@linear-64bpp-rotate-180.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-glk9/igt@kms_big_fb@linear-64bpp-rotate-180.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [DMESG-WARN][25] ([i915#180]) -> [PASS][26] +2 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-apl: [DMESG-WARN][27] ([i915#180]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-apl6/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-apl7/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen:
- shard-skl: [FAIL][29] ([i915#54]) -> [PASS][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-skl5/igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-skl3/igt@kms_cursor_crc@pipe-c-cursor-128x42-onscreen.html
* {igt@kms_flip@flip-vs-suspend@c-hdmi-a1}:
- shard-hsw: [INCOMPLETE][31] ([i915#61]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-hsw8/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-hsw1/igt@kms_flip@flip-vs-suspend@c-hdmi-a1.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][33] ([i915#1188]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-skl3/igt@kms_hdr@bpc-switch.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-skl2/igt@kms_hdr@bpc-switch.html
* igt@kms_plane@plane-panning-bottom-right-pipe-b-planes:
- shard-skl: [FAIL][35] ([i915#1036]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-skl10/igt@kms_plane@plane-panning-bottom-right-pipe-b-planes.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-skl8/igt@kms_plane@plane-panning-bottom-right-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][37] ([fdo#108145] / [i915#265]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [SKIP][39] ([fdo#109642] / [fdo#111068]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-iclb8/igt@kms_psr2_su@frontbuffer.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][41] ([fdo#109441]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-iclb8/igt@kms_psr@psr2_no_drrs.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
#### Warnings ####
* igt@i915_pm_backlight@fade:
- shard-glk: [TIMEOUT][43] -> [SKIP][44] ([fdo#109271]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-glk6/igt@i915_pm_backlight@fade.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-glk2/igt@i915_pm_backlight@fade.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][45] ([i915#658]) -> [SKIP][46] ([i915#588])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-iclb8/igt@i915_pm_dc@dc3co-vpb-simulation.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: [FAIL][47] ([i915#454]) -> [SKIP][48] ([i915#468])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-tglb1/igt@i915_pm_dc@dc6-psr.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
* igt@kms_content_protection@atomic:
- shard-apl: [FAIL][49] ([fdo#110321] / [fdo#110336]) -> [TIMEOUT][50] ([i915#1319] / [i915#1635])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-apl6/igt@kms_content_protection@atomic.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-apl7/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@legacy:
- shard-apl: [TIMEOUT][51] ([i915#1319] / [i915#1635]) -> [TIMEOUT][52] ([i915#1319])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-apl1/igt@kms_content_protection@legacy.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-apl3/igt@kms_content_protection@legacy.html
* igt@kms_cursor_legacy@cursora-vs-flipb-toggle:
- shard-glk: [DMESG-WARN][53] ([i915#1926]) -> [DMESG-FAIL][54] ([i915#1925])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8544/shard-glk9/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/shard-glk6/igt@kms_cursor_legacy@cursora-vs-flipb-toggle.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[i915#1036]: https://gitlab.freedesktop.org/drm/intel/issues/1036
[i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#1635]: https://gitlab.freedesktop.org/drm/intel/issues/1635
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1925]: https://gitlab.freedesktop.org/drm/intel/issues/1925
[i915#1926]: https://gitlab.freedesktop.org/drm/intel/issues/1926
[i915#1928]: https://gitlab.freedesktop.org/drm/intel/issues/1928
[i915#1930]: https://gitlab.freedesktop.org/drm/intel/issues/1930
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#636]: https://gitlab.freedesktop.org/drm/intel/issues/636
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* Linux: CI_DRM_8544 -> Patchwork_17799
CI-20190529: 20190529
CI_DRM_8544: c6c0a18e985d7a3fd4451e0e786e6522371ea9ee @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5680: f7e3772175c53f0c910f4513831791cb5bdcab04 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17799: f13f002114a6588ceb737ef377b3a4cfaaf373bb @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17799/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v3 0/5] Asynchronous flip implementation for i915
2020-05-28 5:39 [Intel-gfx] [PATCH v3 0/5] Asynchronous flip implementation for i915 Karthik B S
` (8 preceding siblings ...)
2020-05-28 8:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-05-28 17:47 ` Paulo Zanoni
2020-05-29 5:13 ` Karthik B S
9 siblings, 1 reply; 22+ messages in thread
From: Paulo Zanoni @ 2020-05-28 17:47 UTC (permalink / raw)
To: Karthik B S, intel-gfx
Em qui, 2020-05-28 às 11:09 +0530, Karthik B S escreveu:
> Without async flip support in the kernel, fullscreen apps where game
> resolution is equal to the screen resolution, must perform an extra blit
> per frame prior to flipping.
>
> Asynchronous page flips will also boost the FPS of Mesa benchmarks.
>
> v2: Few patches have been squashed and patches have been shuffled as
> per the reviews on the previous version.
>
> v3: Few patches have been squashed and patches have been shuffled as
> per the reviews on the previous version.
Hello
I asked quite a few questions in the review of v2, but never got any
replies. I see some things regarding those questions are different in
v3, but I still would really like to have those answers in direct
text/email form in order to clarify my understanding of your original
intent (and also help me understand why things are different in v3).
Would you mind replying to those emails?
Thanks,
Paulo
>
> Karthik B S (5):
> drm/i915: Add enable/disable flip done and flip done handler
> drm/i915: Add support for async flips in I915
> drm/i915: Add checks specific to async flips
> drm/i915: Do not call drm_crtc_arm_vblank_event in async flips
> drm/i915: Enable async flips in i915
>
> drivers/gpu/drm/i915/display/intel_display.c | 71 ++++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_sprite.c | 8 ++-
> drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++
> drivers/gpu/drm/i915/i915_irq.h | 2 +
> drivers/gpu/drm/i915/i915_reg.h | 1 +
> 5 files changed, 133 insertions(+), 1 deletion(-)
>
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v3 0/5] Asynchronous flip implementation for i915
2020-05-28 17:47 ` [Intel-gfx] [PATCH v3 0/5] Asynchronous flip implementation for i915 Paulo Zanoni
@ 2020-05-29 5:13 ` Karthik B S
0 siblings, 0 replies; 22+ messages in thread
From: Karthik B S @ 2020-05-29 5:13 UTC (permalink / raw)
To: Paulo Zanoni, intel-gfx
On 5/28/2020 11:17 PM, Paulo Zanoni wrote:
> Em qui, 2020-05-28 às 11:09 +0530, Karthik B S escreveu:
>> Without async flip support in the kernel, fullscreen apps where game
>> resolution is equal to the screen resolution, must perform an extra blit
>> per frame prior to flipping.
>>
>> Asynchronous page flips will also boost the FPS of Mesa benchmarks.
>>
>> v2: Few patches have been squashed and patches have been shuffled as
>> per the reviews on the previous version.
>>
>> v3: Few patches have been squashed and patches have been shuffled as
>> per the reviews on the previous version.
>
> Hello
>
> I asked quite a few questions in the review of v2, but never got any
> replies. I see some things regarding those questions are different in
> v3, but I still would really like to have those answers in direct
> text/email form in order to clarify my understanding of your original
> intent (and also help me understand why things are different in v3).
> Would you mind replying to those emails?
Hi,
Sorry for not doing this earlier. I've now responded to the questions on
the v2 of this series.
Thank you for all the reviews.
Thanks,
Karthik.B.S
>
> Thanks,
> Paulo
>
>>
>> Karthik B S (5):
>> drm/i915: Add enable/disable flip done and flip done handler
>> drm/i915: Add support for async flips in I915
>> drm/i915: Add checks specific to async flips
>> drm/i915: Do not call drm_crtc_arm_vblank_event in async flips
>> drm/i915: Enable async flips in i915
>>
>> drivers/gpu/drm/i915/display/intel_display.c | 71 ++++++++++++++++++++
>> drivers/gpu/drm/i915/display/intel_sprite.c | 8 ++-
>> drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++
>> drivers/gpu/drm/i915/i915_irq.h | 2 +
>> drivers/gpu/drm/i915/i915_reg.h | 1 +
>> 5 files changed, 133 insertions(+), 1 deletion(-)
>>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler
2020-05-28 5:39 ` [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler Karthik B S
@ 2020-06-10 22:33 ` Paulo Zanoni
2020-06-17 9:58 ` Daniel Vetter
2020-06-24 11:00 ` Karthik B S
0 siblings, 2 replies; 22+ messages in thread
From: Paulo Zanoni @ 2020-06-10 22:33 UTC (permalink / raw)
To: Karthik B S, intel-gfx; +Cc: Vetter, Daniel
Em qui, 2020-05-28 às 11:09 +0530, Karthik B S escreveu:
> Add enable/disable flip done functions and the flip done handler
> function which handles the flip done interrupt.
>
> Enable the flip done interrupt in IER.
>
> Enable flip done function is called before writing the
> surface address register as the write to this register triggers
> the flip done interrupt
>
> Flip done handler is used to send the page flip event as soon as the
> surface address is written as per the requirement of async flips.
> The interrupt is disabled after the event is sent.
>
> v2: -Change function name from icl_* to skl_* (Paulo)
> -Move flip handler to this patch (Paulo)
> -Remove vblank_put() (Paulo)
> -Enable flip done interrupt for gen9+ only (Paulo)
> -Enable flip done interrupt in power_well_post_enable hook (Paulo)
> -Removed the event check in flip done handler to handle async
> flips without pageflip events.
>
> v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
> -Make the pending vblank event NULL in the begining of
> flip_done_handler to remove sporadic WARN_ON that is seen.
>
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 10 ++++
> drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++++++++
> drivers/gpu/drm/i915/i915_irq.h | 2 +
> 3 files changed, 64 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index f40b909952cc..48cc1fc9bc5a 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -15530,6 +15530,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>
> intel_dbuf_pre_plane_update(state);
>
> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> + if (new_crtc_state->uapi.async_flip) {
> + skl_enable_flip_done(&crtc->base);
> + break;
> + }
> + }
> +
> /* Now enable the clocks, plane, pipe, and connectors that we set up. */
> dev_priv->display.commit_modeset_enables(state);
>
> @@ -15551,6 +15558,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> drm_atomic_helper_wait_for_flip_done(dev, &state->base);
>
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> + if (new_crtc_state->uapi.async_flip)
> + skl_disable_flip_done(&crtc->base);
> +
> if (new_crtc_state->hw.active &&
> !needs_modeset(new_crtc_state) &&
> !new_crtc_state->preload_luts &&
> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> index efdd4c7b8e92..632e7b1deb87 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -1295,6 +1295,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
> u32 crc4) {}
> #endif
>
> +static void flip_done_handler(struct drm_i915_private *dev_priv,
> + unsigned int pipe)
> +{
> + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> + struct drm_crtc_state *crtc_state = crtc->base.state;
> + struct drm_pending_vblank_event *e = crtc_state->event;
> + struct drm_device *dev = &dev_priv->drm;
> + unsigned long irqflags;
> +
> + crtc_state->event = NULL;
> +
> + spin_lock_irqsave(&dev->event_lock, irqflags);
> +
> + drm_crtc_send_vblank_event(&crtc->base, e);
I don't think this is what we want. With this, the events the Kernel
sends us all have the same sequence and timestamp. In fact, the IGT
test you submitted fails because of this.
In my original hackish proof-of-concept patch I had changed
drm_update_vblank_count() to force diff=1 in order to always send
events and I also changed g4x_get_vblank_counter() to get the counter
from FLIPCOUNT (which updates every time there's a flip) instead of
FRMCOUNT (which doesn't seem to increment when you do async flips).
That is a drastic change, but the patch was just a PoC so I didn't care
about keeping anything else working.
One thing that confused me a little bit when dealing the the
vblank/flip event interface from drm.ko is that "flips" and "vblanks"
seem to be changed interchangeably, which is confusing for async flips:
if you keep forever doing async flips in the very first few scanlines
you never actually reach the "vblank" period, yet you keep flipping
your frame. Then, what should your expectation regarding events be?
I think we may need to check how the other drivers handle async vblanks
(or how drm.ko wants us to handle async vblanks). Should we increment
sequence on every async flip? What about the timestamp?
Daniel, Ville, do you happen to know the proper semantics here?
There's certainly some adjustment to do to both this patch and the IGT.
> +
> + spin_unlock_irqrestore(&dev->event_lock, irqflags);
> +}
>
> static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
> enum pipe pipe)
> @@ -2388,6 +2405,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> if (iir & GEN8_PIPE_VBLANK)
> intel_handle_vblank(dev_priv, pipe);
>
> + if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
> + flip_done_handler(dev_priv, pipe);
> +
> if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
> hsw_pipe_crc_irq_handler(dev_priv, pipe);
>
> @@ -2669,6 +2689,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
> return 0;
> }
>
> +void skl_enable_flip_done(struct drm_crtc *crtc)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> + enum pipe pipe = to_intel_crtc(crtc)->pipe;
> + unsigned long irqflags;
> +
> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> +
> + bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
> +
> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> +}
> +
> /* Called from drm generic code, passed 'crtc' which
> * we use as a pipe index
> */
> @@ -2729,6 +2762,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
> spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> }
>
> +void skl_disable_flip_done(struct drm_crtc *crtc)
> +{
> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> + enum pipe pipe = to_intel_crtc(crtc)->pipe;
> + unsigned long irqflags;
> +
> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> +
> + bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
> +
> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> +}
> +
> static void ibx_irq_reset(struct drm_i915_private *dev_priv)
> {
> struct intel_uncore *uncore = &dev_priv->uncore;
> @@ -2936,6 +2982,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
> u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
> enum pipe pipe;
>
> + if (INTEL_GEN(dev_priv) >= 9)
> + extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
> +
> spin_lock_irq(&dev_priv->irq_lock);
>
> if (!intel_irqs_enabled(dev_priv)) {
> @@ -3410,6 +3459,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
> GEN8_PIPE_FIFO_UNDERRUN;
>
> + if (INTEL_GEN(dev_priv) >= 9)
> + de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
> +
> de_port_enables = de_port_masked;
> if (IS_GEN9_LP(dev_priv))
> de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
> index 25f25cd95818..2f10c8135116 100644
> --- a/drivers/gpu/drm/i915/i915_irq.h
> +++ b/drivers/gpu/drm/i915/i915_irq.h
> @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc);
> int i965_enable_vblank(struct drm_crtc *crtc);
> int ilk_enable_vblank(struct drm_crtc *crtc);
> int bdw_enable_vblank(struct drm_crtc *crtc);
> +void skl_enable_flip_done(struct drm_crtc *crtc);
> void i8xx_disable_vblank(struct drm_crtc *crtc);
> void i915gm_disable_vblank(struct drm_crtc *crtc);
> void i965_disable_vblank(struct drm_crtc *crtc);
> void ilk_disable_vblank(struct drm_crtc *crtc);
> void bdw_disable_vblank(struct drm_crtc *crtc);
> +void skl_disable_flip_done(struct drm_crtc *crtc);
>
> void gen2_irq_reset(struct intel_uncore *uncore);
> void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler
2020-06-10 22:33 ` Paulo Zanoni
@ 2020-06-17 9:58 ` Daniel Vetter
2020-06-17 14:45 ` Kazlauskas, Nicholas
` (2 more replies)
2020-06-24 11:00 ` Karthik B S
1 sibling, 3 replies; 22+ messages in thread
From: Daniel Vetter @ 2020-06-17 9:58 UTC (permalink / raw)
To: Paulo Zanoni, dri-devel, Wentland, Harry, Kazlauskas, Nicholas
Cc: Vetter, Daniel, intel-gfx
On Wed, Jun 10, 2020 at 03:33:06PM -0700, Paulo Zanoni wrote:
> Em qui, 2020-05-28 às 11:09 +0530, Karthik B S escreveu:
> > Add enable/disable flip done functions and the flip done handler
> > function which handles the flip done interrupt.
> >
> > Enable the flip done interrupt in IER.
> >
> > Enable flip done function is called before writing the
> > surface address register as the write to this register triggers
> > the flip done interrupt
> >
> > Flip done handler is used to send the page flip event as soon as the
> > surface address is written as per the requirement of async flips.
> > The interrupt is disabled after the event is sent.
> >
> > v2: -Change function name from icl_* to skl_* (Paulo)
> > -Move flip handler to this patch (Paulo)
> > -Remove vblank_put() (Paulo)
> > -Enable flip done interrupt for gen9+ only (Paulo)
> > -Enable flip done interrupt in power_well_post_enable hook (Paulo)
> > -Removed the event check in flip done handler to handle async
> > flips without pageflip events.
> >
> > v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
> > -Make the pending vblank event NULL in the begining of
> > flip_done_handler to remove sporadic WARN_ON that is seen.
> >
> > Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 10 ++++
> > drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++++++++
> > drivers/gpu/drm/i915/i915_irq.h | 2 +
> > 3 files changed, 64 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index f40b909952cc..48cc1fc9bc5a 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -15530,6 +15530,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> >
> > intel_dbuf_pre_plane_update(state);
> >
> > + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > + if (new_crtc_state->uapi.async_flip) {
> > + skl_enable_flip_done(&crtc->base);
> > + break;
> > + }
> > + }
> > +
> > /* Now enable the clocks, plane, pipe, and connectors that we set up. */
> > dev_priv->display.commit_modeset_enables(state);
> >
> > @@ -15551,6 +15558,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > drm_atomic_helper_wait_for_flip_done(dev, &state->base);
> >
> > for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > + if (new_crtc_state->uapi.async_flip)
> > + skl_disable_flip_done(&crtc->base);
> > +
> > if (new_crtc_state->hw.active &&
> > !needs_modeset(new_crtc_state) &&
> > !new_crtc_state->preload_luts &&
> > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > index efdd4c7b8e92..632e7b1deb87 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.c
> > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > @@ -1295,6 +1295,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
> > u32 crc4) {}
> > #endif
> >
> > +static void flip_done_handler(struct drm_i915_private *dev_priv,
> > + unsigned int pipe)
> > +{
> > + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > + struct drm_crtc_state *crtc_state = crtc->base.state;
> > + struct drm_pending_vblank_event *e = crtc_state->event;
> > + struct drm_device *dev = &dev_priv->drm;
> > + unsigned long irqflags;
> > +
> > + crtc_state->event = NULL;
> > +
> > + spin_lock_irqsave(&dev->event_lock, irqflags);
> > +
> > + drm_crtc_send_vblank_event(&crtc->base, e);
>
> I don't think this is what we want. With this, the events the Kernel
> sends us all have the same sequence and timestamp. In fact, the IGT
> test you submitted fails because of this.
>
> In my original hackish proof-of-concept patch I had changed
> drm_update_vblank_count() to force diff=1 in order to always send
> events and I also changed g4x_get_vblank_counter() to get the counter
> from FLIPCOUNT (which updates every time there's a flip) instead of
> FRMCOUNT (which doesn't seem to increment when you do async flips).
> That is a drastic change, but the patch was just a PoC so I didn't care
> about keeping anything else working.
>
> One thing that confused me a little bit when dealing the the
> vblank/flip event interface from drm.ko is that "flips" and "vblanks"
> seem to be changed interchangeably, which is confusing for async flips:
> if you keep forever doing async flips in the very first few scanlines
> you never actually reach the "vblank" period, yet you keep flipping
> your frame. Then, what should your expectation regarding events be?
Hm vblank should keep happening I thought (this isn't VRR or DRRS or PSR
where that changes), no idea why we can't keep sending out vblank
interrupts.
Now flip events look maybe conflated in drm.ko code with vblank events
since most of the time a flip complete happens at exactly the same time
the vblank event. But for async flip this is not the case.
Probably worth it to have new helpers/function in drm_vblank.c for
async flips, so that this is less confusing. Plus good documentation.
> I think we may need to check how the other drivers handle async vblanks
> (or how drm.ko wants us to handle async vblanks). Should we increment
> sequence on every async flip? What about the timestamp?
>
> Daniel, Ville, do you happen to know the proper semantics here?
>
> There's certainly some adjustment to do to both this patch and the IGT.
I think it would be really good if we cc dri-devel on this. amdgpu.ko is
currently the only implementation of async flips, we need to make sure we
are fully aligned on all the semantic details.
That also means that the igt needs to be reviewed and tested by amdgpu
people. Might also be good to get the implementation acked by amd DC
people, just to make triple-sure we have the same semantics and generic
userspace compositors like mutter can use this across drivers. We've had
way too much pain here in the past, especially with the details you point
out here.
Also, I think we need to have updated drm core documentation for async
flips, since the current ones are "do it like amdgpu does it". I think
just documenting the various pieces and flags in detail and how it all
interacts with e.g. other atomic commits and everything else would be
great.
Harry and Nicholaus are the people you want from amd. Added everyone to cc.
-Daniel
>
> > +
> > + spin_unlock_irqrestore(&dev->event_lock, irqflags);
> > +}
> >
> > static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
> > enum pipe pipe)
> > @@ -2388,6 +2405,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> > if (iir & GEN8_PIPE_VBLANK)
> > intel_handle_vblank(dev_priv, pipe);
> >
> > + if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
> > + flip_done_handler(dev_priv, pipe);
> > +
> > if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
> > hsw_pipe_crc_irq_handler(dev_priv, pipe);
> >
> > @@ -2669,6 +2689,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
> > return 0;
> > }
> >
> > +void skl_enable_flip_done(struct drm_crtc *crtc)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> > + enum pipe pipe = to_intel_crtc(crtc)->pipe;
> > + unsigned long irqflags;
> > +
> > + spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> > +
> > + bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
> > +
> > + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> > +}
> > +
> > /* Called from drm generic code, passed 'crtc' which
> > * we use as a pipe index
> > */
> > @@ -2729,6 +2762,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
> > spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> > }
> >
> > +void skl_disable_flip_done(struct drm_crtc *crtc)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> > + enum pipe pipe = to_intel_crtc(crtc)->pipe;
> > + unsigned long irqflags;
> > +
> > + spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
> > +
> > + bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
> > +
> > + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
> > +}
> > +
> > static void ibx_irq_reset(struct drm_i915_private *dev_priv)
> > {
> > struct intel_uncore *uncore = &dev_priv->uncore;
> > @@ -2936,6 +2982,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
> > u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
> > enum pipe pipe;
> >
> > + if (INTEL_GEN(dev_priv) >= 9)
> > + extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
> > +
> > spin_lock_irq(&dev_priv->irq_lock);
> >
> > if (!intel_irqs_enabled(dev_priv)) {
> > @@ -3410,6 +3459,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
> > de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
> > GEN8_PIPE_FIFO_UNDERRUN;
> >
> > + if (INTEL_GEN(dev_priv) >= 9)
> > + de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
> > +
> > de_port_enables = de_port_masked;
> > if (IS_GEN9_LP(dev_priv))
> > de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
> > diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
> > index 25f25cd95818..2f10c8135116 100644
> > --- a/drivers/gpu/drm/i915/i915_irq.h
> > +++ b/drivers/gpu/drm/i915/i915_irq.h
> > @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc);
> > int i965_enable_vblank(struct drm_crtc *crtc);
> > int ilk_enable_vblank(struct drm_crtc *crtc);
> > int bdw_enable_vblank(struct drm_crtc *crtc);
> > +void skl_enable_flip_done(struct drm_crtc *crtc);
> > void i8xx_disable_vblank(struct drm_crtc *crtc);
> > void i915gm_disable_vblank(struct drm_crtc *crtc);
> > void i965_disable_vblank(struct drm_crtc *crtc);
> > void ilk_disable_vblank(struct drm_crtc *crtc);
> > void bdw_disable_vblank(struct drm_crtc *crtc);
> > +void skl_disable_flip_done(struct drm_crtc *crtc);
> >
> > void gen2_irq_reset(struct intel_uncore *uncore);
> > void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler
2020-06-17 9:58 ` Daniel Vetter
@ 2020-06-17 14:45 ` Kazlauskas, Nicholas
2020-06-24 11:29 ` Karthik B S
2020-06-17 15:30 ` Ville Syrjälä
2020-06-24 11:14 ` Karthik B S
2 siblings, 1 reply; 22+ messages in thread
From: Kazlauskas, Nicholas @ 2020-06-17 14:45 UTC (permalink / raw)
To: Daniel Vetter, Paulo Zanoni, dri-devel, Wentland, Harry
Cc: Vetter, Daniel, intel-gfx
On 2020-06-17 5:58 a.m., Daniel Vetter wrote:
> On Wed, Jun 10, 2020 at 03:33:06PM -0700, Paulo Zanoni wrote:
>> Em qui, 2020-05-28 às 11:09 +0530, Karthik B S escreveu:
>>> Add enable/disable flip done functions and the flip done handler
>>> function which handles the flip done interrupt.
>>>
>>> Enable the flip done interrupt in IER.
>>>
>>> Enable flip done function is called before writing the
>>> surface address register as the write to this register triggers
>>> the flip done interrupt
>>>
>>> Flip done handler is used to send the page flip event as soon as the
>>> surface address is written as per the requirement of async flips.
>>> The interrupt is disabled after the event is sent.
>>>
>>> v2: -Change function name from icl_* to skl_* (Paulo)
>>> -Move flip handler to this patch (Paulo)
>>> -Remove vblank_put() (Paulo)
>>> -Enable flip done interrupt for gen9+ only (Paulo)
>>> -Enable flip done interrupt in power_well_post_enable hook (Paulo)
>>> -Removed the event check in flip done handler to handle async
>>> flips without pageflip events.
>>>
>>> v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
>>> -Make the pending vblank event NULL in the begining of
>>> flip_done_handler to remove sporadic WARN_ON that is seen.
>>>
>>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_display.c | 10 ++++
>>> drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++++++++
>>> drivers/gpu/drm/i915/i915_irq.h | 2 +
>>> 3 files changed, 64 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>>> index f40b909952cc..48cc1fc9bc5a 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>> @@ -15530,6 +15530,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>>
>>> intel_dbuf_pre_plane_update(state);
>>>
>>> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>>> + if (new_crtc_state->uapi.async_flip) {
>>> + skl_enable_flip_done(&crtc->base);
>>> + break;
>>> + }
>>> + }
>>> +
>>> /* Now enable the clocks, plane, pipe, and connectors that we set up. */
>>> dev_priv->display.commit_modeset_enables(state);
>>>
>>> @@ -15551,6 +15558,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>> drm_atomic_helper_wait_for_flip_done(dev, &state->base);
>>>
>>> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>>> + if (new_crtc_state->uapi.async_flip)
>>> + skl_disable_flip_done(&crtc->base);
>>> +
>>> if (new_crtc_state->hw.active &&
>>> !needs_modeset(new_crtc_state) &&
>>> !new_crtc_state->preload_luts &&
>>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>>> index efdd4c7b8e92..632e7b1deb87 100644
>>> --- a/drivers/gpu/drm/i915/i915_irq.c
>>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>>> @@ -1295,6 +1295,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>>> u32 crc4) {}
>>> #endif
>>>
>>> +static void flip_done_handler(struct drm_i915_private *dev_priv,
>>> + unsigned int pipe)
>>> +{
>>> + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
>>> + struct drm_crtc_state *crtc_state = crtc->base.state;
>>> + struct drm_pending_vblank_event *e = crtc_state->event;
>>> + struct drm_device *dev = &dev_priv->drm;
>>> + unsigned long irqflags;
>>> +
>>> + crtc_state->event = NULL;
>>> +
>>> + spin_lock_irqsave(&dev->event_lock, irqflags);
>>> +
>>> + drm_crtc_send_vblank_event(&crtc->base, e);
>>
>> I don't think this is what we want. With this, the events the Kernel
>> sends us all have the same sequence and timestamp. In fact, the IGT
>> test you submitted fails because of this.
>>
>> In my original hackish proof-of-concept patch I had changed
>> drm_update_vblank_count() to force diff=1 in order to always send
>> events and I also changed g4x_get_vblank_counter() to get the counter
>> from FLIPCOUNT (which updates every time there's a flip) instead of
>> FRMCOUNT (which doesn't seem to increment when you do async flips).
>> That is a drastic change, but the patch was just a PoC so I didn't care
>> about keeping anything else working.
>>
>> One thing that confused me a little bit when dealing the the
>> vblank/flip event interface from drm.ko is that "flips" and "vblanks"
>> seem to be changed interchangeably, which is confusing for async flips:
>> if you keep forever doing async flips in the very first few scanlines
>> you never actually reach the "vblank" period, yet you keep flipping
>> your frame. Then, what should your expectation regarding events be?
>
> Hm vblank should keep happening I thought (this isn't VRR or DRRS or PSR
> where that changes), no idea why we can't keep sending out vblank
> interrupts.
>
> Now flip events look maybe conflated in drm.ko code with vblank events
> since most of the time a flip complete happens at exactly the same time
> the vblank event. But for async flip this is not the case.
>
> Probably worth it to have new helpers/function in drm_vblank.c for
> async flips, so that this is less confusing. Plus good documentation.
>
>> I think we may need to check how the other drivers handle async vblanks
>> (or how drm.ko wants us to handle async vblanks). Should we increment
>> sequence on every async flip? What about the timestamp?
>>
>> Daniel, Ville, do you happen to know the proper semantics here?
>>
>> There's certainly some adjustment to do to both this patch and the IGT.
>
> I think it would be really good if we cc dri-devel on this. amdgpu.ko is
> currently the only implementation of async flips, we need to make sure we
> are fully aligned on all the semantic details.
>
> That also means that the igt needs to be reviewed and tested by amdgpu
> people. Might also be good to get the implementation acked by amd DC
> people, just to make triple-sure we have the same semantics and generic
> userspace compositors like mutter can use this across drivers. We've had
> way too much pain here in the past, especially with the details you point
> out here.
>
> Also, I think we need to have updated drm core documentation for async
> flips, since the current ones are "do it like amdgpu does it". I think
> just documenting the various pieces and flags in detail and how it all
> interacts with e.g. other atomic commits and everything else would be
> great.
>
> Harry and Nicholaus are the people you want from amd. Added everyone to cc.
> -Daniel
IIRC async flips are treated the same as regular flips from amdgpu
perspective. When the hardware latches the new flip address an interrupt
is triggered and we send back the vblank event from the interrupt
handler immediately.
I think we use the same timestamp calculation code for both paths in
this case where we take the current hpos/vpos and calculate when scanout
is going to actually occur.
Technically we're actually scanning out the framebuffer immediately
though so the timestamp is probably bogus.
The regular vblank handler continues to run as usual in the background,
there's no change to the timing. On newer hardware this triggers around
when the hardware starts preparing the next frame, so close to the
double buffer latch (which is typically in the back porch).
Regards,
Nicholas Kazlauskas
>
>
>>
>>> +
>>> + spin_unlock_irqrestore(&dev->event_lock, irqflags);
>>> +}
>>>
>>> static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>>> enum pipe pipe)
>>> @@ -2388,6 +2405,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>>> if (iir & GEN8_PIPE_VBLANK)
>>> intel_handle_vblank(dev_priv, pipe);
>>>
>>> + if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
>>> + flip_done_handler(dev_priv, pipe);
>>> +
>>> if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
>>> hsw_pipe_crc_irq_handler(dev_priv, pipe);
>>>
>>> @@ -2669,6 +2689,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
>>> return 0;
>>> }
>>>
>>> +void skl_enable_flip_done(struct drm_crtc *crtc)
>>> +{
>>> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>>> + enum pipe pipe = to_intel_crtc(crtc)->pipe;
>>> + unsigned long irqflags;
>>> +
>>> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>>> +
>>> + bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
>>> +
>>> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>>> +}
>>> +
>>> /* Called from drm generic code, passed 'crtc' which
>>> * we use as a pipe index
>>> */
>>> @@ -2729,6 +2762,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
>>> spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>>> }
>>>
>>> +void skl_disable_flip_done(struct drm_crtc *crtc)
>>> +{
>>> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>>> + enum pipe pipe = to_intel_crtc(crtc)->pipe;
>>> + unsigned long irqflags;
>>> +
>>> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>>> +
>>> + bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
>>> +
>>> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>>> +}
>>> +
>>> static void ibx_irq_reset(struct drm_i915_private *dev_priv)
>>> {
>>> struct intel_uncore *uncore = &dev_priv->uncore;
>>> @@ -2936,6 +2982,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
>>> u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
>>> enum pipe pipe;
>>>
>>> + if (INTEL_GEN(dev_priv) >= 9)
>>> + extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
>>> +
>>> spin_lock_irq(&dev_priv->irq_lock);
>>>
>>> if (!intel_irqs_enabled(dev_priv)) {
>>> @@ -3410,6 +3459,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>>> de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
>>> GEN8_PIPE_FIFO_UNDERRUN;
>>>
>>> + if (INTEL_GEN(dev_priv) >= 9)
>>> + de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
>>> +
>>> de_port_enables = de_port_masked;
>>> if (IS_GEN9_LP(dev_priv))
>>> de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
>>> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
>>> index 25f25cd95818..2f10c8135116 100644
>>> --- a/drivers/gpu/drm/i915/i915_irq.h
>>> +++ b/drivers/gpu/drm/i915/i915_irq.h
>>> @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc);
>>> int i965_enable_vblank(struct drm_crtc *crtc);
>>> int ilk_enable_vblank(struct drm_crtc *crtc);
>>> int bdw_enable_vblank(struct drm_crtc *crtc);
>>> +void skl_enable_flip_done(struct drm_crtc *crtc);
>>> void i8xx_disable_vblank(struct drm_crtc *crtc);
>>> void i915gm_disable_vblank(struct drm_crtc *crtc);
>>> void i965_disable_vblank(struct drm_crtc *crtc);
>>> void ilk_disable_vblank(struct drm_crtc *crtc);
>>> void bdw_disable_vblank(struct drm_crtc *crtc);
>>> +void skl_disable_flip_done(struct drm_crtc *crtc);
>>>
>>> void gen2_irq_reset(struct intel_uncore *uncore);
>>> void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch/
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler
2020-06-17 9:58 ` Daniel Vetter
2020-06-17 14:45 ` Kazlauskas, Nicholas
@ 2020-06-17 15:30 ` Ville Syrjälä
2020-06-24 11:39 ` Karthik B S
2020-06-24 11:14 ` Karthik B S
2 siblings, 1 reply; 22+ messages in thread
From: Ville Syrjälä @ 2020-06-17 15:30 UTC (permalink / raw)
To: Daniel Vetter
Cc: Paulo Zanoni, intel-gfx, dri-devel, Vetter, Daniel,
Wentland, Harry, Kazlauskas, Nicholas
On Wed, Jun 17, 2020 at 11:58:10AM +0200, Daniel Vetter wrote:
> On Wed, Jun 10, 2020 at 03:33:06PM -0700, Paulo Zanoni wrote:
> > Em qui, 2020-05-28 às 11:09 +0530, Karthik B S escreveu:
> > > Add enable/disable flip done functions and the flip done handler
> > > function which handles the flip done interrupt.
> > >
> > > Enable the flip done interrupt in IER.
> > >
> > > Enable flip done function is called before writing the
> > > surface address register as the write to this register triggers
> > > the flip done interrupt
> > >
> > > Flip done handler is used to send the page flip event as soon as the
> > > surface address is written as per the requirement of async flips.
> > > The interrupt is disabled after the event is sent.
> > >
> > > v2: -Change function name from icl_* to skl_* (Paulo)
> > > -Move flip handler to this patch (Paulo)
> > > -Remove vblank_put() (Paulo)
> > > -Enable flip done interrupt for gen9+ only (Paulo)
> > > -Enable flip done interrupt in power_well_post_enable hook (Paulo)
> > > -Removed the event check in flip done handler to handle async
> > > flips without pageflip events.
> > >
> > > v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
> > > -Make the pending vblank event NULL in the begining of
> > > flip_done_handler to remove sporadic WARN_ON that is seen.
> > >
> > > Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_display.c | 10 ++++
> > > drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++++++++
> > > drivers/gpu/drm/i915/i915_irq.h | 2 +
> > > 3 files changed, 64 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > > index f40b909952cc..48cc1fc9bc5a 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -15530,6 +15530,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > >
> > > intel_dbuf_pre_plane_update(state);
> > >
> > > + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > > + if (new_crtc_state->uapi.async_flip) {
> > > + skl_enable_flip_done(&crtc->base);
> > > + break;
> > > + }
> > > + }
> > > +
> > > /* Now enable the clocks, plane, pipe, and connectors that we set up. */
> > > dev_priv->display.commit_modeset_enables(state);
> > >
> > > @@ -15551,6 +15558,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
> > > drm_atomic_helper_wait_for_flip_done(dev, &state->base);
> > >
> > > for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > > + if (new_crtc_state->uapi.async_flip)
> > > + skl_disable_flip_done(&crtc->base);
> > > +
> > > if (new_crtc_state->hw.active &&
> > > !needs_modeset(new_crtc_state) &&
> > > !new_crtc_state->preload_luts &&
> > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
> > > index efdd4c7b8e92..632e7b1deb87 100644
> > > --- a/drivers/gpu/drm/i915/i915_irq.c
> > > +++ b/drivers/gpu/drm/i915/i915_irq.c
> > > @@ -1295,6 +1295,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
> > > u32 crc4) {}
> > > #endif
> > >
> > > +static void flip_done_handler(struct drm_i915_private *dev_priv,
> > > + unsigned int pipe)
> > > +{
> > > + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > > + struct drm_crtc_state *crtc_state = crtc->base.state;
> > > + struct drm_pending_vblank_event *e = crtc_state->event;
> > > + struct drm_device *dev = &dev_priv->drm;
> > > + unsigned long irqflags;
> > > +
> > > + crtc_state->event = NULL;
> > > +
> > > + spin_lock_irqsave(&dev->event_lock, irqflags);
> > > +
> > > + drm_crtc_send_vblank_event(&crtc->base, e);
> >
> > I don't think this is what we want. With this, the events the Kernel
> > sends us all have the same sequence and timestamp. In fact, the IGT
> > test you submitted fails because of this.
> >
> > In my original hackish proof-of-concept patch I had changed
> > drm_update_vblank_count() to force diff=1 in order to always send
> > events and I also changed g4x_get_vblank_counter() to get the counter
> > from FLIPCOUNT (which updates every time there's a flip) instead of
> > FRMCOUNT (which doesn't seem to increment when you do async flips).
> > That is a drastic change, but the patch was just a PoC so I didn't care
> > about keeping anything else working.
> >
> > One thing that confused me a little bit when dealing the the
> > vblank/flip event interface from drm.ko is that "flips" and "vblanks"
> > seem to be changed interchangeably, which is confusing for async flips:
> > if you keep forever doing async flips in the very first few scanlines
> > you never actually reach the "vblank" period, yet you keep flipping
> > your frame. Then, what should your expectation regarding events be?
>
> Hm vblank should keep happening I thought (this isn't VRR or DRRS or PSR
> where that changes), no idea why we can't keep sending out vblank
> interrupts.
>
> Now flip events look maybe conflated in drm.ko code with vblank events
> since most of the time a flip complete happens at exactly the same time
> the vblank event. But for async flip this is not the case.
>
> Probably worth it to have new helpers/function in drm_vblank.c for
> async flips, so that this is less confusing. Plus good documentation.
We're going to need three different ways to calculate the flip
timestamps: sync flip, vrr sync flip, async flip.
First one we handle just fine currently since we know know when
the timestamp was sampled and when the vblank ends so we can do
the appropriate correction.
VRR is going to be a bit more interesting since we don't really know how
long the vblank will be. I think we may have to use the frame timestamp
and current timestamp counter to first convert the monotonic timestamp
to correlate with the start of the vblank exit, and then we can move it
forward by the fixed (I think) length of the vblank exit procedure.
For async flip I think we may want to do something similar with the
flip done timestamp and current timestamp (apart from adding the
fixed length of the vblank exit procedure of course, since there
is no vblank exit). Although I'm not entirely sure what we should do
if we do the async flip during the vblank. If we want to maintain
that the timestamp always correlates with the first pixel actually
getting scanned out then we should still correct the timestamp to
point past the end of vblank. And even with the corrections there
will be some amount of error due to the old data first having to
drain out of the FIFO. That error I think we're just going to
have to accept.
Not sure how much surgery all that is going to require to the vblank
timestamping code.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/5] drm/i915: Add checks specific to async flips
2020-05-28 5:39 ` [Intel-gfx] [PATCH v3 3/5] drm/i915: Add checks specific to async flips Karthik B S
@ 2020-06-17 15:57 ` Ville Syrjälä
2020-06-24 11:53 ` Karthik B S
0 siblings, 1 reply; 22+ messages in thread
From: Ville Syrjälä @ 2020-06-17 15:57 UTC (permalink / raw)
To: Karthik B S; +Cc: intel-gfx, paulo.r.zanoni
On Thu, May 28, 2020 at 11:09:29AM +0530, Karthik B S wrote:
> Support added only for async flips on primary plane.
> If flip is requested on any other plane, reject it.
>
> Make sure there is no change in fbc, offset and framebuffer modifiers
> when async flip is requested.
>
> If any of these are modified, reject async flip.
>
> v2: -Replace DRM_ERROR (Paulo)
> -Add check for changes in OFFSET, FBC, RC(Paulo)
>
> v3: -Removed TODO as benchmarking tests have been run now.
>
> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 55 ++++++++++++++++++++
> 1 file changed, 55 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index eb1c360431ae..2307f924732c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14798,6 +14798,53 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
> return false;
> }
>
> +static int intel_atomic_check_async(struct intel_atomic_state *state)
> +{
> + struct drm_plane *plane;
> + struct drm_plane_state *plane_state;
> + struct intel_crtc_state *old_crtc_state, *new_crtc_state;
> + struct intel_plane_state *new_plane_state, *old_plane_state;
> + struct intel_crtc *crtc;
> + struct intel_plane *intel_plane;
> + int i, j;
> +
> + /*FIXME: Async flip is only supported for primary plane currently
> + * Support for overlays to be added.
> + */
> + for_each_new_plane_in_state(&state->base, plane, plane_state, j) {
> + if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
I think skl+ can do async flips on any universal planes. Earlier
platforms were limited to primary only I think. Can't remember if g4x
already had usable async flip via mmio. Pretty sure at least ilk+ had
it.
Also intel_ types are preferred, so this should use those, and I
think since we're talking about hw planes we should rather check for
PLANE_PRIMARY here.
> + DRM_DEBUG_KMS("Async flips is NOT supported for non-primary plane\n");
> + return -EINVAL;
> + }
> + }
> +
> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> + new_crtc_state, i) {
> + if (old_crtc_state->enable_fbc != new_crtc_state->enable_fbc) {
enable_fbc is bork, so this probably doesn't do anything particularly
sensible.
> + DRM_DEBUG_KMS("FBC status cannot be changed in async flip\n");
> + return -EINVAL;
> + }
> + }
> +
> + for_each_oldnew_intel_plane_in_state(state, intel_plane, old_plane_state,
> + new_plane_state, i) {
> + if ((old_plane_state->color_plane[0].x !=
> + new_plane_state->color_plane[0].x) ||
> + (old_plane_state->color_plane[0].y !=
> + new_plane_state->color_plane[0].y)) {
Don't think we've even calculated those by the time you call this. So
this stuff has to be called much later I think.
> + DRM_DEBUG_KMS("Offsets cannot be changed in async\n");
> + return -EINVAL;
> + }
> +
> + if (old_plane_state->uapi.fb->modifier !=
> + new_plane_state->uapi.fb->modifier) {
We seem to be missing a lot of state here. Basically I think async flip
can *only* change the plane surface address, so anything else changing
we should reject. I guess if this comes in via the legacy page flip path
the code/helpers do prevent most other things changing, but not sure.
I don't really like relying on such core checks since someone could
blindly expose this via the atomic ioctl without having those same
restrictions in place.
We might also want a dedicated plane hook for async flips since writing
all the plane registers for these is rather pointless. I'm not even sure
what happens with all the other double buffered registers if you write
them and then do an async surface address update.
Also if we want more accurate timestmaps based on the flip timestamp
register then we're going to have to limit async flips to single plane
per pipe at a time becasue the timestamp can only be sampled from
a single plane.
> + DRM_DEBUG_KMS("Framebuffer modifiers cannot be changed in async flip\n");
> + return -EINVAL;
> + }
> + }
> + return 0;
> +}
> +
> /**
> * intel_atomic_check - validate state object
> * @dev: drm device
> @@ -14825,6 +14872,14 @@ static int intel_atomic_check(struct drm_device *dev,
> if (ret)
> goto fail;
>
> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> + if (new_crtc_state->uapi.async_flip) {
> + ret = intel_atomic_check_async(state);
Kinda redundant to call this multiple times. I think the async_flip flag
is actually misplaced. It should probably be in the drm_atomic_state
instead of the crtc state.
Also still not a huge fan of using the "async flip" termonology in
the drm core. IMO we should just adopt the vulkan terminology for
this stuff so it's obviuos what people mean when they talk about these
things.
> + if (ret)
> + goto fail;
> + }
> + }
> +
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> if (!needs_modeset(new_crtc_state)) {
> --
> 2.17.1
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler
2020-06-10 22:33 ` Paulo Zanoni
2020-06-17 9:58 ` Daniel Vetter
@ 2020-06-24 11:00 ` Karthik B S
1 sibling, 0 replies; 22+ messages in thread
From: Karthik B S @ 2020-06-24 11:00 UTC (permalink / raw)
To: Paulo Zanoni, intel-gfx; +Cc: Vetter, Daniel
On 6/11/2020 4:03 AM, Paulo Zanoni wrote:
> Em qui, 2020-05-28 às 11:09 +0530, Karthik B S escreveu:
>> Add enable/disable flip done functions and the flip done handler
>> function which handles the flip done interrupt.
>>
>> Enable the flip done interrupt in IER.
>>
>> Enable flip done function is called before writing the
>> surface address register as the write to this register triggers
>> the flip done interrupt
>>
>> Flip done handler is used to send the page flip event as soon as the
>> surface address is written as per the requirement of async flips.
>> The interrupt is disabled after the event is sent.
>>
>> v2: -Change function name from icl_* to skl_* (Paulo)
>> -Move flip handler to this patch (Paulo)
>> -Remove vblank_put() (Paulo)
>> -Enable flip done interrupt for gen9+ only (Paulo)
>> -Enable flip done interrupt in power_well_post_enable hook (Paulo)
>> -Removed the event check in flip done handler to handle async
>> flips without pageflip events.
>>
>> v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
>> -Make the pending vblank event NULL in the begining of
>> flip_done_handler to remove sporadic WARN_ON that is seen.
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 10 ++++
>> drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++++++++
>> drivers/gpu/drm/i915/i915_irq.h | 2 +
>> 3 files changed, 64 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index f40b909952cc..48cc1fc9bc5a 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -15530,6 +15530,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>
>> intel_dbuf_pre_plane_update(state);
>>
>> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>> + if (new_crtc_state->uapi.async_flip) {
>> + skl_enable_flip_done(&crtc->base);
>> + break;
>> + }
>> + }
>> +
>> /* Now enable the clocks, plane, pipe, and connectors that we set up. */
>> dev_priv->display.commit_modeset_enables(state);
>>
>> @@ -15551,6 +15558,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>> drm_atomic_helper_wait_for_flip_done(dev, &state->base);
>>
>> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>> + if (new_crtc_state->uapi.async_flip)
>> + skl_disable_flip_done(&crtc->base);
>> +
>> if (new_crtc_state->hw.active &&
>> !needs_modeset(new_crtc_state) &&
>> !new_crtc_state->preload_luts &&
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>> index efdd4c7b8e92..632e7b1deb87 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -1295,6 +1295,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>> u32 crc4) {}
>> #endif
>>
>> +static void flip_done_handler(struct drm_i915_private *dev_priv,
>> + unsigned int pipe)
>> +{
>> + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
>> + struct drm_crtc_state *crtc_state = crtc->base.state;
>> + struct drm_pending_vblank_event *e = crtc_state->event;
>> + struct drm_device *dev = &dev_priv->drm;
>> + unsigned long irqflags;
>> +
>> + crtc_state->event = NULL;
>> +
>> + spin_lock_irqsave(&dev->event_lock, irqflags);
>> +
>> + drm_crtc_send_vblank_event(&crtc->base, e);
>
> I don't think this is what we want. With this, the events the Kernel
> sends us all have the same sequence and timestamp. In fact, the IGT
> test you submitted fails because of this.
>
> In my original hackish proof-of-concept patch I had changed
> drm_update_vblank_count() to force diff=1 in order to always send
> events and I also changed g4x_get_vblank_counter() to get the counter
> from FLIPCOUNT (which updates every time there's a flip) instead of
> FRMCOUNT (which doesn't seem to increment when you do async flips).
> That is a drastic change, but the patch was just a PoC so I didn't care
> about keeping anything else working.
>
> One thing that confused me a little bit when dealing the the
> vblank/flip event interface from drm.ko is that "flips" and "vblanks"
> seem to be changed interchangeably, which is confusing for async flips:
> if you keep forever doing async flips in the very first few scanlines
> you never actually reach the "vblank" period, yet you keep flipping
> your frame. Then, what should your expectation regarding events be?
>
> I think we may need to check how the other drivers handle async vblanks
> (or how drm.ko wants us to handle async vblanks). Should we increment
> sequence on every async flip? What about the timestamp?
>
> Daniel, Ville, do you happen to know the proper semantics here?
>
> There's certainly some adjustment to do to both this patch and the IGT.
Thanks for the review.
I will find the proper way to implement the sequence and time stammping
parts by looking into the other drivers implementation for this.
Also will make the required changes regarding the events to be sent.
Will also look into the other inputs received and make the required
corrections.
Regards,
Karthik.B.S
>
>> +
>> + spin_unlock_irqrestore(&dev->event_lock, irqflags);
>> +}
>>
>> static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>> enum pipe pipe)
>> @@ -2388,6 +2405,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>> if (iir & GEN8_PIPE_VBLANK)
>> intel_handle_vblank(dev_priv, pipe);
>>
>> + if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
>> + flip_done_handler(dev_priv, pipe);
>> +
>> if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
>> hsw_pipe_crc_irq_handler(dev_priv, pipe);
>>
>> @@ -2669,6 +2689,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
>> return 0;
>> }
>>
>> +void skl_enable_flip_done(struct drm_crtc *crtc)
>> +{
>> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>> + enum pipe pipe = to_intel_crtc(crtc)->pipe;
>> + unsigned long irqflags;
>> +
>> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>> +
>> + bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
>> +
>> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>> +}
>> +
>> /* Called from drm generic code, passed 'crtc' which
>> * we use as a pipe index
>> */
>> @@ -2729,6 +2762,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
>> spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>> }
>>
>> +void skl_disable_flip_done(struct drm_crtc *crtc)
>> +{
>> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>> + enum pipe pipe = to_intel_crtc(crtc)->pipe;
>> + unsigned long irqflags;
>> +
>> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>> +
>> + bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
>> +
>> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>> +}
>> +
>> static void ibx_irq_reset(struct drm_i915_private *dev_priv)
>> {
>> struct intel_uncore *uncore = &dev_priv->uncore;
>> @@ -2936,6 +2982,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
>> u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
>> enum pipe pipe;
>>
>> + if (INTEL_GEN(dev_priv) >= 9)
>> + extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
>> +
>> spin_lock_irq(&dev_priv->irq_lock);
>>
>> if (!intel_irqs_enabled(dev_priv)) {
>> @@ -3410,6 +3459,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>> de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
>> GEN8_PIPE_FIFO_UNDERRUN;
>>
>> + if (INTEL_GEN(dev_priv) >= 9)
>> + de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
>> +
>> de_port_enables = de_port_masked;
>> if (IS_GEN9_LP(dev_priv))
>> de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
>> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
>> index 25f25cd95818..2f10c8135116 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.h
>> +++ b/drivers/gpu/drm/i915/i915_irq.h
>> @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc);
>> int i965_enable_vblank(struct drm_crtc *crtc);
>> int ilk_enable_vblank(struct drm_crtc *crtc);
>> int bdw_enable_vblank(struct drm_crtc *crtc);
>> +void skl_enable_flip_done(struct drm_crtc *crtc);
>> void i8xx_disable_vblank(struct drm_crtc *crtc);
>> void i915gm_disable_vblank(struct drm_crtc *crtc);
>> void i965_disable_vblank(struct drm_crtc *crtc);
>> void ilk_disable_vblank(struct drm_crtc *crtc);
>> void bdw_disable_vblank(struct drm_crtc *crtc);
>> +void skl_disable_flip_done(struct drm_crtc *crtc);
>>
>> void gen2_irq_reset(struct intel_uncore *uncore);
>> void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
>
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler
2020-06-17 9:58 ` Daniel Vetter
2020-06-17 14:45 ` Kazlauskas, Nicholas
2020-06-17 15:30 ` Ville Syrjälä
@ 2020-06-24 11:14 ` Karthik B S
2 siblings, 0 replies; 22+ messages in thread
From: Karthik B S @ 2020-06-24 11:14 UTC (permalink / raw)
To: Daniel Vetter, Paulo Zanoni, dri-devel, Wentland, Harry,
Kazlauskas, Nicholas
Cc: Vetter, Daniel, intel-gfx
On 6/17/2020 3:28 PM, Daniel Vetter wrote:
> On Wed, Jun 10, 2020 at 03:33:06PM -0700, Paulo Zanoni wrote:
>> Em qui, 2020-05-28 às 11:09 +0530, Karthik B S escreveu:
>>> Add enable/disable flip done functions and the flip done handler
>>> function which handles the flip done interrupt.
>>>
>>> Enable the flip done interrupt in IER.
>>>
>>> Enable flip done function is called before writing the
>>> surface address register as the write to this register triggers
>>> the flip done interrupt
>>>
>>> Flip done handler is used to send the page flip event as soon as the
>>> surface address is written as per the requirement of async flips.
>>> The interrupt is disabled after the event is sent.
>>>
>>> v2: -Change function name from icl_* to skl_* (Paulo)
>>> -Move flip handler to this patch (Paulo)
>>> -Remove vblank_put() (Paulo)
>>> -Enable flip done interrupt for gen9+ only (Paulo)
>>> -Enable flip done interrupt in power_well_post_enable hook (Paulo)
>>> -Removed the event check in flip done handler to handle async
>>> flips without pageflip events.
>>>
>>> v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
>>> -Make the pending vblank event NULL in the begining of
>>> flip_done_handler to remove sporadic WARN_ON that is seen.
>>>
>>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/display/intel_display.c | 10 ++++
>>> drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++++++++
>>> drivers/gpu/drm/i915/i915_irq.h | 2 +
>>> 3 files changed, 64 insertions(+)
>>>
>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>>> index f40b909952cc..48cc1fc9bc5a 100644
>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>> @@ -15530,6 +15530,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>>
>>> intel_dbuf_pre_plane_update(state);
>>>
>>> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>>> + if (new_crtc_state->uapi.async_flip) {
>>> + skl_enable_flip_done(&crtc->base);
>>> + break;
>>> + }
>>> + }
>>> +
>>> /* Now enable the clocks, plane, pipe, and connectors that we set up. */
>>> dev_priv->display.commit_modeset_enables(state);
>>>
>>> @@ -15551,6 +15558,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>> drm_atomic_helper_wait_for_flip_done(dev, &state->base);
>>>
>>> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>>> + if (new_crtc_state->uapi.async_flip)
>>> + skl_disable_flip_done(&crtc->base);
>>> +
>>> if (new_crtc_state->hw.active &&
>>> !needs_modeset(new_crtc_state) &&
>>> !new_crtc_state->preload_luts &&
>>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>>> index efdd4c7b8e92..632e7b1deb87 100644
>>> --- a/drivers/gpu/drm/i915/i915_irq.c
>>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>>> @@ -1295,6 +1295,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>>> u32 crc4) {}
>>> #endif
>>>
>>> +static void flip_done_handler(struct drm_i915_private *dev_priv,
>>> + unsigned int pipe)
>>> +{
>>> + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
>>> + struct drm_crtc_state *crtc_state = crtc->base.state;
>>> + struct drm_pending_vblank_event *e = crtc_state->event;
>>> + struct drm_device *dev = &dev_priv->drm;
>>> + unsigned long irqflags;
>>> +
>>> + crtc_state->event = NULL;
>>> +
>>> + spin_lock_irqsave(&dev->event_lock, irqflags);
>>> +
>>> + drm_crtc_send_vblank_event(&crtc->base, e);
>>
>> I don't think this is what we want. With this, the events the Kernel
>> sends us all have the same sequence and timestamp. In fact, the IGT
>> test you submitted fails because of this.
>>
>> In my original hackish proof-of-concept patch I had changed
>> drm_update_vblank_count() to force diff=1 in order to always send
>> events and I also changed g4x_get_vblank_counter() to get the counter
>> from FLIPCOUNT (which updates every time there's a flip) instead of
>> FRMCOUNT (which doesn't seem to increment when you do async flips).
>> That is a drastic change, but the patch was just a PoC so I didn't care
>> about keeping anything else working.
>>
>> One thing that confused me a little bit when dealing the the
>> vblank/flip event interface from drm.ko is that "flips" and "vblanks"
>> seem to be changed interchangeably, which is confusing for async flips:
>> if you keep forever doing async flips in the very first few scanlines
>> you never actually reach the "vblank" period, yet you keep flipping
>> your frame. Then, what should your expectation regarding events be?
>
> Hm vblank should keep happening I thought (this isn't VRR or DRRS or PSR
> where that changes), no idea why we can't keep sending out vblank
> interrupts.
Thanks for the review.
I was facing a race which lead the complete system to freeze with
vblanks being enabled during async flips. Thus had made this change.
But I'll find a proper implementation for this and enable the vblank
interrupts as well.
>
> Now flip events look maybe conflated in drm.ko code with vblank events
> since most of the time a flip complete happens at exactly the same time
> the vblank event. But for async flip this is not the case.
>
> Probably worth it to have new helpers/function in drm_vblank.c for
> async flips, so that this is less confusing. Plus good documentation.
>
Sure, I'll look into this and make the required additions.
>> I think we may need to check how the other drivers handle async vblanks
>> (or how drm.ko wants us to handle async vblanks). Should we increment
>> sequence on every async flip? What about the timestamp?
>>
>> Daniel, Ville, do you happen to know the proper semantics here?
>>
>> There's certainly some adjustment to do to both this patch and the IGT.
>
> I think it would be really good if we cc dri-devel on this. amdgpu.ko is
> currently the only implementation of async flips, we need to make sure we
> are fully aligned on all the semantic details.
>
Sure, I'll look into the amddgpu.ko and make sure we are aligned.
> That also means that the igt needs to be reviewed and tested by amdgpu
> people. Might also be good to get the implementation acked by amd DC
> people, just to make triple-sure we have the same semantics and generic
> userspace compositors like mutter can use this across drivers. We've had
> way too much pain here in the past, especially with the details you point
> out here.
>
Sure, I'll get the IGT reviewed by the amdgpu and amd DC people.
> Also, I think we need to have updated drm core documentation for async
> flips, since the current ones are "do it like amdgpu does it". I think
> just documenting the various pieces and flags in detail and how it all
> interacts with e.g. other atomic commits and everything else would be
> great.
>
Sure, I'll do this.
> Harry and Nicholaus are the people you want from amd. Added everyone to cc.
Thanks for this.
Thanks and Regards,
Karthik.B.S
> -Daniel
>
>
>>
>>> +
>>> + spin_unlock_irqrestore(&dev->event_lock, irqflags);
>>> +}
>>>
>>> static void hsw_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>>> enum pipe pipe)
>>> @@ -2388,6 +2405,9 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>>> if (iir & GEN8_PIPE_VBLANK)
>>> intel_handle_vblank(dev_priv, pipe);
>>>
>>> + if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
>>> + flip_done_handler(dev_priv, pipe);
>>> +
>>> if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
>>> hsw_pipe_crc_irq_handler(dev_priv, pipe);
>>>
>>> @@ -2669,6 +2689,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
>>> return 0;
>>> }
>>>
>>> +void skl_enable_flip_done(struct drm_crtc *crtc)
>>> +{
>>> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>>> + enum pipe pipe = to_intel_crtc(crtc)->pipe;
>>> + unsigned long irqflags;
>>> +
>>> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>>> +
>>> + bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
>>> +
>>> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>>> +}
>>> +
>>> /* Called from drm generic code, passed 'crtc' which
>>> * we use as a pipe index
>>> */
>>> @@ -2729,6 +2762,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
>>> spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>>> }
>>>
>>> +void skl_disable_flip_done(struct drm_crtc *crtc)
>>> +{
>>> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>>> + enum pipe pipe = to_intel_crtc(crtc)->pipe;
>>> + unsigned long irqflags;
>>> +
>>> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>>> +
>>> + bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
>>> +
>>> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>>> +}
>>> +
>>> static void ibx_irq_reset(struct drm_i915_private *dev_priv)
>>> {
>>> struct intel_uncore *uncore = &dev_priv->uncore;
>>> @@ -2936,6 +2982,9 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
>>> u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
>>> enum pipe pipe;
>>>
>>> + if (INTEL_GEN(dev_priv) >= 9)
>>> + extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
>>> +
>>> spin_lock_irq(&dev_priv->irq_lock);
>>>
>>> if (!intel_irqs_enabled(dev_priv)) {
>>> @@ -3410,6 +3459,9 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
>>> de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
>>> GEN8_PIPE_FIFO_UNDERRUN;
>>>
>>> + if (INTEL_GEN(dev_priv) >= 9)
>>> + de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
>>> +
>>> de_port_enables = de_port_masked;
>>> if (IS_GEN9_LP(dev_priv))
>>> de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
>>> diff --git a/drivers/gpu/drm/i915/i915_irq.h b/drivers/gpu/drm/i915/i915_irq.h
>>> index 25f25cd95818..2f10c8135116 100644
>>> --- a/drivers/gpu/drm/i915/i915_irq.h
>>> +++ b/drivers/gpu/drm/i915/i915_irq.h
>>> @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc);
>>> int i965_enable_vblank(struct drm_crtc *crtc);
>>> int ilk_enable_vblank(struct drm_crtc *crtc);
>>> int bdw_enable_vblank(struct drm_crtc *crtc);
>>> +void skl_enable_flip_done(struct drm_crtc *crtc);
>>> void i8xx_disable_vblank(struct drm_crtc *crtc);
>>> void i915gm_disable_vblank(struct drm_crtc *crtc);
>>> void i965_disable_vblank(struct drm_crtc *crtc);
>>> void ilk_disable_vblank(struct drm_crtc *crtc);
>>> void bdw_disable_vblank(struct drm_crtc *crtc);
>>> +void skl_disable_flip_done(struct drm_crtc *crtc);
>>>
>>> void gen2_irq_reset(struct intel_uncore *uncore);
>>> void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler
2020-06-17 14:45 ` Kazlauskas, Nicholas
@ 2020-06-24 11:29 ` Karthik B S
0 siblings, 0 replies; 22+ messages in thread
From: Karthik B S @ 2020-06-24 11:29 UTC (permalink / raw)
To: Kazlauskas, Nicholas, Daniel Vetter, Paulo Zanoni, dri-devel,
Wentland, Harry
Cc: Vetter, Daniel, intel-gfx
On 6/17/2020 8:15 PM, Kazlauskas, Nicholas wrote:
> On 2020-06-17 5:58 a.m., Daniel Vetter wrote:
>> On Wed, Jun 10, 2020 at 03:33:06PM -0700, Paulo Zanoni wrote:
>>> Em qui, 2020-05-28 às 11:09 +0530, Karthik B S escreveu:
>>>> Add enable/disable flip done functions and the flip done handler
>>>> function which handles the flip done interrupt.
>>>>
>>>> Enable the flip done interrupt in IER.
>>>>
>>>> Enable flip done function is called before writing the
>>>> surface address register as the write to this register triggers
>>>> the flip done interrupt
>>>>
>>>> Flip done handler is used to send the page flip event as soon as the
>>>> surface address is written as per the requirement of async flips.
>>>> The interrupt is disabled after the event is sent.
>>>>
>>>> v2: -Change function name from icl_* to skl_* (Paulo)
>>>> -Move flip handler to this patch (Paulo)
>>>> -Remove vblank_put() (Paulo)
>>>> -Enable flip done interrupt for gen9+ only (Paulo)
>>>> -Enable flip done interrupt in power_well_post_enable hook (Paulo)
>>>> -Removed the event check in flip done handler to handle async
>>>> flips without pageflip events.
>>>>
>>>> v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
>>>> -Make the pending vblank event NULL in the begining of
>>>> flip_done_handler to remove sporadic WARN_ON that is seen.
>>>>
>>>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/display/intel_display.c | 10 ++++
>>>> drivers/gpu/drm/i915/i915_irq.c | 52
>>>> ++++++++++++++++++++
>>>> drivers/gpu/drm/i915/i915_irq.h | 2 +
>>>> 3 files changed, 64 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
>>>> b/drivers/gpu/drm/i915/display/intel_display.c
>>>> index f40b909952cc..48cc1fc9bc5a 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>>> @@ -15530,6 +15530,13 @@ static void intel_atomic_commit_tail(struct
>>>> intel_atomic_state *state)
>>>>
>>>> intel_dbuf_pre_plane_update(state);
>>>>
>>>> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>>>> + if (new_crtc_state->uapi.async_flip) {
>>>> + skl_enable_flip_done(&crtc->base);
>>>> + break;
>>>> + }
>>>> + }
>>>> +
>>>> /* Now enable the clocks, plane, pipe, and connectors that we
>>>> set up. */
>>>> dev_priv->display.commit_modeset_enables(state);
>>>>
>>>> @@ -15551,6 +15558,9 @@ static void intel_atomic_commit_tail(struct
>>>> intel_atomic_state *state)
>>>> drm_atomic_helper_wait_for_flip_done(dev, &state->base);
>>>>
>>>> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>>>> + if (new_crtc_state->uapi.async_flip)
>>>> + skl_disable_flip_done(&crtc->base);
>>>> +
>>>> if (new_crtc_state->hw.active &&
>>>> !needs_modeset(new_crtc_state) &&
>>>> !new_crtc_state->preload_luts &&
>>>> diff --git a/drivers/gpu/drm/i915/i915_irq.c
>>>> b/drivers/gpu/drm/i915/i915_irq.c
>>>> index efdd4c7b8e92..632e7b1deb87 100644
>>>> --- a/drivers/gpu/drm/i915/i915_irq.c
>>>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>>>> @@ -1295,6 +1295,23 @@ display_pipe_crc_irq_handler(struct
>>>> drm_i915_private *dev_priv,
>>>> u32 crc4) {}
>>>> #endif
>>>>
>>>> +static void flip_done_handler(struct drm_i915_private *dev_priv,
>>>> + unsigned int pipe)
>>>> +{
>>>> + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
>>>> + struct drm_crtc_state *crtc_state = crtc->base.state;
>>>> + struct drm_pending_vblank_event *e = crtc_state->event;
>>>> + struct drm_device *dev = &dev_priv->drm;
>>>> + unsigned long irqflags;
>>>> +
>>>> + crtc_state->event = NULL;
>>>> +
>>>> + spin_lock_irqsave(&dev->event_lock, irqflags);
>>>> +
>>>> + drm_crtc_send_vblank_event(&crtc->base, e);
>>>
>>> I don't think this is what we want. With this, the events the Kernel
>>> sends us all have the same sequence and timestamp. In fact, the IGT
>>> test you submitted fails because of this.
>>>
>>> In my original hackish proof-of-concept patch I had changed
>>> drm_update_vblank_count() to force diff=1 in order to always send
>>> events and I also changed g4x_get_vblank_counter() to get the counter
>>> from FLIPCOUNT (which updates every time there's a flip) instead of
>>> FRMCOUNT (which doesn't seem to increment when you do async flips).
>>> That is a drastic change, but the patch was just a PoC so I didn't care
>>> about keeping anything else working.
>>>
>>> One thing that confused me a little bit when dealing the the
>>> vblank/flip event interface from drm.ko is that "flips" and "vblanks"
>>> seem to be changed interchangeably, which is confusing for async flips:
>>> if you keep forever doing async flips in the very first few scanlines
>>> you never actually reach the "vblank" period, yet you keep flipping
>>> your frame. Then, what should your expectation regarding events be?
>>
>> Hm vblank should keep happening I thought (this isn't VRR or DRRS or PSR
>> where that changes), no idea why we can't keep sending out vblank
>> interrupts.
>>
>> Now flip events look maybe conflated in drm.ko code with vblank events
>> since most of the time a flip complete happens at exactly the same time
>> the vblank event. But for async flip this is not the case.
>>
>> Probably worth it to have new helpers/function in drm_vblank.c for
>> async flips, so that this is less confusing. Plus good documentation.
>>
>>> I think we may need to check how the other drivers handle async vblanks
>>> (or how drm.ko wants us to handle async vblanks). Should we increment
>>> sequence on every async flip? What about the timestamp?
>>>
>>> Daniel, Ville, do you happen to know the proper semantics here?
>>>
>>> There's certainly some adjustment to do to both this patch and the IGT.
>>
>> I think it would be really good if we cc dri-devel on this. amdgpu.ko is
>> currently the only implementation of async flips, we need to make sure we
>> are fully aligned on all the semantic details.
>>
>> That also means that the igt needs to be reviewed and tested by amdgpu
>> people. Might also be good to get the implementation acked by amd DC
>> people, just to make triple-sure we have the same semantics and generic
>> userspace compositors like mutter can use this across drivers. We've had
>> way too much pain here in the past, especially with the details you point
>> out here.
>>
>> Also, I think we need to have updated drm core documentation for async
>> flips, since the current ones are "do it like amdgpu does it". I think
>> just documenting the various pieces and flags in detail and how it all
>> interacts with e.g. other atomic commits and everything else would be
>> great.
>>
>> Harry and Nicholaus are the people you want from amd. Added everyone
>> to cc.
>> -Daniel
>
> IIRC async flips are treated the same as regular flips from amdgpu
> perspective. When the hardware latches the new flip address an interrupt
> is triggered and we send back the vblank event from the interrupt
> handler immediately
>
> I think we use the same timestamp calculation code for both paths in
> this case where we take the current hpos/vpos and calculate when scanout
> is going to actually occur.
>
> Technically we're actually scanning out the framebuffer immediately
> though so the timestamp is probably bogus.
>
> The regular vblank handler continues to run as usual in the background,
> there's no change to the timing. On newer hardware this triggers around
> when the hardware starts preparing the next frame, so close to the
> double buffer latch (which is typically in the back porch).
Thanks for the review.
Even in this implementation I've made the changes to send the flip done
event from the interrupt handler itself. But I've not kept the vblank
handler running in background. I'll make the appropriate changes based
on your inputs and make sure the implementation is aligned with the
amdgpu implementation for async flips.
Thanks and Regards,
Karthik.B.S
>
> Regards,
> Nicholas Kazlauskas
>
>>
>>
>>>
>>>> +
>>>> + spin_unlock_irqrestore(&dev->event_lock, irqflags);
>>>> +}
>>>>
>>>> static void hsw_pipe_crc_irq_handler(struct drm_i915_private
>>>> *dev_priv,
>>>> enum pipe pipe)
>>>> @@ -2388,6 +2405,9 @@ gen8_de_irq_handler(struct drm_i915_private
>>>> *dev_priv, u32 master_ctl)
>>>> if (iir & GEN8_PIPE_VBLANK)
>>>> intel_handle_vblank(dev_priv, pipe);
>>>>
>>>> + if (iir & GEN9_PIPE_PLANE1_FLIP_DONE)
>>>> + flip_done_handler(dev_priv, pipe);
>>>> +
>>>> if (iir & GEN8_PIPE_CDCLK_CRC_DONE)
>>>> hsw_pipe_crc_irq_handler(dev_priv, pipe);
>>>>
>>>> @@ -2669,6 +2689,19 @@ int bdw_enable_vblank(struct drm_crtc *crtc)
>>>> return 0;
>>>> }
>>>>
>>>> +void skl_enable_flip_done(struct drm_crtc *crtc)
>>>> +{
>>>> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>>>> + enum pipe pipe = to_intel_crtc(crtc)->pipe;
>>>> + unsigned long irqflags;
>>>> +
>>>> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>>>> +
>>>> + bdw_enable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
>>>> +
>>>> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>>>> +}
>>>> +
>>>> /* Called from drm generic code, passed 'crtc' which
>>>> * we use as a pipe index
>>>> */
>>>> @@ -2729,6 +2762,19 @@ void bdw_disable_vblank(struct drm_crtc *crtc)
>>>> spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>>>> }
>>>>
>>>> +void skl_disable_flip_done(struct drm_crtc *crtc)
>>>> +{
>>>> + struct drm_i915_private *dev_priv = to_i915(crtc->dev);
>>>> + enum pipe pipe = to_intel_crtc(crtc)->pipe;
>>>> + unsigned long irqflags;
>>>> +
>>>> + spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
>>>> +
>>>> + bdw_disable_pipe_irq(dev_priv, pipe, GEN9_PIPE_PLANE1_FLIP_DONE);
>>>> +
>>>> + spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
>>>> +}
>>>> +
>>>> static void ibx_irq_reset(struct drm_i915_private *dev_priv)
>>>> {
>>>> struct intel_uncore *uncore = &dev_priv->uncore;
>>>> @@ -2936,6 +2982,9 @@ void gen8_irq_power_well_post_enable(struct
>>>> drm_i915_private *dev_priv,
>>>> u32 extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
>>>> enum pipe pipe;
>>>>
>>>> + if (INTEL_GEN(dev_priv) >= 9)
>>>> + extra_ier |= GEN9_PIPE_PLANE1_FLIP_DONE;
>>>> +
>>>> spin_lock_irq(&dev_priv->irq_lock);
>>>>
>>>> if (!intel_irqs_enabled(dev_priv)) {
>>>> @@ -3410,6 +3459,9 @@ static void gen8_de_irq_postinstall(struct
>>>> drm_i915_private *dev_priv)
>>>> de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
>>>> GEN8_PIPE_FIFO_UNDERRUN;
>>>>
>>>> + if (INTEL_GEN(dev_priv) >= 9)
>>>> + de_pipe_enables |= GEN9_PIPE_PLANE1_FLIP_DONE;
>>>> +
>>>> de_port_enables = de_port_masked;
>>>> if (IS_GEN9_LP(dev_priv))
>>>> de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
>>>> diff --git a/drivers/gpu/drm/i915/i915_irq.h
>>>> b/drivers/gpu/drm/i915/i915_irq.h
>>>> index 25f25cd95818..2f10c8135116 100644
>>>> --- a/drivers/gpu/drm/i915/i915_irq.h
>>>> +++ b/drivers/gpu/drm/i915/i915_irq.h
>>>> @@ -112,11 +112,13 @@ int i915gm_enable_vblank(struct drm_crtc *crtc);
>>>> int i965_enable_vblank(struct drm_crtc *crtc);
>>>> int ilk_enable_vblank(struct drm_crtc *crtc);
>>>> int bdw_enable_vblank(struct drm_crtc *crtc);
>>>> +void skl_enable_flip_done(struct drm_crtc *crtc);
>>>> void i8xx_disable_vblank(struct drm_crtc *crtc);
>>>> void i915gm_disable_vblank(struct drm_crtc *crtc);
>>>> void i965_disable_vblank(struct drm_crtc *crtc);
>>>> void ilk_disable_vblank(struct drm_crtc *crtc);
>>>> void bdw_disable_vblank(struct drm_crtc *crtc);
>>>> +void skl_disable_flip_done(struct drm_crtc *crtc);
>>>>
>>>> void gen2_irq_reset(struct intel_uncore *uncore);
>>>> void gen3_irq_reset(struct intel_uncore *uncore, i915_reg_t imr,
>>>
>>> _______________________________________________
>>> Intel-gfx mailing list
>>> Intel-gfx@lists.freedesktop.org
>>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>
>> --
>> Daniel Vetter
>> Software Engineer, Intel Corporation
>> http://blog.ffwll.ch/
>>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler
2020-06-17 15:30 ` Ville Syrjälä
@ 2020-06-24 11:39 ` Karthik B S
0 siblings, 0 replies; 22+ messages in thread
From: Karthik B S @ 2020-06-24 11:39 UTC (permalink / raw)
To: Ville Syrjälä, Daniel Vetter
Cc: Paulo Zanoni, intel-gfx, dri-devel, Vetter, Daniel,
Wentland, Harry, Kazlauskas, Nicholas
On 6/17/2020 9:00 PM, Ville Syrjälä wrote:
> On Wed, Jun 17, 2020 at 11:58:10AM +0200, Daniel Vetter wrote:
>> On Wed, Jun 10, 2020 at 03:33:06PM -0700, Paulo Zanoni wrote:
>>> Em qui, 2020-05-28 às 11:09 +0530, Karthik B S escreveu:
>>>> Add enable/disable flip done functions and the flip done handler
>>>> function which handles the flip done interrupt.
>>>>
>>>> Enable the flip done interrupt in IER.
>>>>
>>>> Enable flip done function is called before writing the
>>>> surface address register as the write to this register triggers
>>>> the flip done interrupt
>>>>
>>>> Flip done handler is used to send the page flip event as soon as the
>>>> surface address is written as per the requirement of async flips.
>>>> The interrupt is disabled after the event is sent.
>>>>
>>>> v2: -Change function name from icl_* to skl_* (Paulo)
>>>> -Move flip handler to this patch (Paulo)
>>>> -Remove vblank_put() (Paulo)
>>>> -Enable flip done interrupt for gen9+ only (Paulo)
>>>> -Enable flip done interrupt in power_well_post_enable hook (Paulo)
>>>> -Removed the event check in flip done handler to handle async
>>>> flips without pageflip events.
>>>>
>>>> v3: -Move skl_disable_flip_done out of interrupt handler (Paulo)
>>>> -Make the pending vblank event NULL in the begining of
>>>> flip_done_handler to remove sporadic WARN_ON that is seen.
>>>>
>>>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/display/intel_display.c | 10 ++++
>>>> drivers/gpu/drm/i915/i915_irq.c | 52 ++++++++++++++++++++
>>>> drivers/gpu/drm/i915/i915_irq.h | 2 +
>>>> 3 files changed, 64 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>>>> index f40b909952cc..48cc1fc9bc5a 100644
>>>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>>>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>>>> @@ -15530,6 +15530,13 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>>>
>>>> intel_dbuf_pre_plane_update(state);
>>>>
>>>> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>>>> + if (new_crtc_state->uapi.async_flip) {
>>>> + skl_enable_flip_done(&crtc->base);
>>>> + break;
>>>> + }
>>>> + }
>>>> +
>>>> /* Now enable the clocks, plane, pipe, and connectors that we set up. */
>>>> dev_priv->display.commit_modeset_enables(state);
>>>>
>>>> @@ -15551,6 +15558,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>>>> drm_atomic_helper_wait_for_flip_done(dev, &state->base);
>>>>
>>>> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>>>> + if (new_crtc_state->uapi.async_flip)
>>>> + skl_disable_flip_done(&crtc->base);
>>>> +
>>>> if (new_crtc_state->hw.active &&
>>>> !needs_modeset(new_crtc_state) &&
>>>> !new_crtc_state->preload_luts &&
>>>> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
>>>> index efdd4c7b8e92..632e7b1deb87 100644
>>>> --- a/drivers/gpu/drm/i915/i915_irq.c
>>>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>>>> @@ -1295,6 +1295,23 @@ display_pipe_crc_irq_handler(struct drm_i915_private *dev_priv,
>>>> u32 crc4) {}
>>>> #endif
>>>>
>>>> +static void flip_done_handler(struct drm_i915_private *dev_priv,
>>>> + unsigned int pipe)
>>>> +{
>>>> + struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
>>>> + struct drm_crtc_state *crtc_state = crtc->base.state;
>>>> + struct drm_pending_vblank_event *e = crtc_state->event;
>>>> + struct drm_device *dev = &dev_priv->drm;
>>>> + unsigned long irqflags;
>>>> +
>>>> + crtc_state->event = NULL;
>>>> +
>>>> + spin_lock_irqsave(&dev->event_lock, irqflags);
>>>> +
>>>> + drm_crtc_send_vblank_event(&crtc->base, e);
>>>
>>> I don't think this is what we want. With this, the events the Kernel
>>> sends us all have the same sequence and timestamp. In fact, the IGT
>>> test you submitted fails because of this.
>>>
>>> In my original hackish proof-of-concept patch I had changed
>>> drm_update_vblank_count() to force diff=1 in order to always send
>>> events and I also changed g4x_get_vblank_counter() to get the counter
>>> from FLIPCOUNT (which updates every time there's a flip) instead of
>>> FRMCOUNT (which doesn't seem to increment when you do async flips).
>>> That is a drastic change, but the patch was just a PoC so I didn't care
>>> about keeping anything else working.
>>>
>>> One thing that confused me a little bit when dealing the the
>>> vblank/flip event interface from drm.ko is that "flips" and "vblanks"
>>> seem to be changed interchangeably, which is confusing for async flips:
>>> if you keep forever doing async flips in the very first few scanlines
>>> you never actually reach the "vblank" period, yet you keep flipping
>>> your frame. Then, what should your expectation regarding events be?
>>
>> Hm vblank should keep happening I thought (this isn't VRR or DRRS or PSR
>> where that changes), no idea why we can't keep sending out vblank
>> interrupts.
>>
>> Now flip events look maybe conflated in drm.ko code with vblank events
>> since most of the time a flip complete happens at exactly the same time
>> the vblank event. But for async flip this is not the case.
>>
>> Probably worth it to have new helpers/function in drm_vblank.c for
>> async flips, so that this is less confusing. Plus good documentation.
>
> We're going to need three different ways to calculate the flip
> timestamps: sync flip, vrr sync flip, async flip.
>
> First one we handle just fine currently since we know know when
> the timestamp was sampled and when the vblank ends so we can do
> the appropriate correction.
>
> VRR is going to be a bit more interesting since we don't really know how
> long the vblank will be. I think we may have to use the frame timestamp
> and current timestamp counter to first convert the monotonic timestamp
> to correlate with the start of the vblank exit, and then we can move it
> forward by the fixed (I think) length of the vblank exit procedure.
>
> For async flip I think we may want to do something similar with the
> flip done timestamp and current timestamp (apart from adding the
> fixed length of the vblank exit procedure of course, since there
> is no vblank exit). Although I'm not entirely sure what we should do
> if we do the async flip during the vblank. If we want to maintain
> that the timestamp always correlates with the first pixel actually
> getting scanned out then we should still correct the timestamp to
> point past the end of vblank. And even with the corrections there
> will be some amount of error due to the old data first having to
> drain out of the FIFO. That error I think we're just going to
> have to accept.
>
> Not sure how much surgery all that is going to require to the vblank
> timestamping code.
Thanks for the review.
I'll check what changes needs to be done for this in the timestamping
code and find the right implementation for timestamps based on your inputs.
Thanks and Regards,
Karthik.B.S
>
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [Intel-gfx] [PATCH v3 3/5] drm/i915: Add checks specific to async flips
2020-06-17 15:57 ` Ville Syrjälä
@ 2020-06-24 11:53 ` Karthik B S
0 siblings, 0 replies; 22+ messages in thread
From: Karthik B S @ 2020-06-24 11:53 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, paulo.r.zanoni
On 6/17/2020 9:27 PM, Ville Syrjälä wrote:
> On Thu, May 28, 2020 at 11:09:29AM +0530, Karthik B S wrote:
>> Support added only for async flips on primary plane.
>> If flip is requested on any other plane, reject it.
>>
>> Make sure there is no change in fbc, offset and framebuffer modifiers
>> when async flip is requested.
>>
>> If any of these are modified, reject async flip.
>>
>> v2: -Replace DRM_ERROR (Paulo)
>> -Add check for changes in OFFSET, FBC, RC(Paulo)
>>
>> v3: -Removed TODO as benchmarking tests have been run now.
>>
>> Signed-off-by: Karthik B S <karthik.b.s@intel.com>
>> ---
>> drivers/gpu/drm/i915/display/intel_display.c | 55 ++++++++++++++++++++
>> 1 file changed, 55 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
>> index eb1c360431ae..2307f924732c 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display.c
>> @@ -14798,6 +14798,53 @@ static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
>> return false;
>> }
>>
>> +static int intel_atomic_check_async(struct intel_atomic_state *state)
>> +{
>> + struct drm_plane *plane;
>> + struct drm_plane_state *plane_state;
>> + struct intel_crtc_state *old_crtc_state, *new_crtc_state;
>> + struct intel_plane_state *new_plane_state, *old_plane_state;
>> + struct intel_crtc *crtc;
>> + struct intel_plane *intel_plane;
>> + int i, j;
>> +
>> + /*FIXME: Async flip is only supported for primary plane currently
>> + * Support for overlays to be added.
>> + */
>> + for_each_new_plane_in_state(&state->base, plane, plane_state, j) {
>> + if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
>
> I think skl+ can do async flips on any universal planes. Earlier
> platforms were limited to primary only I think. Can't remember if g4x
> already had usable async flip via mmio. Pretty sure at least ilk+ had
> it.
>
Thanks for the review.
Sure I'll update this.
> Also intel_ types are preferred, so this should use those, and I
> think since we're talking about hw planes we should rather check for
> PLANE_PRIMARY here.
Sure, I'll change this.
>
>> + DRM_DEBUG_KMS("Async flips is NOT supported for non-primary plane\n");
>> + return -EINVAL;
>> + }
>> + }
>> +
>> + for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>> + new_crtc_state, i) {
>> + if (old_crtc_state->enable_fbc != new_crtc_state->enable_fbc) {
>
> enable_fbc is bork, so this probably doesn't do anything particularly
> sensible.
>
Sure. I'll remove this.
>> + DRM_DEBUG_KMS("FBC status cannot be changed in async flip\n");
>> + return -EINVAL;
>> + }
>> + }
>> +
>> + for_each_oldnew_intel_plane_in_state(state, intel_plane, old_plane_state,
>> + new_plane_state, i) {
>> + if ((old_plane_state->color_plane[0].x !=
>> + new_plane_state->color_plane[0].x) ||
>> + (old_plane_state->color_plane[0].y !=
>> + new_plane_state->color_plane[0].y)) {
>
> Don't think we've even calculated those by the time you call this. So
> this stuff has to be called much later I think.
>
Sure. I'll check this and move it to the right place.
>> + DRM_DEBUG_KMS("Offsets cannot be changed in async\n");
>> + return -EINVAL;
>> + }
>> +
>> + if (old_plane_state->uapi.fb->modifier !=
>> + new_plane_state->uapi.fb->modifier) {
>
> We seem to be missing a lot of state here. Basically I think async flip
> can *only* change the plane surface address, so anything else changing
> we should reject. I guess if this comes in via the legacy page flip path
> the code/helpers do prevent most other things changing, but not sure.
> I don't really like relying on such core checks since someone could
> blindly expose this via the atomic ioctl without having those same
> restrictions in place.
>
Yes. I have not added the checks which were present in the legacy page
flip path. Does it mean that I should add those checks also in here? Or
Am I missing something in understanding the comment? Is there any other
way to make sure only the plane surface address is changing.
> We might also want a dedicated plane hook for async flips since writing
> all the plane registers for these is rather pointless. I'm not even sure
> what happens with all the other double buffered registers if you write
> them and then do an async surface address update.
>
Sure. I'll make a dedicated plane hook for async flips so that we only
update the Surface address register here.
> Also if we want more accurate timestmaps based on the flip timestamp
> register then we're going to have to limit async flips to single plane
> per pipe at a time becasue the timestamp can only be sampled from
> a single plane.
>
Sure. I'll make sure async flips are limited to a single plane per pipe.
>> + DRM_DEBUG_KMS("Framebuffer modifiers cannot be changed in async flip\n");
>> + return -EINVAL;
>> + }
>> + }
>> + return 0;
>> +}
>> +
>> /**
>> * intel_atomic_check - validate state object
>> * @dev: drm device
>> @@ -14825,6 +14872,14 @@ static int intel_atomic_check(struct drm_device *dev,
>> if (ret)
>> goto fail;
>>
>> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
>> + if (new_crtc_state->uapi.async_flip) {
>> + ret = intel_atomic_check_async(state);
>
> Kinda redundant to call this multiple times. I think the async_flip flag
> is actually misplaced. It should probably be in the drm_atomic_state
> instead of the crtc state.
>
> Also still not a huge fan of using the "async flip" termonology in
> the drm core. IMO we should just adopt the vulkan terminology for
> this stuff so it's obviuos what people mean when they talk about these
> things.
A little lost here.Could you please help me out? I should move the
async_flip flag to drm_atomic_state from crtc_state and then change its
name? What would be the proper vulkan terminology for this?
Thanks and Regards,
Karthik.B.S
>
>> + if (ret)
>> + goto fail;
>> + }
>> + }
>> +
>> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
>> new_crtc_state, i) {
>> if (!needs_modeset(new_crtc_state)) {
>> --
>> 2.17.1
>
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^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2020-06-24 11:53 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-05-28 5:39 [Intel-gfx] [PATCH v3 0/5] Asynchronous flip implementation for i915 Karthik B S
2020-05-28 5:39 ` [Intel-gfx] [PATCH v3 1/5] drm/i915: Add enable/disable flip done and flip done handler Karthik B S
2020-06-10 22:33 ` Paulo Zanoni
2020-06-17 9:58 ` Daniel Vetter
2020-06-17 14:45 ` Kazlauskas, Nicholas
2020-06-24 11:29 ` Karthik B S
2020-06-17 15:30 ` Ville Syrjälä
2020-06-24 11:39 ` Karthik B S
2020-06-24 11:14 ` Karthik B S
2020-06-24 11:00 ` Karthik B S
2020-05-28 5:39 ` [Intel-gfx] [PATCH v3 2/5] drm/i915: Add support for async flips in I915 Karthik B S
2020-05-28 5:39 ` [Intel-gfx] [PATCH v3 3/5] drm/i915: Add checks specific to async flips Karthik B S
2020-06-17 15:57 ` Ville Syrjälä
2020-06-24 11:53 ` Karthik B S
2020-05-28 5:39 ` [Intel-gfx] [PATCH v3 4/5] drm/i915: Do not call drm_crtc_arm_vblank_event in " Karthik B S
2020-05-28 5:39 ` [Intel-gfx] [PATCH v3 5/5] drm/i915: Enable async flips in i915 Karthik B S
2020-05-28 6:35 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Asynchronous flip implementation for i915 (rev3) Patchwork
2020-05-28 6:36 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-05-28 6:56 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-28 8:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-05-28 17:47 ` [Intel-gfx] [PATCH v3 0/5] Asynchronous flip implementation for i915 Paulo Zanoni
2020-05-29 5:13 ` Karthik B S
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