* [Intel-gfx] [PATCH] drm/i915: use direct alias for i915 in requests
@ 2023-07-19 15:07 Andrzej Hajda
2023-07-19 19:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (11 more replies)
0 siblings, 12 replies; 17+ messages in thread
From: Andrzej Hajda @ 2023-07-19 15:07 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson, Andrzej Hajda, Nirmoy Das
i915_request contains direct alias to i915, there is no point to go via
rq->engine->i915.
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++--
drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 +++++++++---------
.../drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_migrate.c | 10 +++++-----
.../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_rc6.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_timeline.c | 4 ++--
drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 2 +-
drivers/gpu/drm/i915/i915_request.c | 2 +-
drivers/gpu/drm/i915/i915_trace.h | 10 +++++-----
drivers/gpu/drm/i915/selftests/i915_perf.c | 2 +-
drivers/gpu/drm/i915/selftests/igt_spinner.c | 14 +++++++-------
17 files changed, 42 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index d3208a32561442..5a687a3686bd53 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2229,8 +2229,8 @@ static int i915_reset_gen7_sol_offsets(struct i915_request *rq)
u32 *cs;
int i;
- if (GRAPHICS_VER(rq->engine->i915) != 7 || rq->engine->id != RCS0) {
- drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs only\n");
+ if (GRAPHICS_VER(rq->i915) != 7 || rq->engine->id != RCS0) {
+ drm_dbg(&rq->i915->drm, "sol reset is gen7/rcs only\n");
return -EINVAL;
}
diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
index 1c82caf525c346..8fe0499308ffe5 100644
--- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
@@ -76,7 +76,7 @@ int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode)
cmd = MI_FLUSH;
if (mode & EMIT_INVALIDATE) {
cmd |= MI_EXE_FLUSH;
- if (IS_G4X(rq->engine->i915) || GRAPHICS_VER(rq->engine->i915) == 5)
+ if (IS_G4X(rq->i915) || GRAPHICS_VER(rq->i915) == 5)
cmd |= MI_INVALIDATE_ISP;
}
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 23857cc08eca1f..3ba20ea030e8d1 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -39,11 +39,11 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
* On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
* pipe control.
*/
- if (GRAPHICS_VER(rq->engine->i915) == 9)
+ if (GRAPHICS_VER(rq->i915) == 9)
vf_flush_wa = true;
/* WaForGAMHang:kbl */
- if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
+ if (IS_KBL_GRAPHICS_STEP(rq->i915, 0, STEP_C0))
dc_flush_wa = true;
}
@@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
static int mtl_dummy_pipe_control(struct i915_request *rq)
{
/* Wa_14016712196 */
- if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
+ if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {
u32 *cs;
/* dummy PIPE_CONTROL + depth flush */
@@ -267,7 +267,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
else if (engine->class == COMPUTE_CLASS)
flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
- if (!HAS_FLAT_CCS(rq->engine->i915))
+ if (!HAS_FLAT_CCS(rq->i915))
count = 8 + 4;
else
count = 8;
@@ -285,7 +285,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
- if (!HAS_FLAT_CCS(rq->engine->i915)) {
+ if (!HAS_FLAT_CCS(rq->i915)) {
/* hsdes: 1809175790 */
cs = gen12_emit_aux_table_inv(rq->engine->gt,
cs, GEN12_GFX_CCS_AUX_NV);
@@ -307,7 +307,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
if (mode & EMIT_INVALIDATE) {
cmd += 2;
- if (!HAS_FLAT_CCS(rq->engine->i915) &&
+ if (!HAS_FLAT_CCS(rq->i915) &&
(rq->engine->class == VIDEO_DECODE_CLASS ||
rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) {
aux_inv = rq->engine->mask &
@@ -754,7 +754,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
{
- struct drm_i915_private *i915 = rq->engine->i915;
+ struct drm_i915_private *i915 = rq->i915;
u32 flags = (PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_TLB_INVALIDATE |
PIPE_CONTROL_TILE_CACHE_FLUSH |
@@ -775,7 +775,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
/* Wa_1409600907 */
flags |= PIPE_CONTROL_DEPTH_STALL;
- if (!HAS_3D_PIPELINE(rq->engine->i915))
+ if (!HAS_3D_PIPELINE(rq->i915))
flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
else if (rq->engine->class == COMPUTE_CLASS)
flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index d85b5a6d981f99..8a641bcf777cb4 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2718,7 +2718,7 @@ static int emit_pdps(struct i915_request *rq)
int err, i;
u32 *cs;
- GEM_BUG_ON(intel_vgpu_active(rq->engine->i915));
+ GEM_BUG_ON(intel_vgpu_active(rq->i915));
/*
* Beware ye of the dragons, this sequence is magic!
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 6023288b0e2dd5..576e5ef0289ba5 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -366,7 +366,7 @@ static int emit_pte(struct i915_request *rq,
u64 offset,
int length)
{
- bool has_64K_pages = HAS_64K_PAGES(rq->engine->i915);
+ bool has_64K_pages = HAS_64K_PAGES(rq->i915);
const u64 encode = rq->context->vm->pte_encode(0, pat_index,
is_lmem ? PTE_LM : 0);
struct intel_ring *ring = rq->ring;
@@ -375,7 +375,7 @@ static int emit_pte(struct i915_request *rq,
u32 page_size;
u32 *hdr, *cs;
- GEM_BUG_ON(GRAPHICS_VER(rq->engine->i915) < 8);
+ GEM_BUG_ON(GRAPHICS_VER(rq->i915) < 8);
page_size = I915_GTT_PAGE_SIZE;
dword_length = 0x400;
@@ -531,7 +531,7 @@ static int emit_copy_ccs(struct i915_request *rq,
u32 dst_offset, u8 dst_access,
u32 src_offset, u8 src_access, int size)
{
- struct drm_i915_private *i915 = rq->engine->i915;
+ struct drm_i915_private *i915 = rq->i915;
int mocs = rq->engine->gt->mocs.uc_index << 1;
u32 num_ccs_blks;
u32 *cs;
@@ -581,7 +581,7 @@ static int emit_copy_ccs(struct i915_request *rq,
static int emit_copy(struct i915_request *rq,
u32 dst_offset, u32 src_offset, int size)
{
- const int ver = GRAPHICS_VER(rq->engine->i915);
+ const int ver = GRAPHICS_VER(rq->i915);
u32 instance = rq->engine->instance;
u32 *cs;
@@ -917,7 +917,7 @@ intel_context_migrate_copy(struct intel_context *ce,
static int emit_clear(struct i915_request *rq, u32 offset, int size,
u32 value, bool is_lmem)
{
- struct drm_i915_private *i915 = rq->engine->i915;
+ struct drm_i915_private *i915 = rq->i915;
int mocs = rq->engine->gt->mocs.uc_index << 1;
const int ver = GRAPHICS_VER(i915);
int ring_sz;
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 3fd795c3263fd2..92085ffd23de0e 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -805,7 +805,7 @@ static int mi_set_context(struct i915_request *rq,
static int remap_l3_slice(struct i915_request *rq, int slice)
{
#define L3LOG_DW (GEN7_L3LOG_SIZE / sizeof(u32))
- u32 *cs, *remap_info = rq->engine->i915->l3_parity.remap_info[slice];
+ u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
int i;
if (!remap_info)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b177c588698b08..589d009032fcd3 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -3249,7 +3249,7 @@ wa_list_srm(struct i915_request *rq,
const struct i915_wa_list *wal,
struct i915_vma *vma)
{
- struct drm_i915_private *i915 = rq->engine->i915;
+ struct drm_i915_private *i915 = rq->i915;
unsigned int i, count = 0;
const struct i915_wa *wa;
u32 srm, *cs;
@@ -3348,7 +3348,7 @@ static int engine_wa_list_verify(struct intel_context *ce,
err = 0;
for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
- if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg)))
+ if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))
continue;
if (!wa_verify(wal->gt, wa, results[i], wal->name, from))
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
index 78cdfc6f315f2a..86cecf7a110540 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
@@ -62,7 +62,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
return PTR_ERR(cs);
cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
- if (GRAPHICS_VER(rq->engine->i915) >= 8)
+ if (GRAPHICS_VER(rq->i915) >= 8)
cmd++;
*cs++ = cmd;
*cs++ = i915_mmio_reg_offset(timestamp_reg(rq->engine));
diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
index a8446ab825012f..d73e438fb85fab 100644
--- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
@@ -137,7 +137,7 @@ static int read_mocs_table(struct i915_request *rq,
if (!table)
return 0;
- if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915))
+ if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915))
addr = global_mocs_offset() + gt->uncore->gsi_offset;
else
addr = mocs_offset(rq->engine);
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
index 2ceeadecc639cc..a7189c2d660cc5 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
@@ -140,7 +140,7 @@ static const u32 *__live_rc6_ctx(struct intel_context *ce)
}
cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
- if (GRAPHICS_VER(rq->engine->i915) >= 8)
+ if (GRAPHICS_VER(rq->i915) >= 8)
cmd++;
*cs++ = cmd;
diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index 39c3ec12df1abb..fa36cf920bdee9 100644
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -459,12 +459,12 @@ static int emit_ggtt_store_dw(struct i915_request *rq, u32 addr, u32 value)
if (IS_ERR(cs))
return PTR_ERR(cs);
- if (GRAPHICS_VER(rq->engine->i915) >= 8) {
+ if (GRAPHICS_VER(rq->i915) >= 8) {
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*cs++ = addr;
*cs++ = 0;
*cs++ = value;
- } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
+ } else if (GRAPHICS_VER(rq->i915) >= 4) {
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*cs++ = 0;
*cs++ = addr;
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index f4055804aad1fe..a5c8005ec484c3 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -974,7 +974,7 @@ static void update_guest_context(struct intel_vgpu_workload *workload)
context_page_num = rq->engine->context_size;
context_page_num = context_page_num >> PAGE_SHIFT;
- if (IS_BROADWELL(rq->engine->i915) && rq->engine->id == RCS0)
+ if (IS_BROADWELL(rq->i915) && rq->engine->id == RCS0)
context_page_num = 19;
context_base = (void *) ctx->lrc_reg_state -
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 49c6f1ff11284f..04bc1f4a111504 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1319,7 +1319,7 @@ __store_reg_to_mem(struct i915_request *rq, i915_reg_t reg, u32 ggtt_offset)
u32 *cs, cmd;
cmd = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
- if (GRAPHICS_VER(rq->engine->i915) >= 8)
+ if (GRAPHICS_VER(rq->i915) >= 8)
cmd++;
cs = intel_ring_begin(rq, 4);
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index c5fe199b046d01..9d83f064456cd9 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1341,7 +1341,7 @@ __i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
{
mark_external(rq);
return i915_sw_fence_await_dma_fence(&rq->submit, fence,
- i915_fence_context_timeout(rq->engine->i915,
+ i915_fence_context_timeout(rq->i915,
fence->context),
I915_FENCE_GFP);
}
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index f6f9228a135185..ce1cbee1b39dd0 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -277,7 +277,7 @@ TRACE_EVENT(i915_request_queue,
),
TP_fast_assign(
- __entry->dev = rq->engine->i915->drm.primary->index;
+ __entry->dev = rq->i915->drm.primary->index;
__entry->class = rq->engine->uabi_class;
__entry->instance = rq->engine->uabi_instance;
__entry->ctx = rq->fence.context;
@@ -304,7 +304,7 @@ DECLARE_EVENT_CLASS(i915_request,
),
TP_fast_assign(
- __entry->dev = rq->engine->i915->drm.primary->index;
+ __entry->dev = rq->i915->drm.primary->index;
__entry->class = rq->engine->uabi_class;
__entry->instance = rq->engine->uabi_instance;
__entry->ctx = rq->fence.context;
@@ -353,7 +353,7 @@ TRACE_EVENT(i915_request_in,
),
TP_fast_assign(
- __entry->dev = rq->engine->i915->drm.primary->index;
+ __entry->dev = rq->i915->drm.primary->index;
__entry->class = rq->engine->uabi_class;
__entry->instance = rq->engine->uabi_instance;
__entry->ctx = rq->fence.context;
@@ -382,7 +382,7 @@ TRACE_EVENT(i915_request_out,
),
TP_fast_assign(
- __entry->dev = rq->engine->i915->drm.primary->index;
+ __entry->dev = rq->i915->drm.primary->index;
__entry->class = rq->engine->uabi_class;
__entry->instance = rq->engine->uabi_instance;
__entry->ctx = rq->fence.context;
@@ -623,7 +623,7 @@ TRACE_EVENT(i915_request_wait_begin,
* less desirable.
*/
TP_fast_assign(
- __entry->dev = rq->engine->i915->drm.primary->index;
+ __entry->dev = rq->i915->drm.primary->index;
__entry->class = rq->engine->uabi_class;
__entry->instance = rq->engine->uabi_instance;
__entry->ctx = rq->fence.context;
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c b/drivers/gpu/drm/i915/selftests/i915_perf.c
index d4608b220123ce..403134a7acec30 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf.c
+++ b/drivers/gpu/drm/i915/selftests/i915_perf.c
@@ -168,7 +168,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
return PTR_ERR(cs);
len = 5;
- if (GRAPHICS_VER(rq->engine->i915) >= 8)
+ if (GRAPHICS_VER(rq->i915) >= 8)
len++;
*cs++ = GFX_OP_PIPE_CONTROL(len);
diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c
index 618d9386d55494..3c5e0952f1b81b 100644
--- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
+++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
@@ -159,15 +159,15 @@ igt_spinner_create_request(struct igt_spinner *spin,
batch = spin->batch;
- if (GRAPHICS_VER(rq->engine->i915) >= 8) {
+ if (GRAPHICS_VER(rq->i915) >= 8) {
*batch++ = MI_STORE_DWORD_IMM_GEN4;
*batch++ = lower_32_bits(hws_address(hws, rq));
*batch++ = upper_32_bits(hws_address(hws, rq));
- } else if (GRAPHICS_VER(rq->engine->i915) >= 6) {
+ } else if (GRAPHICS_VER(rq->i915) >= 6) {
*batch++ = MI_STORE_DWORD_IMM_GEN4;
*batch++ = 0;
*batch++ = hws_address(hws, rq);
- } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
+ } else if (GRAPHICS_VER(rq->i915) >= 4) {
*batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*batch++ = 0;
*batch++ = hws_address(hws, rq);
@@ -179,11 +179,11 @@ igt_spinner_create_request(struct igt_spinner *spin,
*batch++ = arbitration_command;
- if (GRAPHICS_VER(rq->engine->i915) >= 8)
+ if (GRAPHICS_VER(rq->i915) >= 8)
*batch++ = MI_BATCH_BUFFER_START | BIT(8) | 1;
- else if (IS_HASWELL(rq->engine->i915))
+ else if (IS_HASWELL(rq->i915))
*batch++ = MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW;
- else if (GRAPHICS_VER(rq->engine->i915) >= 6)
+ else if (GRAPHICS_VER(rq->i915) >= 6)
*batch++ = MI_BATCH_BUFFER_START;
else
*batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
@@ -201,7 +201,7 @@ igt_spinner_create_request(struct igt_spinner *spin,
}
flags = 0;
- if (GRAPHICS_VER(rq->engine->i915) <= 5)
+ if (GRAPHICS_VER(rq->i915) <= 5)
flags |= I915_DISPATCH_SECURE;
err = engine->emit_bb_start(rq, i915_vma_offset(vma), PAGE_SIZE, flags);
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: use direct alias for i915 in requests
2023-07-19 15:07 [Intel-gfx] [PATCH] drm/i915: use direct alias for i915 in requests Andrzej Hajda
@ 2023-07-19 19:10 ` Patchwork
2023-07-19 19:10 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (10 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-07-19 19:10 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: use direct alias for i915 in requests
URL : https://patchwork.freedesktop.org/series/120991/
State : warning
== Summary ==
Error: dim checkpatch failed
98626971c431 drm/i915: use direct alias for i915 in requests
-:122: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants
#122: FILE: drivers/gpu/drm/i915/gt/intel_execlists_submission.c:2721:
+ GEM_BUG_ON(intel_vgpu_active(rq->i915));
-:144: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants
#144: FILE: drivers/gpu/drm/i915/gt/intel_migrate.c:378:
+ GEM_BUG_ON(GRAPHICS_VER(rq->i915) < 8);
total: 0 errors, 2 warnings, 0 checks, 303 lines checked
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: use direct alias for i915 in requests
2023-07-19 15:07 [Intel-gfx] [PATCH] drm/i915: use direct alias for i915 in requests Andrzej Hajda
2023-07-19 19:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2023-07-19 19:10 ` Patchwork
2023-07-19 19:29 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (9 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-07-19 19:10 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: use direct alias for i915 in requests
URL : https://patchwork.freedesktop.org/series/120991/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: use direct alias for i915 in requests
2023-07-19 15:07 [Intel-gfx] [PATCH] drm/i915: use direct alias for i915 in requests Andrzej Hajda
2023-07-19 19:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2023-07-19 19:10 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-07-19 19:29 ` Patchwork
2023-07-20 9:46 ` [Intel-gfx] [PATCH] " Tvrtko Ursulin
` (8 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-07-19 19:29 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 12015 bytes --]
== Series Details ==
Series: drm/i915: use direct alias for i915 in requests
URL : https://patchwork.freedesktop.org/series/120991/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13396 -> Patchwork_120991v1
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_120991v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_120991v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/index.html
Participating hosts (42 -> 43)
------------------------------
Additional (2): fi-kbl-soraka bat-rpls-2
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_120991v1:
### IGT changes ###
#### Possible regressions ####
* igt@i915_module_load@load:
- bat-rpls-1: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/bat-rpls-1/igt@i915_module_load@load.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/bat-rpls-1/igt@i915_module_load@load.html
- bat-adlp-6: [PASS][3] -> [ABORT][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/bat-adlp-6/igt@i915_module_load@load.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/bat-adlp-6/igt@i915_module_load@load.html
- bat-adls-5: [PASS][5] -> [ABORT][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/bat-adls-5/igt@i915_module_load@load.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/bat-adls-5/igt@i915_module_load@load.html
- bat-dg1-5: [PASS][7] -> [ABORT][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/bat-dg1-5/igt@i915_module_load@load.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/bat-dg1-5/igt@i915_module_load@load.html
- bat-dg1-7: [PASS][9] -> [ABORT][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/bat-dg1-7/igt@i915_module_load@load.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/bat-dg1-7/igt@i915_module_load@load.html
- bat-adlp-9: [PASS][11] -> [ABORT][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/bat-adlp-9/igt@i915_module_load@load.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/bat-adlp-9/igt@i915_module_load@load.html
- bat-dg2-11: [PASS][13] -> [ABORT][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/bat-dg2-11/igt@i915_module_load@load.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/bat-dg2-11/igt@i915_module_load@load.html
- bat-adln-1: [PASS][15] -> [ABORT][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/bat-adln-1/igt@i915_module_load@load.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/bat-adln-1/igt@i915_module_load@load.html
- bat-adlm-1: [PASS][17] -> [ABORT][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/bat-adlm-1/igt@i915_module_load@load.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/bat-adlm-1/igt@i915_module_load@load.html
- fi-tgl-1115g4: [PASS][19] -> [ABORT][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/fi-tgl-1115g4/igt@i915_module_load@load.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/fi-tgl-1115g4/igt@i915_module_load@load.html
- bat-atsm-1: [PASS][21] -> [ABORT][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/bat-atsm-1/igt@i915_module_load@load.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/bat-atsm-1/igt@i915_module_load@load.html
- bat-dg2-9: [PASS][23] -> [ABORT][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/bat-dg2-9/igt@i915_module_load@load.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/bat-dg2-9/igt@i915_module_load@load.html
- bat-rpls-2: NOTRUN -> [ABORT][25]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/bat-rpls-2/igt@i915_module_load@load.html
- bat-dg2-8: [PASS][26] -> [ABORT][27]
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/bat-dg2-8/igt@i915_module_load@load.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/bat-dg2-8/igt@i915_module_load@load.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_module_load@load:
- {bat-dg2-13}: [DMESG-WARN][28] ([Intel XE#486] / [i915#8879]) -> [ABORT][29]
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/bat-dg2-13/igt@i915_module_load@load.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/bat-dg2-13/igt@i915_module_load@load.html
- {bat-dg2-14}: [DMESG-WARN][30] ([Intel XE#486] / [i915#8879]) -> [ABORT][31]
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/bat-dg2-14/igt@i915_module_load@load.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/bat-dg2-14/igt@i915_module_load@load.html
Known issues
------------
Here are the changes found in Patchwork_120991v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#2190])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][33] ([fdo#109271] / [i915#4613]) +3 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@i915_module_load@load:
- fi-rkl-11600: [PASS][34] -> [ABORT][35] ([i915#8695])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/fi-rkl-11600/igt@i915_module_load@load.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/fi-rkl-11600/igt@i915_module_load@load.html
- fi-kbl-soraka: NOTRUN -> [DMESG-WARN][36] ([i915#1982])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/fi-kbl-soraka/igt@i915_module_load@load.html
- bat-rplp-1: [PASS][37] -> [ABORT][38] ([i915#8695])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/bat-rplp-1/igt@i915_module_load@load.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/bat-rplp-1/igt@i915_module_load@load.html
- bat-mtlp-6: [PASS][39] -> [ABORT][40] ([i915#8141])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/bat-mtlp-6/igt@i915_module_load@load.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/bat-mtlp-6/igt@i915_module_load@load.html
- bat-mtlp-8: [PASS][41] -> [ABORT][42] ([i915#8141])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/bat-mtlp-8/igt@i915_module_load@load.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/bat-mtlp-8/igt@i915_module_load@load.html
* igt@i915_pm_rpm@basic-rte:
- fi-cfl-guc: [PASS][43] -> [FAIL][44] ([i915#7940])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/fi-cfl-guc/igt@i915_pm_rpm@basic-rte.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/fi-cfl-guc/igt@i915_pm_rpm@basic-rte.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][45] ([i915#5334] / [i915#7872])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][46] ([i915#1886] / [i915#7913])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@kms_chamelium_frames@hdmi-crc-fast:
- fi-kbl-soraka: NOTRUN -> [SKIP][47] ([fdo#109271]) +15 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/fi-kbl-soraka/igt@kms_chamelium_frames@hdmi-crc-fast.html
#### Possible fixes ####
* igt@i915_pm_rpm@basic-rte:
- fi-cfl-8700k: [FAIL][48] ([i915#7940]) -> [PASS][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/fi-cfl-8700k/igt@i915_pm_rpm@basic-rte.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/fi-cfl-8700k/igt@i915_pm_rpm@basic-rte.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-glk-j4005: [DMESG-FAIL][50] ([i915#5334]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/fi-glk-j4005/igt@i915_selftest@live@gt_heartbeat.html
#### Warnings ####
* igt@i915_module_load@load:
- bat-adlp-11: [DMESG-WARN][52] ([i915#4423]) -> [ABORT][53] ([i915#4423])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/bat-adlp-11/igt@i915_module_load@load.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/bat-adlp-11/igt@i915_module_load@load.html
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-kbl-guc: [SKIP][54] ([fdo#109271]) -> [FAIL][55] ([i915#7940])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/fi-kbl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
- fi-cfl-guc: [FAIL][56] ([i915#7691]) -> [FAIL][57] ([i915#7940])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13396/fi-cfl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/fi-cfl-guc/igt@i915_pm_rpm@basic-pci-d3-state.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[Intel XE#486]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/486
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#7691]: https://gitlab.freedesktop.org/drm/intel/issues/7691
[i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
[i915#8141]: https://gitlab.freedesktop.org/drm/intel/issues/8141
[i915#8695]: https://gitlab.freedesktop.org/drm/intel/issues/8695
[i915#8879]: https://gitlab.freedesktop.org/drm/intel/issues/8879
Build changes
-------------
* Linux: CI_DRM_13396 -> Patchwork_120991v1
CI-20190529: 20190529
CI_DRM_13396: da1bb773ff84001b185e7bec54b32b89dff44f91 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7394: 3b0c82d7e9f1b8708d351243de7f227153793ede @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_120991v1: da1bb773ff84001b185e7bec54b32b89dff44f91 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
a8306d5e6ec8 drm/i915: use direct alias for i915 in requests
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v1/index.html
[-- Attachment #2: Type: text/html, Size: 14055 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: use direct alias for i915 in requests
2023-07-19 15:07 [Intel-gfx] [PATCH] drm/i915: use direct alias for i915 in requests Andrzej Hajda
` (2 preceding siblings ...)
2023-07-19 19:29 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2023-07-20 9:46 ` Tvrtko Ursulin
2023-07-20 10:07 ` Tvrtko Ursulin
2023-07-20 9:51 ` [Intel-gfx] [PATCH] " Nirmoy Das
` (7 subsequent siblings)
11 siblings, 1 reply; 17+ messages in thread
From: Tvrtko Ursulin @ 2023-07-20 9:46 UTC (permalink / raw)
To: Andrzej Hajda, intel-gfx; +Cc: Chris Wilson, Nirmoy Das
On 19/07/2023 16:07, Andrzej Hajda wrote:
> i915_request contains direct alias to i915, there is no point to go via
> rq->engine->i915.
>
> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++--
> drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 +++++++++---------
> .../drm/i915/gt/intel_execlists_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_migrate.c | 10 +++++-----
> .../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
> drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_rc6.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_timeline.c | 4 ++--
> drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
> drivers/gpu/drm/i915/i915_perf.c | 2 +-
> drivers/gpu/drm/i915/i915_request.c | 2 +-
> drivers/gpu/drm/i915/i915_trace.h | 10 +++++-----
> drivers/gpu/drm/i915/selftests/i915_perf.c | 2 +-
> drivers/gpu/drm/i915/selftests/igt_spinner.c | 14 +++++++-------
> 17 files changed, 42 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index d3208a32561442..5a687a3686bd53 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -2229,8 +2229,8 @@ static int i915_reset_gen7_sol_offsets(struct i915_request *rq)
> u32 *cs;
> int i;
>
> - if (GRAPHICS_VER(rq->engine->i915) != 7 || rq->engine->id != RCS0) {
> - drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs only\n");
> + if (GRAPHICS_VER(rq->i915) != 7 || rq->engine->id != RCS0) {
> + drm_dbg(&rq->i915->drm, "sol reset is gen7/rcs only\n");
> return -EINVAL;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> index 1c82caf525c346..8fe0499308ffe5 100644
> --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> @@ -76,7 +76,7 @@ int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode)
> cmd = MI_FLUSH;
> if (mode & EMIT_INVALIDATE) {
> cmd |= MI_EXE_FLUSH;
> - if (IS_G4X(rq->engine->i915) || GRAPHICS_VER(rq->engine->i915) == 5)
> + if (IS_G4X(rq->i915) || GRAPHICS_VER(rq->i915) == 5)
> cmd |= MI_INVALIDATE_ISP;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 23857cc08eca1f..3ba20ea030e8d1 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -39,11 +39,11 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
> * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
> * pipe control.
> */
> - if (GRAPHICS_VER(rq->engine->i915) == 9)
> + if (GRAPHICS_VER(rq->i915) == 9)
> vf_flush_wa = true;
>
> /* WaForGAMHang:kbl */
> - if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
> + if (IS_KBL_GRAPHICS_STEP(rq->i915, 0, STEP_C0))
> dc_flush_wa = true;
> }
>
> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
> static int mtl_dummy_pipe_control(struct i915_request *rq)
> {
> /* Wa_14016712196 */
> - if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
> - IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
> + if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {
> u32 *cs;
>
> /* dummy PIPE_CONTROL + depth flush */
> @@ -267,7 +267,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> else if (engine->class == COMPUTE_CLASS)
> flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
>
> - if (!HAS_FLAT_CCS(rq->engine->i915))
> + if (!HAS_FLAT_CCS(rq->i915))
> count = 8 + 4;
> else
> count = 8;
> @@ -285,7 +285,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
>
> cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
>
> - if (!HAS_FLAT_CCS(rq->engine->i915)) {
> + if (!HAS_FLAT_CCS(rq->i915)) {
> /* hsdes: 1809175790 */
> cs = gen12_emit_aux_table_inv(rq->engine->gt,
> cs, GEN12_GFX_CCS_AUX_NV);
> @@ -307,7 +307,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
> if (mode & EMIT_INVALIDATE) {
> cmd += 2;
>
> - if (!HAS_FLAT_CCS(rq->engine->i915) &&
> + if (!HAS_FLAT_CCS(rq->i915) &&
> (rq->engine->class == VIDEO_DECODE_CLASS ||
> rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) {
> aux_inv = rq->engine->mask &
> @@ -754,7 +754,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
>
> u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> {
> - struct drm_i915_private *i915 = rq->engine->i915;
> + struct drm_i915_private *i915 = rq->i915;
> u32 flags = (PIPE_CONTROL_CS_STALL |
> PIPE_CONTROL_TLB_INVALIDATE |
> PIPE_CONTROL_TILE_CACHE_FLUSH |
> @@ -775,7 +775,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> /* Wa_1409600907 */
> flags |= PIPE_CONTROL_DEPTH_STALL;
>
> - if (!HAS_3D_PIPELINE(rq->engine->i915))
> + if (!HAS_3D_PIPELINE(rq->i915))
> flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
> else if (rq->engine->class == COMPUTE_CLASS)
> flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index d85b5a6d981f99..8a641bcf777cb4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2718,7 +2718,7 @@ static int emit_pdps(struct i915_request *rq)
> int err, i;
> u32 *cs;
>
> - GEM_BUG_ON(intel_vgpu_active(rq->engine->i915));
> + GEM_BUG_ON(intel_vgpu_active(rq->i915));
>
> /*
> * Beware ye of the dragons, this sequence is magic!
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index 6023288b0e2dd5..576e5ef0289ba5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -366,7 +366,7 @@ static int emit_pte(struct i915_request *rq,
> u64 offset,
> int length)
> {
> - bool has_64K_pages = HAS_64K_PAGES(rq->engine->i915);
> + bool has_64K_pages = HAS_64K_PAGES(rq->i915);
> const u64 encode = rq->context->vm->pte_encode(0, pat_index,
> is_lmem ? PTE_LM : 0);
> struct intel_ring *ring = rq->ring;
> @@ -375,7 +375,7 @@ static int emit_pte(struct i915_request *rq,
> u32 page_size;
> u32 *hdr, *cs;
>
> - GEM_BUG_ON(GRAPHICS_VER(rq->engine->i915) < 8);
> + GEM_BUG_ON(GRAPHICS_VER(rq->i915) < 8);
>
> page_size = I915_GTT_PAGE_SIZE;
> dword_length = 0x400;
> @@ -531,7 +531,7 @@ static int emit_copy_ccs(struct i915_request *rq,
> u32 dst_offset, u8 dst_access,
> u32 src_offset, u8 src_access, int size)
> {
> - struct drm_i915_private *i915 = rq->engine->i915;
> + struct drm_i915_private *i915 = rq->i915;
> int mocs = rq->engine->gt->mocs.uc_index << 1;
> u32 num_ccs_blks;
> u32 *cs;
> @@ -581,7 +581,7 @@ static int emit_copy_ccs(struct i915_request *rq,
> static int emit_copy(struct i915_request *rq,
> u32 dst_offset, u32 src_offset, int size)
> {
> - const int ver = GRAPHICS_VER(rq->engine->i915);
> + const int ver = GRAPHICS_VER(rq->i915);
> u32 instance = rq->engine->instance;
> u32 *cs;
>
> @@ -917,7 +917,7 @@ intel_context_migrate_copy(struct intel_context *ce,
> static int emit_clear(struct i915_request *rq, u32 offset, int size,
> u32 value, bool is_lmem)
> {
> - struct drm_i915_private *i915 = rq->engine->i915;
> + struct drm_i915_private *i915 = rq->i915;
> int mocs = rq->engine->gt->mocs.uc_index << 1;
> const int ver = GRAPHICS_VER(i915);
> int ring_sz;
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 3fd795c3263fd2..92085ffd23de0e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -805,7 +805,7 @@ static int mi_set_context(struct i915_request *rq,
> static int remap_l3_slice(struct i915_request *rq, int slice)
> {
> #define L3LOG_DW (GEN7_L3LOG_SIZE / sizeof(u32))
> - u32 *cs, *remap_info = rq->engine->i915->l3_parity.remap_info[slice];
> + u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
> int i;
>
> if (!remap_info)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index b177c588698b08..589d009032fcd3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -3249,7 +3249,7 @@ wa_list_srm(struct i915_request *rq,
> const struct i915_wa_list *wal,
> struct i915_vma *vma)
> {
> - struct drm_i915_private *i915 = rq->engine->i915;
> + struct drm_i915_private *i915 = rq->i915;
> unsigned int i, count = 0;
> const struct i915_wa *wa;
> u32 srm, *cs;
> @@ -3348,7 +3348,7 @@ static int engine_wa_list_verify(struct intel_context *ce,
>
> err = 0;
> for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
> - if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg)))
> + if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))
> continue;
>
> if (!wa_verify(wal->gt, wa, results[i], wal->name, from))
> diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> index 78cdfc6f315f2a..86cecf7a110540 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> @@ -62,7 +62,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
> return PTR_ERR(cs);
>
> cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
> + if (GRAPHICS_VER(rq->i915) >= 8)
> cmd++;
> *cs++ = cmd;
> *cs++ = i915_mmio_reg_offset(timestamp_reg(rq->engine));
> diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> index a8446ab825012f..d73e438fb85fab 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> @@ -137,7 +137,7 @@ static int read_mocs_table(struct i915_request *rq,
> if (!table)
> return 0;
>
> - if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915))
> + if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915))
> addr = global_mocs_offset() + gt->uncore->gsi_offset;
> else
> addr = mocs_offset(rq->engine);
> diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> index 2ceeadecc639cc..a7189c2d660cc5 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> @@ -140,7 +140,7 @@ static const u32 *__live_rc6_ctx(struct intel_context *ce)
> }
>
> cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
> + if (GRAPHICS_VER(rq->i915) >= 8)
> cmd++;
>
> *cs++ = cmd;
> diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> index 39c3ec12df1abb..fa36cf920bdee9 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> @@ -459,12 +459,12 @@ static int emit_ggtt_store_dw(struct i915_request *rq, u32 addr, u32 value)
> if (IS_ERR(cs))
> return PTR_ERR(cs);
>
> - if (GRAPHICS_VER(rq->engine->i915) >= 8) {
> + if (GRAPHICS_VER(rq->i915) >= 8) {
> *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> *cs++ = addr;
> *cs++ = 0;
> *cs++ = value;
> - } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
> + } else if (GRAPHICS_VER(rq->i915) >= 4) {
> *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> *cs++ = 0;
> *cs++ = addr;
> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
> index f4055804aad1fe..a5c8005ec484c3 100644
> --- a/drivers/gpu/drm/i915/gvt/scheduler.c
> +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
> @@ -974,7 +974,7 @@ static void update_guest_context(struct intel_vgpu_workload *workload)
> context_page_num = rq->engine->context_size;
> context_page_num = context_page_num >> PAGE_SHIFT;
>
> - if (IS_BROADWELL(rq->engine->i915) && rq->engine->id == RCS0)
> + if (IS_BROADWELL(rq->i915) && rq->engine->id == RCS0)
> context_page_num = 19;
>
> context_base = (void *) ctx->lrc_reg_state -
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 49c6f1ff11284f..04bc1f4a111504 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1319,7 +1319,7 @@ __store_reg_to_mem(struct i915_request *rq, i915_reg_t reg, u32 ggtt_offset)
> u32 *cs, cmd;
>
> cmd = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
> + if (GRAPHICS_VER(rq->i915) >= 8)
> cmd++;
>
> cs = intel_ring_begin(rq, 4);
> diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
> index c5fe199b046d01..9d83f064456cd9 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -1341,7 +1341,7 @@ __i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
> {
> mark_external(rq);
> return i915_sw_fence_await_dma_fence(&rq->submit, fence,
> - i915_fence_context_timeout(rq->engine->i915,
> + i915_fence_context_timeout(rq->i915,
> fence->context),
> I915_FENCE_GFP);
> }
> diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
> index f6f9228a135185..ce1cbee1b39dd0 100644
> --- a/drivers/gpu/drm/i915/i915_trace.h
> +++ b/drivers/gpu/drm/i915/i915_trace.h
> @@ -277,7 +277,7 @@ TRACE_EVENT(i915_request_queue,
> ),
>
> TP_fast_assign(
> - __entry->dev = rq->engine->i915->drm.primary->index;
> + __entry->dev = rq->i915->drm.primary->index;
> __entry->class = rq->engine->uabi_class;
> __entry->instance = rq->engine->uabi_instance;
> __entry->ctx = rq->fence.context;
> @@ -304,7 +304,7 @@ DECLARE_EVENT_CLASS(i915_request,
> ),
>
> TP_fast_assign(
> - __entry->dev = rq->engine->i915->drm.primary->index;
> + __entry->dev = rq->i915->drm.primary->index;
> __entry->class = rq->engine->uabi_class;
> __entry->instance = rq->engine->uabi_instance;
> __entry->ctx = rq->fence.context;
> @@ -353,7 +353,7 @@ TRACE_EVENT(i915_request_in,
> ),
>
> TP_fast_assign(
> - __entry->dev = rq->engine->i915->drm.primary->index;
> + __entry->dev = rq->i915->drm.primary->index;
> __entry->class = rq->engine->uabi_class;
> __entry->instance = rq->engine->uabi_instance;
> __entry->ctx = rq->fence.context;
> @@ -382,7 +382,7 @@ TRACE_EVENT(i915_request_out,
> ),
>
> TP_fast_assign(
> - __entry->dev = rq->engine->i915->drm.primary->index;
> + __entry->dev = rq->i915->drm.primary->index;
> __entry->class = rq->engine->uabi_class;
> __entry->instance = rq->engine->uabi_instance;
> __entry->ctx = rq->fence.context;
> @@ -623,7 +623,7 @@ TRACE_EVENT(i915_request_wait_begin,
> * less desirable.
> */
> TP_fast_assign(
> - __entry->dev = rq->engine->i915->drm.primary->index;
> + __entry->dev = rq->i915->drm.primary->index;
> __entry->class = rq->engine->uabi_class;
> __entry->instance = rq->engine->uabi_instance;
> __entry->ctx = rq->fence.context;
> diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c b/drivers/gpu/drm/i915/selftests/i915_perf.c
> index d4608b220123ce..403134a7acec30 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_perf.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_perf.c
> @@ -168,7 +168,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
> return PTR_ERR(cs);
>
> len = 5;
> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
> + if (GRAPHICS_VER(rq->i915) >= 8)
> len++;
>
> *cs++ = GFX_OP_PIPE_CONTROL(len);
> diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c
> index 618d9386d55494..3c5e0952f1b81b 100644
> --- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
> +++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
> @@ -159,15 +159,15 @@ igt_spinner_create_request(struct igt_spinner *spin,
>
> batch = spin->batch;
>
> - if (GRAPHICS_VER(rq->engine->i915) >= 8) {
> + if (GRAPHICS_VER(rq->i915) >= 8) {
> *batch++ = MI_STORE_DWORD_IMM_GEN4;
> *batch++ = lower_32_bits(hws_address(hws, rq));
> *batch++ = upper_32_bits(hws_address(hws, rq));
> - } else if (GRAPHICS_VER(rq->engine->i915) >= 6) {
> + } else if (GRAPHICS_VER(rq->i915) >= 6) {
> *batch++ = MI_STORE_DWORD_IMM_GEN4;
> *batch++ = 0;
> *batch++ = hws_address(hws, rq);
> - } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
> + } else if (GRAPHICS_VER(rq->i915) >= 4) {
> *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> *batch++ = 0;
> *batch++ = hws_address(hws, rq);
> @@ -179,11 +179,11 @@ igt_spinner_create_request(struct igt_spinner *spin,
>
> *batch++ = arbitration_command;
>
> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
> + if (GRAPHICS_VER(rq->i915) >= 8)
> *batch++ = MI_BATCH_BUFFER_START | BIT(8) | 1;
> - else if (IS_HASWELL(rq->engine->i915))
> + else if (IS_HASWELL(rq->i915))
> *batch++ = MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW;
> - else if (GRAPHICS_VER(rq->engine->i915) >= 6)
> + else if (GRAPHICS_VER(rq->i915) >= 6)
> *batch++ = MI_BATCH_BUFFER_START;
> else
> *batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
> @@ -201,7 +201,7 @@ igt_spinner_create_request(struct igt_spinner *spin,
> }
>
> flags = 0;
> - if (GRAPHICS_VER(rq->engine->i915) <= 5)
> + if (GRAPHICS_VER(rq->i915) <= 5)
> flags |= I915_DISPATCH_SECURE;
> err = engine->emit_bb_start(rq, i915_vma_offset(vma), PAGE_SIZE, flags);
>
Nice cleanup, thank you!
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Apparently was possible ever since 7307e91bfcd0 ("drm/i915: Do not
access rq->engine without a reference") which is funnily related to the
other story we are discussing last few days.
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: use direct alias for i915 in requests
2023-07-19 15:07 [Intel-gfx] [PATCH] drm/i915: use direct alias for i915 in requests Andrzej Hajda
` (3 preceding siblings ...)
2023-07-20 9:46 ` [Intel-gfx] [PATCH] " Tvrtko Ursulin
@ 2023-07-20 9:51 ` Nirmoy Das
2023-07-20 16:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: use direct alias for i915 in requests (rev2) Patchwork
` (6 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Nirmoy Das @ 2023-07-20 9:51 UTC (permalink / raw)
To: Andrzej Hajda, intel-gfx; +Cc: Chris Wilson, Nirmoy Das
On 7/19/2023 5:07 PM, Andrzej Hajda wrote:
> i915_request contains direct alias to i915, there is no point to go via
> rq->engine->i915.
>
> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Acked-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++--
> drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 +++++++++---------
> .../drm/i915/gt/intel_execlists_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_migrate.c | 10 +++++-----
> .../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
> drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_rc6.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_timeline.c | 4 ++--
> drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
> drivers/gpu/drm/i915/i915_perf.c | 2 +-
> drivers/gpu/drm/i915/i915_request.c | 2 +-
> drivers/gpu/drm/i915/i915_trace.h | 10 +++++-----
> drivers/gpu/drm/i915/selftests/i915_perf.c | 2 +-
> drivers/gpu/drm/i915/selftests/igt_spinner.c | 14 +++++++-------
> 17 files changed, 42 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index d3208a32561442..5a687a3686bd53 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -2229,8 +2229,8 @@ static int i915_reset_gen7_sol_offsets(struct i915_request *rq)
> u32 *cs;
> int i;
>
> - if (GRAPHICS_VER(rq->engine->i915) != 7 || rq->engine->id != RCS0) {
> - drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs only\n");
> + if (GRAPHICS_VER(rq->i915) != 7 || rq->engine->id != RCS0) {
> + drm_dbg(&rq->i915->drm, "sol reset is gen7/rcs only\n");
> return -EINVAL;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> index 1c82caf525c346..8fe0499308ffe5 100644
> --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> @@ -76,7 +76,7 @@ int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode)
> cmd = MI_FLUSH;
> if (mode & EMIT_INVALIDATE) {
> cmd |= MI_EXE_FLUSH;
> - if (IS_G4X(rq->engine->i915) || GRAPHICS_VER(rq->engine->i915) == 5)
> + if (IS_G4X(rq->i915) || GRAPHICS_VER(rq->i915) == 5)
> cmd |= MI_INVALIDATE_ISP;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 23857cc08eca1f..3ba20ea030e8d1 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -39,11 +39,11 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
> * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
> * pipe control.
> */
> - if (GRAPHICS_VER(rq->engine->i915) == 9)
> + if (GRAPHICS_VER(rq->i915) == 9)
> vf_flush_wa = true;
>
> /* WaForGAMHang:kbl */
> - if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
> + if (IS_KBL_GRAPHICS_STEP(rq->i915, 0, STEP_C0))
> dc_flush_wa = true;
> }
>
> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
> static int mtl_dummy_pipe_control(struct i915_request *rq)
> {
> /* Wa_14016712196 */
> - if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
> - IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
> + if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {
> u32 *cs;
>
> /* dummy PIPE_CONTROL + depth flush */
> @@ -267,7 +267,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> else if (engine->class == COMPUTE_CLASS)
> flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
>
> - if (!HAS_FLAT_CCS(rq->engine->i915))
> + if (!HAS_FLAT_CCS(rq->i915))
> count = 8 + 4;
> else
> count = 8;
> @@ -285,7 +285,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
>
> cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
>
> - if (!HAS_FLAT_CCS(rq->engine->i915)) {
> + if (!HAS_FLAT_CCS(rq->i915)) {
> /* hsdes: 1809175790 */
> cs = gen12_emit_aux_table_inv(rq->engine->gt,
> cs, GEN12_GFX_CCS_AUX_NV);
> @@ -307,7 +307,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
> if (mode & EMIT_INVALIDATE) {
> cmd += 2;
>
> - if (!HAS_FLAT_CCS(rq->engine->i915) &&
> + if (!HAS_FLAT_CCS(rq->i915) &&
> (rq->engine->class == VIDEO_DECODE_CLASS ||
> rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) {
> aux_inv = rq->engine->mask &
> @@ -754,7 +754,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
>
> u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> {
> - struct drm_i915_private *i915 = rq->engine->i915;
> + struct drm_i915_private *i915 = rq->i915;
> u32 flags = (PIPE_CONTROL_CS_STALL |
> PIPE_CONTROL_TLB_INVALIDATE |
> PIPE_CONTROL_TILE_CACHE_FLUSH |
> @@ -775,7 +775,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> /* Wa_1409600907 */
> flags |= PIPE_CONTROL_DEPTH_STALL;
>
> - if (!HAS_3D_PIPELINE(rq->engine->i915))
> + if (!HAS_3D_PIPELINE(rq->i915))
> flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
> else if (rq->engine->class == COMPUTE_CLASS)
> flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index d85b5a6d981f99..8a641bcf777cb4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2718,7 +2718,7 @@ static int emit_pdps(struct i915_request *rq)
> int err, i;
> u32 *cs;
>
> - GEM_BUG_ON(intel_vgpu_active(rq->engine->i915));
> + GEM_BUG_ON(intel_vgpu_active(rq->i915));
>
> /*
> * Beware ye of the dragons, this sequence is magic!
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index 6023288b0e2dd5..576e5ef0289ba5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -366,7 +366,7 @@ static int emit_pte(struct i915_request *rq,
> u64 offset,
> int length)
> {
> - bool has_64K_pages = HAS_64K_PAGES(rq->engine->i915);
> + bool has_64K_pages = HAS_64K_PAGES(rq->i915);
> const u64 encode = rq->context->vm->pte_encode(0, pat_index,
> is_lmem ? PTE_LM : 0);
> struct intel_ring *ring = rq->ring;
> @@ -375,7 +375,7 @@ static int emit_pte(struct i915_request *rq,
> u32 page_size;
> u32 *hdr, *cs;
>
> - GEM_BUG_ON(GRAPHICS_VER(rq->engine->i915) < 8);
> + GEM_BUG_ON(GRAPHICS_VER(rq->i915) < 8);
>
> page_size = I915_GTT_PAGE_SIZE;
> dword_length = 0x400;
> @@ -531,7 +531,7 @@ static int emit_copy_ccs(struct i915_request *rq,
> u32 dst_offset, u8 dst_access,
> u32 src_offset, u8 src_access, int size)
> {
> - struct drm_i915_private *i915 = rq->engine->i915;
> + struct drm_i915_private *i915 = rq->i915;
> int mocs = rq->engine->gt->mocs.uc_index << 1;
> u32 num_ccs_blks;
> u32 *cs;
> @@ -581,7 +581,7 @@ static int emit_copy_ccs(struct i915_request *rq,
> static int emit_copy(struct i915_request *rq,
> u32 dst_offset, u32 src_offset, int size)
> {
> - const int ver = GRAPHICS_VER(rq->engine->i915);
> + const int ver = GRAPHICS_VER(rq->i915);
> u32 instance = rq->engine->instance;
> u32 *cs;
>
> @@ -917,7 +917,7 @@ intel_context_migrate_copy(struct intel_context *ce,
> static int emit_clear(struct i915_request *rq, u32 offset, int size,
> u32 value, bool is_lmem)
> {
> - struct drm_i915_private *i915 = rq->engine->i915;
> + struct drm_i915_private *i915 = rq->i915;
> int mocs = rq->engine->gt->mocs.uc_index << 1;
> const int ver = GRAPHICS_VER(i915);
> int ring_sz;
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 3fd795c3263fd2..92085ffd23de0e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -805,7 +805,7 @@ static int mi_set_context(struct i915_request *rq,
> static int remap_l3_slice(struct i915_request *rq, int slice)
> {
> #define L3LOG_DW (GEN7_L3LOG_SIZE / sizeof(u32))
> - u32 *cs, *remap_info = rq->engine->i915->l3_parity.remap_info[slice];
> + u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
> int i;
>
> if (!remap_info)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index b177c588698b08..589d009032fcd3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -3249,7 +3249,7 @@ wa_list_srm(struct i915_request *rq,
> const struct i915_wa_list *wal,
> struct i915_vma *vma)
> {
> - struct drm_i915_private *i915 = rq->engine->i915;
> + struct drm_i915_private *i915 = rq->i915;
> unsigned int i, count = 0;
> const struct i915_wa *wa;
> u32 srm, *cs;
> @@ -3348,7 +3348,7 @@ static int engine_wa_list_verify(struct intel_context *ce,
>
> err = 0;
> for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
> - if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg)))
> + if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))
> continue;
>
> if (!wa_verify(wal->gt, wa, results[i], wal->name, from))
> diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> index 78cdfc6f315f2a..86cecf7a110540 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> @@ -62,7 +62,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
> return PTR_ERR(cs);
>
> cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
> + if (GRAPHICS_VER(rq->i915) >= 8)
> cmd++;
> *cs++ = cmd;
> *cs++ = i915_mmio_reg_offset(timestamp_reg(rq->engine));
> diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> index a8446ab825012f..d73e438fb85fab 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> @@ -137,7 +137,7 @@ static int read_mocs_table(struct i915_request *rq,
> if (!table)
> return 0;
>
> - if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915))
> + if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915))
> addr = global_mocs_offset() + gt->uncore->gsi_offset;
> else
> addr = mocs_offset(rq->engine);
> diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> index 2ceeadecc639cc..a7189c2d660cc5 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> @@ -140,7 +140,7 @@ static const u32 *__live_rc6_ctx(struct intel_context *ce)
> }
>
> cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
> + if (GRAPHICS_VER(rq->i915) >= 8)
> cmd++;
>
> *cs++ = cmd;
> diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> index 39c3ec12df1abb..fa36cf920bdee9 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> @@ -459,12 +459,12 @@ static int emit_ggtt_store_dw(struct i915_request *rq, u32 addr, u32 value)
> if (IS_ERR(cs))
> return PTR_ERR(cs);
>
> - if (GRAPHICS_VER(rq->engine->i915) >= 8) {
> + if (GRAPHICS_VER(rq->i915) >= 8) {
> *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> *cs++ = addr;
> *cs++ = 0;
> *cs++ = value;
> - } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
> + } else if (GRAPHICS_VER(rq->i915) >= 4) {
> *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> *cs++ = 0;
> *cs++ = addr;
> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
> index f4055804aad1fe..a5c8005ec484c3 100644
> --- a/drivers/gpu/drm/i915/gvt/scheduler.c
> +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
> @@ -974,7 +974,7 @@ static void update_guest_context(struct intel_vgpu_workload *workload)
> context_page_num = rq->engine->context_size;
> context_page_num = context_page_num >> PAGE_SHIFT;
>
> - if (IS_BROADWELL(rq->engine->i915) && rq->engine->id == RCS0)
> + if (IS_BROADWELL(rq->i915) && rq->engine->id == RCS0)
> context_page_num = 19;
>
> context_base = (void *) ctx->lrc_reg_state -
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 49c6f1ff11284f..04bc1f4a111504 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1319,7 +1319,7 @@ __store_reg_to_mem(struct i915_request *rq, i915_reg_t reg, u32 ggtt_offset)
> u32 *cs, cmd;
>
> cmd = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
> + if (GRAPHICS_VER(rq->i915) >= 8)
> cmd++;
>
> cs = intel_ring_begin(rq, 4);
> diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
> index c5fe199b046d01..9d83f064456cd9 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -1341,7 +1341,7 @@ __i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
> {
> mark_external(rq);
> return i915_sw_fence_await_dma_fence(&rq->submit, fence,
> - i915_fence_context_timeout(rq->engine->i915,
> + i915_fence_context_timeout(rq->i915,
> fence->context),
> I915_FENCE_GFP);
> }
> diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
> index f6f9228a135185..ce1cbee1b39dd0 100644
> --- a/drivers/gpu/drm/i915/i915_trace.h
> +++ b/drivers/gpu/drm/i915/i915_trace.h
> @@ -277,7 +277,7 @@ TRACE_EVENT(i915_request_queue,
> ),
>
> TP_fast_assign(
> - __entry->dev = rq->engine->i915->drm.primary->index;
> + __entry->dev = rq->i915->drm.primary->index;
> __entry->class = rq->engine->uabi_class;
> __entry->instance = rq->engine->uabi_instance;
> __entry->ctx = rq->fence.context;
> @@ -304,7 +304,7 @@ DECLARE_EVENT_CLASS(i915_request,
> ),
>
> TP_fast_assign(
> - __entry->dev = rq->engine->i915->drm.primary->index;
> + __entry->dev = rq->i915->drm.primary->index;
> __entry->class = rq->engine->uabi_class;
> __entry->instance = rq->engine->uabi_instance;
> __entry->ctx = rq->fence.context;
> @@ -353,7 +353,7 @@ TRACE_EVENT(i915_request_in,
> ),
>
> TP_fast_assign(
> - __entry->dev = rq->engine->i915->drm.primary->index;
> + __entry->dev = rq->i915->drm.primary->index;
> __entry->class = rq->engine->uabi_class;
> __entry->instance = rq->engine->uabi_instance;
> __entry->ctx = rq->fence.context;
> @@ -382,7 +382,7 @@ TRACE_EVENT(i915_request_out,
> ),
>
> TP_fast_assign(
> - __entry->dev = rq->engine->i915->drm.primary->index;
> + __entry->dev = rq->i915->drm.primary->index;
> __entry->class = rq->engine->uabi_class;
> __entry->instance = rq->engine->uabi_instance;
> __entry->ctx = rq->fence.context;
> @@ -623,7 +623,7 @@ TRACE_EVENT(i915_request_wait_begin,
> * less desirable.
> */
> TP_fast_assign(
> - __entry->dev = rq->engine->i915->drm.primary->index;
> + __entry->dev = rq->i915->drm.primary->index;
> __entry->class = rq->engine->uabi_class;
> __entry->instance = rq->engine->uabi_instance;
> __entry->ctx = rq->fence.context;
> diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c b/drivers/gpu/drm/i915/selftests/i915_perf.c
> index d4608b220123ce..403134a7acec30 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_perf.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_perf.c
> @@ -168,7 +168,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
> return PTR_ERR(cs);
>
> len = 5;
> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
> + if (GRAPHICS_VER(rq->i915) >= 8)
> len++;
>
> *cs++ = GFX_OP_PIPE_CONTROL(len);
> diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c
> index 618d9386d55494..3c5e0952f1b81b 100644
> --- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
> +++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
> @@ -159,15 +159,15 @@ igt_spinner_create_request(struct igt_spinner *spin,
>
> batch = spin->batch;
>
> - if (GRAPHICS_VER(rq->engine->i915) >= 8) {
> + if (GRAPHICS_VER(rq->i915) >= 8) {
> *batch++ = MI_STORE_DWORD_IMM_GEN4;
> *batch++ = lower_32_bits(hws_address(hws, rq));
> *batch++ = upper_32_bits(hws_address(hws, rq));
> - } else if (GRAPHICS_VER(rq->engine->i915) >= 6) {
> + } else if (GRAPHICS_VER(rq->i915) >= 6) {
> *batch++ = MI_STORE_DWORD_IMM_GEN4;
> *batch++ = 0;
> *batch++ = hws_address(hws, rq);
> - } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
> + } else if (GRAPHICS_VER(rq->i915) >= 4) {
> *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> *batch++ = 0;
> *batch++ = hws_address(hws, rq);
> @@ -179,11 +179,11 @@ igt_spinner_create_request(struct igt_spinner *spin,
>
> *batch++ = arbitration_command;
>
> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
> + if (GRAPHICS_VER(rq->i915) >= 8)
> *batch++ = MI_BATCH_BUFFER_START | BIT(8) | 1;
> - else if (IS_HASWELL(rq->engine->i915))
> + else if (IS_HASWELL(rq->i915))
> *batch++ = MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW;
> - else if (GRAPHICS_VER(rq->engine->i915) >= 6)
> + else if (GRAPHICS_VER(rq->i915) >= 6)
> *batch++ = MI_BATCH_BUFFER_START;
> else
> *batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
> @@ -201,7 +201,7 @@ igt_spinner_create_request(struct igt_spinner *spin,
> }
>
> flags = 0;
> - if (GRAPHICS_VER(rq->engine->i915) <= 5)
> + if (GRAPHICS_VER(rq->i915) <= 5)
> flags |= I915_DISPATCH_SECURE;
> err = engine->emit_bb_start(rq, i915_vma_offset(vma), PAGE_SIZE, flags);
>
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: use direct alias for i915 in requests
2023-07-20 9:46 ` [Intel-gfx] [PATCH] " Tvrtko Ursulin
@ 2023-07-20 10:07 ` Tvrtko Ursulin
2023-07-20 10:48 ` Andrzej Hajda
2023-07-20 11:30 ` [Intel-gfx] [PATCH v2] " Andrzej Hajda
0 siblings, 2 replies; 17+ messages in thread
From: Tvrtko Ursulin @ 2023-07-20 10:07 UTC (permalink / raw)
To: Andrzej Hajda, intel-gfx; +Cc: Chris Wilson, Nirmoy Das
On 20/07/2023 10:46, Tvrtko Ursulin wrote:
>
> On 19/07/2023 16:07, Andrzej Hajda wrote:
>> i915_request contains direct alias to i915, there is no point to go via
>> rq->engine->i915.
>>
>> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
>> ---
>> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++--
>> drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +-
>> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 +++++++++---------
>> .../drm/i915/gt/intel_execlists_submission.c | 2 +-
>> drivers/gpu/drm/i915/gt/intel_migrate.c | 10 +++++-----
>> .../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
>> drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 2 +-
>> drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-
>> drivers/gpu/drm/i915/gt/selftest_rc6.c | 2 +-
>> drivers/gpu/drm/i915/gt/selftest_timeline.c | 4 ++--
>> drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
>> drivers/gpu/drm/i915/i915_perf.c | 2 +-
>> drivers/gpu/drm/i915/i915_request.c | 2 +-
>> drivers/gpu/drm/i915/i915_trace.h | 10 +++++-----
>> drivers/gpu/drm/i915/selftests/i915_perf.c | 2 +-
>> drivers/gpu/drm/i915/selftests/igt_spinner.c | 14 +++++++-------
>> 17 files changed, 42 insertions(+), 42 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>> index d3208a32561442..5a687a3686bd53 100644
>> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>> @@ -2229,8 +2229,8 @@ static int i915_reset_gen7_sol_offsets(struct
>> i915_request *rq)
>> u32 *cs;
>> int i;
>> - if (GRAPHICS_VER(rq->engine->i915) != 7 || rq->engine->id != RCS0) {
>> - drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs only\n");
>> + if (GRAPHICS_VER(rq->i915) != 7 || rq->engine->id != RCS0) {
>> + drm_dbg(&rq->i915->drm, "sol reset is gen7/rcs only\n");
>> return -EINVAL;
>> }
>> diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
>> b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
>> index 1c82caf525c346..8fe0499308ffe5 100644
>> --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
>> @@ -76,7 +76,7 @@ int gen4_emit_flush_rcs(struct i915_request *rq, u32
>> mode)
>> cmd = MI_FLUSH;
>> if (mode & EMIT_INVALIDATE) {
>> cmd |= MI_EXE_FLUSH;
>> - if (IS_G4X(rq->engine->i915) ||
>> GRAPHICS_VER(rq->engine->i915) == 5)
>> + if (IS_G4X(rq->i915) || GRAPHICS_VER(rq->i915) == 5)
>> cmd |= MI_INVALIDATE_ISP;
>> }
>> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> index 23857cc08eca1f..3ba20ea030e8d1 100644
>> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>> @@ -39,11 +39,11 @@ int gen8_emit_flush_rcs(struct i915_request *rq,
>> u32 mode)
>> * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
>> * pipe control.
>> */
>> - if (GRAPHICS_VER(rq->engine->i915) == 9)
>> + if (GRAPHICS_VER(rq->i915) == 9)
>> vf_flush_wa = true;
>> /* WaForGAMHang:kbl */
>> - if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
>> + if (IS_KBL_GRAPHICS_STEP(rq->i915, 0, STEP_C0))
>> dc_flush_wa = true;
>> }
>> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt,
>> u32 *cs, const i915_reg_t inv
>> static int mtl_dummy_pipe_control(struct i915_request *rq)
>> {
>> /* Wa_14016712196 */
>> - if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
>> - IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
>> + if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||
>> + IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {
>> u32 *cs;
>> /* dummy PIPE_CONTROL + depth flush */
>> @@ -267,7 +267,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq,
>> u32 mode)
>> else if (engine->class == COMPUTE_CLASS)
>> flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
>> - if (!HAS_FLAT_CCS(rq->engine->i915))
>> + if (!HAS_FLAT_CCS(rq->i915))
>> count = 8 + 4;
>> else
>> count = 8;
>> @@ -285,7 +285,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq,
>> u32 mode)
>> cs = gen8_emit_pipe_control(cs, flags,
>> LRC_PPHWSP_SCRATCH_ADDR);
>> - if (!HAS_FLAT_CCS(rq->engine->i915)) {
>> + if (!HAS_FLAT_CCS(rq->i915)) {
>> /* hsdes: 1809175790 */
>> cs = gen12_emit_aux_table_inv(rq->engine->gt,
>> cs, GEN12_GFX_CCS_AUX_NV);
>> @@ -307,7 +307,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq,
>> u32 mode)
>> if (mode & EMIT_INVALIDATE) {
>> cmd += 2;
>> - if (!HAS_FLAT_CCS(rq->engine->i915) &&
>> + if (!HAS_FLAT_CCS(rq->i915) &&
>> (rq->engine->class == VIDEO_DECODE_CLASS ||
>> rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) {
>> aux_inv = rq->engine->mask &
>> @@ -754,7 +754,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct
>> i915_request *rq, u32 *cs)
>> u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
>> {
>> - struct drm_i915_private *i915 = rq->engine->i915;
>> + struct drm_i915_private *i915 = rq->i915;
>> u32 flags = (PIPE_CONTROL_CS_STALL |
>> PIPE_CONTROL_TLB_INVALIDATE |
>> PIPE_CONTROL_TILE_CACHE_FLUSH |
>> @@ -775,7 +775,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct
>> i915_request *rq, u32 *cs)
>> /* Wa_1409600907 */
>> flags |= PIPE_CONTROL_DEPTH_STALL;
>> - if (!HAS_3D_PIPELINE(rq->engine->i915))
>> + if (!HAS_3D_PIPELINE(rq->i915))
>> flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
>> else if (rq->engine->class == COMPUTE_CLASS)
>> flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> index d85b5a6d981f99..8a641bcf777cb4 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>> @@ -2718,7 +2718,7 @@ static int emit_pdps(struct i915_request *rq)
>> int err, i;
>> u32 *cs;
>> - GEM_BUG_ON(intel_vgpu_active(rq->engine->i915));
>> + GEM_BUG_ON(intel_vgpu_active(rq->i915));
>> /*
>> * Beware ye of the dragons, this sequence is magic!
>> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
>> b/drivers/gpu/drm/i915/gt/intel_migrate.c
>> index 6023288b0e2dd5..576e5ef0289ba5 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
>> @@ -366,7 +366,7 @@ static int emit_pte(struct i915_request *rq,
>> u64 offset,
>> int length)
>> {
>> - bool has_64K_pages = HAS_64K_PAGES(rq->engine->i915);
>> + bool has_64K_pages = HAS_64K_PAGES(rq->i915);
>> const u64 encode = rq->context->vm->pte_encode(0, pat_index,
>> is_lmem ? PTE_LM : 0);
>> struct intel_ring *ring = rq->ring;
>> @@ -375,7 +375,7 @@ static int emit_pte(struct i915_request *rq,
>> u32 page_size;
>> u32 *hdr, *cs;
>> - GEM_BUG_ON(GRAPHICS_VER(rq->engine->i915) < 8);
>> + GEM_BUG_ON(GRAPHICS_VER(rq->i915) < 8);
>> page_size = I915_GTT_PAGE_SIZE;
>> dword_length = 0x400;
>> @@ -531,7 +531,7 @@ static int emit_copy_ccs(struct i915_request *rq,
>> u32 dst_offset, u8 dst_access,
>> u32 src_offset, u8 src_access, int size)
>> {
>> - struct drm_i915_private *i915 = rq->engine->i915;
>> + struct drm_i915_private *i915 = rq->i915;
>> int mocs = rq->engine->gt->mocs.uc_index << 1;
>> u32 num_ccs_blks;
>> u32 *cs;
>> @@ -581,7 +581,7 @@ static int emit_copy_ccs(struct i915_request *rq,
>> static int emit_copy(struct i915_request *rq,
>> u32 dst_offset, u32 src_offset, int size)
>> {
>> - const int ver = GRAPHICS_VER(rq->engine->i915);
>> + const int ver = GRAPHICS_VER(rq->i915);
>> u32 instance = rq->engine->instance;
>> u32 *cs;
>> @@ -917,7 +917,7 @@ intel_context_migrate_copy(struct intel_context *ce,
>> static int emit_clear(struct i915_request *rq, u32 offset, int size,
>> u32 value, bool is_lmem)
>> {
>> - struct drm_i915_private *i915 = rq->engine->i915;
>> + struct drm_i915_private *i915 = rq->i915;
>> int mocs = rq->engine->gt->mocs.uc_index << 1;
>> const int ver = GRAPHICS_VER(i915);
>> int ring_sz;
>> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>> b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>> index 3fd795c3263fd2..92085ffd23de0e 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>> @@ -805,7 +805,7 @@ static int mi_set_context(struct i915_request *rq,
>> static int remap_l3_slice(struct i915_request *rq, int slice)
>> {
>> #define L3LOG_DW (GEN7_L3LOG_SIZE / sizeof(u32))
>> - u32 *cs, *remap_info =
>> rq->engine->i915->l3_parity.remap_info[slice];
>> + u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
>> int i;
>> if (!remap_info)
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index b177c588698b08..589d009032fcd3 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -3249,7 +3249,7 @@ wa_list_srm(struct i915_request *rq,
>> const struct i915_wa_list *wal,
>> struct i915_vma *vma)
>> {
>> - struct drm_i915_private *i915 = rq->engine->i915;
>> + struct drm_i915_private *i915 = rq->i915;
>> unsigned int i, count = 0;
>> const struct i915_wa *wa;
>> u32 srm, *cs;
>> @@ -3348,7 +3348,7 @@ static int engine_wa_list_verify(struct
>> intel_context *ce,
>> err = 0;
>> for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
>> - if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg)))
>> + if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))
>> continue;
>> if (!wa_verify(wal->gt, wa, results[i], wal->name, from))
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
>> b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
>> index 78cdfc6f315f2a..86cecf7a110540 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
>> @@ -62,7 +62,7 @@ static int write_timestamp(struct i915_request *rq,
>> int slot)
>> return PTR_ERR(cs);
>> cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
>> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
>> + if (GRAPHICS_VER(rq->i915) >= 8)
>> cmd++;
>> *cs++ = cmd;
>> *cs++ = i915_mmio_reg_offset(timestamp_reg(rq->engine));
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c
>> b/drivers/gpu/drm/i915/gt/selftest_mocs.c
>> index a8446ab825012f..d73e438fb85fab 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
>> @@ -137,7 +137,7 @@ static int read_mocs_table(struct i915_request *rq,
>> if (!table)
>> return 0;
>> - if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915))
>> + if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915))
>> addr = global_mocs_offset() + gt->uncore->gsi_offset;
>> else
>> addr = mocs_offset(rq->engine);
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c
>> b/drivers/gpu/drm/i915/gt/selftest_rc6.c
>> index 2ceeadecc639cc..a7189c2d660cc5 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
>> @@ -140,7 +140,7 @@ static const u32 *__live_rc6_ctx(struct
>> intel_context *ce)
>> }
>> cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
>> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
>> + if (GRAPHICS_VER(rq->i915) >= 8)
>> cmd++;
>> *cs++ = cmd;
>> diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c
>> b/drivers/gpu/drm/i915/gt/selftest_timeline.c
>> index 39c3ec12df1abb..fa36cf920bdee9 100644
>> --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
>> +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
>> @@ -459,12 +459,12 @@ static int emit_ggtt_store_dw(struct
>> i915_request *rq, u32 addr, u32 value)
>> if (IS_ERR(cs))
>> return PTR_ERR(cs);
>> - if (GRAPHICS_VER(rq->engine->i915) >= 8) {
>> + if (GRAPHICS_VER(rq->i915) >= 8) {
>> *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>> *cs++ = addr;
>> *cs++ = 0;
>> *cs++ = value;
>> - } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
>> + } else if (GRAPHICS_VER(rq->i915) >= 4) {
>> *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>> *cs++ = 0;
>> *cs++ = addr;
>> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c
>> b/drivers/gpu/drm/i915/gvt/scheduler.c
>> index f4055804aad1fe..a5c8005ec484c3 100644
>> --- a/drivers/gpu/drm/i915/gvt/scheduler.c
>> +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
>> @@ -974,7 +974,7 @@ static void update_guest_context(struct
>> intel_vgpu_workload *workload)
>> context_page_num = rq->engine->context_size;
>> context_page_num = context_page_num >> PAGE_SHIFT;
>> - if (IS_BROADWELL(rq->engine->i915) && rq->engine->id == RCS0)
>> + if (IS_BROADWELL(rq->i915) && rq->engine->id == RCS0)
>> context_page_num = 19;
>> context_base = (void *) ctx->lrc_reg_state -
>> diff --git a/drivers/gpu/drm/i915/i915_perf.c
>> b/drivers/gpu/drm/i915/i915_perf.c
>> index 49c6f1ff11284f..04bc1f4a111504 100644
>> --- a/drivers/gpu/drm/i915/i915_perf.c
>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>> @@ -1319,7 +1319,7 @@ __store_reg_to_mem(struct i915_request *rq,
>> i915_reg_t reg, u32 ggtt_offset)
>> u32 *cs, cmd;
>> cmd = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
>> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
>> + if (GRAPHICS_VER(rq->i915) >= 8)
>> cmd++;
>> cs = intel_ring_begin(rq, 4);
>> diff --git a/drivers/gpu/drm/i915/i915_request.c
>> b/drivers/gpu/drm/i915/i915_request.c
>> index c5fe199b046d01..9d83f064456cd9 100644
>> --- a/drivers/gpu/drm/i915/i915_request.c
>> +++ b/drivers/gpu/drm/i915/i915_request.c
>> @@ -1341,7 +1341,7 @@ __i915_request_await_external(struct
>> i915_request *rq, struct dma_fence *fence)
>> {
>> mark_external(rq);
>> return i915_sw_fence_await_dma_fence(&rq->submit, fence,
>> - i915_fence_context_timeout(rq->engine->i915,
>> + i915_fence_context_timeout(rq->i915,
>> fence->context),
>> I915_FENCE_GFP);
>> }
>> diff --git a/drivers/gpu/drm/i915/i915_trace.h
>> b/drivers/gpu/drm/i915/i915_trace.h
>> index f6f9228a135185..ce1cbee1b39dd0 100644
>> --- a/drivers/gpu/drm/i915/i915_trace.h
>> +++ b/drivers/gpu/drm/i915/i915_trace.h
>> @@ -277,7 +277,7 @@ TRACE_EVENT(i915_request_queue,
>> ),
>> TP_fast_assign(
>> - __entry->dev = rq->engine->i915->drm.primary->index;
>> + __entry->dev = rq->i915->drm.primary->index;
>> __entry->class = rq->engine->uabi_class;
>> __entry->instance = rq->engine->uabi_instance;
>> __entry->ctx = rq->fence.context;
>> @@ -304,7 +304,7 @@ DECLARE_EVENT_CLASS(i915_request,
>> ),
>> TP_fast_assign(
>> - __entry->dev = rq->engine->i915->drm.primary->index;
>> + __entry->dev = rq->i915->drm.primary->index;
>> __entry->class = rq->engine->uabi_class;
>> __entry->instance = rq->engine->uabi_instance;
>> __entry->ctx = rq->fence.context;
>> @@ -353,7 +353,7 @@ TRACE_EVENT(i915_request_in,
>> ),
>> TP_fast_assign(
>> - __entry->dev = rq->engine->i915->drm.primary->index;
>> + __entry->dev = rq->i915->drm.primary->index;
>> __entry->class = rq->engine->uabi_class;
>> __entry->instance = rq->engine->uabi_instance;
>> __entry->ctx = rq->fence.context;
>> @@ -382,7 +382,7 @@ TRACE_EVENT(i915_request_out,
>> ),
>> TP_fast_assign(
>> - __entry->dev = rq->engine->i915->drm.primary->index;
>> + __entry->dev = rq->i915->drm.primary->index;
>> __entry->class = rq->engine->uabi_class;
>> __entry->instance = rq->engine->uabi_instance;
>> __entry->ctx = rq->fence.context;
>> @@ -623,7 +623,7 @@ TRACE_EVENT(i915_request_wait_begin,
>> * less desirable.
>> */
>> TP_fast_assign(
>> - __entry->dev = rq->engine->i915->drm.primary->index;
>> + __entry->dev = rq->i915->drm.primary->index;
>> __entry->class = rq->engine->uabi_class;
>> __entry->instance = rq->engine->uabi_instance;
>> __entry->ctx = rq->fence.context;
>> diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c
>> b/drivers/gpu/drm/i915/selftests/i915_perf.c
>> index d4608b220123ce..403134a7acec30 100644
>> --- a/drivers/gpu/drm/i915/selftests/i915_perf.c
>> +++ b/drivers/gpu/drm/i915/selftests/i915_perf.c
>> @@ -168,7 +168,7 @@ static int write_timestamp(struct i915_request
>> *rq, int slot)
>> return PTR_ERR(cs);
>> len = 5;
>> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
>> + if (GRAPHICS_VER(rq->i915) >= 8)
>> len++;
>> *cs++ = GFX_OP_PIPE_CONTROL(len);
>> diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c
>> b/drivers/gpu/drm/i915/selftests/igt_spinner.c
>> index 618d9386d55494..3c5e0952f1b81b 100644
>> --- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
>> +++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
>> @@ -159,15 +159,15 @@ igt_spinner_create_request(struct igt_spinner
>> *spin,
>> batch = spin->batch;
>> - if (GRAPHICS_VER(rq->engine->i915) >= 8) {
>> + if (GRAPHICS_VER(rq->i915) >= 8) {
>> *batch++ = MI_STORE_DWORD_IMM_GEN4;
>> *batch++ = lower_32_bits(hws_address(hws, rq));
>> *batch++ = upper_32_bits(hws_address(hws, rq));
>> - } else if (GRAPHICS_VER(rq->engine->i915) >= 6) {
>> + } else if (GRAPHICS_VER(rq->i915) >= 6) {
>> *batch++ = MI_STORE_DWORD_IMM_GEN4;
>> *batch++ = 0;
>> *batch++ = hws_address(hws, rq);
>> - } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
>> + } else if (GRAPHICS_VER(rq->i915) >= 4) {
>> *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>> *batch++ = 0;
>> *batch++ = hws_address(hws, rq);
>> @@ -179,11 +179,11 @@ igt_spinner_create_request(struct igt_spinner
>> *spin,
>> *batch++ = arbitration_command;
>> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
>> + if (GRAPHICS_VER(rq->i915) >= 8)
>> *batch++ = MI_BATCH_BUFFER_START | BIT(8) | 1;
>> - else if (IS_HASWELL(rq->engine->i915))
>> + else if (IS_HASWELL(rq->i915))
>> *batch++ = MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW;
>> - else if (GRAPHICS_VER(rq->engine->i915) >= 6)
>> + else if (GRAPHICS_VER(rq->i915) >= 6)
>> *batch++ = MI_BATCH_BUFFER_START;
>> else
>> *batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
>> @@ -201,7 +201,7 @@ igt_spinner_create_request(struct igt_spinner *spin,
>> }
>> flags = 0;
>> - if (GRAPHICS_VER(rq->engine->i915) <= 5)
>> + if (GRAPHICS_VER(rq->i915) <= 5)
>> flags |= I915_DISPATCH_SECURE;
>> err = engine->emit_bb_start(rq, i915_vma_offset(vma), PAGE_SIZE,
>> flags);
>
> Nice cleanup, thank you!
>
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> Apparently was possible ever since 7307e91bfcd0 ("drm/i915: Do not
> access rq->engine without a reference") which is funnily related to the
> other story we are discussing last few days.
CI disagrees with my r-b though - I think could be direct request
creation in measure_breadcrumb_dw.
Regards,
Tvrtko
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: use direct alias for i915 in requests
2023-07-20 10:07 ` Tvrtko Ursulin
@ 2023-07-20 10:48 ` Andrzej Hajda
2023-07-20 11:30 ` [Intel-gfx] [PATCH v2] " Andrzej Hajda
1 sibling, 0 replies; 17+ messages in thread
From: Andrzej Hajda @ 2023-07-20 10:48 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx; +Cc: Chris Wilson, Nirmoy Das
On 20.07.2023 12:07, Tvrtko Ursulin wrote:
>
> On 20/07/2023 10:46, Tvrtko Ursulin wrote:
>>
>> On 19/07/2023 16:07, Andrzej Hajda wrote:
>>> i915_request contains direct alias to i915, there is no point to go via
>>> rq->engine->i915.
>>>
>>> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++--
>>> drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +-
>>> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18
>>> +++++++++---------
>>> .../drm/i915/gt/intel_execlists_submission.c | 2 +-
>>> drivers/gpu/drm/i915/gt/intel_migrate.c | 10 +++++-----
>>> .../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
>>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
>>> drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 2 +-
>>> drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-
>>> drivers/gpu/drm/i915/gt/selftest_rc6.c | 2 +-
>>> drivers/gpu/drm/i915/gt/selftest_timeline.c | 4 ++--
>>> drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
>>> drivers/gpu/drm/i915/i915_perf.c | 2 +-
>>> drivers/gpu/drm/i915/i915_request.c | 2 +-
>>> drivers/gpu/drm/i915/i915_trace.h | 10 +++++-----
>>> drivers/gpu/drm/i915/selftests/i915_perf.c | 2 +-
>>> drivers/gpu/drm/i915/selftests/igt_spinner.c | 14 +++++++-------
>>> 17 files changed, 42 insertions(+), 42 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>>> b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>>> index d3208a32561442..5a687a3686bd53 100644
>>> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>>> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
>>> @@ -2229,8 +2229,8 @@ static int i915_reset_gen7_sol_offsets(struct
>>> i915_request *rq)
>>> u32 *cs;
>>> int i;
>>> - if (GRAPHICS_VER(rq->engine->i915) != 7 || rq->engine->id !=
>>> RCS0) {
>>> - drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs
>>> only\n");
>>> + if (GRAPHICS_VER(rq->i915) != 7 || rq->engine->id != RCS0) {
>>> + drm_dbg(&rq->i915->drm, "sol reset is gen7/rcs only\n");
>>> return -EINVAL;
>>> }
>>> diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
>>> b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
>>> index 1c82caf525c346..8fe0499308ffe5 100644
>>> --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
>>> +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
>>> @@ -76,7 +76,7 @@ int gen4_emit_flush_rcs(struct i915_request *rq,
>>> u32 mode)
>>> cmd = MI_FLUSH;
>>> if (mode & EMIT_INVALIDATE) {
>>> cmd |= MI_EXE_FLUSH;
>>> - if (IS_G4X(rq->engine->i915) ||
>>> GRAPHICS_VER(rq->engine->i915) == 5)
>>> + if (IS_G4X(rq->i915) || GRAPHICS_VER(rq->i915) == 5)
>>> cmd |= MI_INVALIDATE_ISP;
>>> }
>>> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>> b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>> index 23857cc08eca1f..3ba20ea030e8d1 100644
>>> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
>>> @@ -39,11 +39,11 @@ int gen8_emit_flush_rcs(struct i915_request *rq,
>>> u32 mode)
>>> * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
>>> * pipe control.
>>> */
>>> - if (GRAPHICS_VER(rq->engine->i915) == 9)
>>> + if (GRAPHICS_VER(rq->i915) == 9)
>>> vf_flush_wa = true;
>>> /* WaForGAMHang:kbl */
>>> - if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
>>> + if (IS_KBL_GRAPHICS_STEP(rq->i915, 0, STEP_C0))
>>> dc_flush_wa = true;
>>> }
>>> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt
>>> *gt, u32 *cs, const i915_reg_t inv
>>> static int mtl_dummy_pipe_control(struct i915_request *rq)
>>> {
>>> /* Wa_14016712196 */
>>> - if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
>>> - IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
>>> + if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||
>>> + IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {
>>> u32 *cs;
>>> /* dummy PIPE_CONTROL + depth flush */
>>> @@ -267,7 +267,7 @@ int gen12_emit_flush_rcs(struct i915_request
>>> *rq, u32 mode)
>>> else if (engine->class == COMPUTE_CLASS)
>>> flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
>>> - if (!HAS_FLAT_CCS(rq->engine->i915))
>>> + if (!HAS_FLAT_CCS(rq->i915))
>>> count = 8 + 4;
>>> else
>>> count = 8;
>>> @@ -285,7 +285,7 @@ int gen12_emit_flush_rcs(struct i915_request
>>> *rq, u32 mode)
>>> cs = gen8_emit_pipe_control(cs, flags,
>>> LRC_PPHWSP_SCRATCH_ADDR);
>>> - if (!HAS_FLAT_CCS(rq->engine->i915)) {
>>> + if (!HAS_FLAT_CCS(rq->i915)) {
>>> /* hsdes: 1809175790 */
>>> cs = gen12_emit_aux_table_inv(rq->engine->gt,
>>> cs, GEN12_GFX_CCS_AUX_NV);
>>> @@ -307,7 +307,7 @@ int gen12_emit_flush_xcs(struct i915_request
>>> *rq, u32 mode)
>>> if (mode & EMIT_INVALIDATE) {
>>> cmd += 2;
>>> - if (!HAS_FLAT_CCS(rq->engine->i915) &&
>>> + if (!HAS_FLAT_CCS(rq->i915) &&
>>> (rq->engine->class == VIDEO_DECODE_CLASS ||
>>> rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) {
>>> aux_inv = rq->engine->mask &
>>> @@ -754,7 +754,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct
>>> i915_request *rq, u32 *cs)
>>> u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
>>> {
>>> - struct drm_i915_private *i915 = rq->engine->i915;
>>> + struct drm_i915_private *i915 = rq->i915;
>>> u32 flags = (PIPE_CONTROL_CS_STALL |
>>> PIPE_CONTROL_TLB_INVALIDATE |
>>> PIPE_CONTROL_TILE_CACHE_FLUSH |
>>> @@ -775,7 +775,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct
>>> i915_request *rq, u32 *cs)
>>> /* Wa_1409600907 */
>>> flags |= PIPE_CONTROL_DEPTH_STALL;
>>> - if (!HAS_3D_PIPELINE(rq->engine->i915))
>>> + if (!HAS_3D_PIPELINE(rq->i915))
>>> flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
>>> else if (rq->engine->class == COMPUTE_CLASS)
>>> flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>> b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>> index d85b5a6d981f99..8a641bcf777cb4 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
>>> @@ -2718,7 +2718,7 @@ static int emit_pdps(struct i915_request *rq)
>>> int err, i;
>>> u32 *cs;
>>> - GEM_BUG_ON(intel_vgpu_active(rq->engine->i915));
>>> + GEM_BUG_ON(intel_vgpu_active(rq->i915));
>>> /*
>>> * Beware ye of the dragons, this sequence is magic!
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c
>>> b/drivers/gpu/drm/i915/gt/intel_migrate.c
>>> index 6023288b0e2dd5..576e5ef0289ba5 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
>>> @@ -366,7 +366,7 @@ static int emit_pte(struct i915_request *rq,
>>> u64 offset,
>>> int length)
>>> {
>>> - bool has_64K_pages = HAS_64K_PAGES(rq->engine->i915);
>>> + bool has_64K_pages = HAS_64K_PAGES(rq->i915);
>>> const u64 encode = rq->context->vm->pte_encode(0, pat_index,
>>> is_lmem ? PTE_LM : 0);
>>> struct intel_ring *ring = rq->ring;
>>> @@ -375,7 +375,7 @@ static int emit_pte(struct i915_request *rq,
>>> u32 page_size;
>>> u32 *hdr, *cs;
>>> - GEM_BUG_ON(GRAPHICS_VER(rq->engine->i915) < 8);
>>> + GEM_BUG_ON(GRAPHICS_VER(rq->i915) < 8);
>>> page_size = I915_GTT_PAGE_SIZE;
>>> dword_length = 0x400;
>>> @@ -531,7 +531,7 @@ static int emit_copy_ccs(struct i915_request *rq,
>>> u32 dst_offset, u8 dst_access,
>>> u32 src_offset, u8 src_access, int size)
>>> {
>>> - struct drm_i915_private *i915 = rq->engine->i915;
>>> + struct drm_i915_private *i915 = rq->i915;
>>> int mocs = rq->engine->gt->mocs.uc_index << 1;
>>> u32 num_ccs_blks;
>>> u32 *cs;
>>> @@ -581,7 +581,7 @@ static int emit_copy_ccs(struct i915_request *rq,
>>> static int emit_copy(struct i915_request *rq,
>>> u32 dst_offset, u32 src_offset, int size)
>>> {
>>> - const int ver = GRAPHICS_VER(rq->engine->i915);
>>> + const int ver = GRAPHICS_VER(rq->i915);
>>> u32 instance = rq->engine->instance;
>>> u32 *cs;
>>> @@ -917,7 +917,7 @@ intel_context_migrate_copy(struct intel_context
>>> *ce,
>>> static int emit_clear(struct i915_request *rq, u32 offset, int size,
>>> u32 value, bool is_lmem)
>>> {
>>> - struct drm_i915_private *i915 = rq->engine->i915;
>>> + struct drm_i915_private *i915 = rq->i915;
>>> int mocs = rq->engine->gt->mocs.uc_index << 1;
>>> const int ver = GRAPHICS_VER(i915);
>>> int ring_sz;
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>>> b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>>> index 3fd795c3263fd2..92085ffd23de0e 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
>>> @@ -805,7 +805,7 @@ static int mi_set_context(struct i915_request *rq,
>>> static int remap_l3_slice(struct i915_request *rq, int slice)
>>> {
>>> #define L3LOG_DW (GEN7_L3LOG_SIZE / sizeof(u32))
>>> - u32 *cs, *remap_info =
>>> rq->engine->i915->l3_parity.remap_info[slice];
>>> + u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
>>> int i;
>>> if (!remap_info)
>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> index b177c588698b08..589d009032fcd3 100644
>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>> @@ -3249,7 +3249,7 @@ wa_list_srm(struct i915_request *rq,
>>> const struct i915_wa_list *wal,
>>> struct i915_vma *vma)
>>> {
>>> - struct drm_i915_private *i915 = rq->engine->i915;
>>> + struct drm_i915_private *i915 = rq->i915;
>>> unsigned int i, count = 0;
>>> const struct i915_wa *wa;
>>> u32 srm, *cs;
>>> @@ -3348,7 +3348,7 @@ static int engine_wa_list_verify(struct
>>> intel_context *ce,
>>> err = 0;
>>> for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
>>> - if (mcr_range(rq->engine->i915,
>>> i915_mmio_reg_offset(wa->reg)))
>>> + if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))
>>> continue;
>>> if (!wa_verify(wal->gt, wa, results[i], wal->name, from))
>>> diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
>>> b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
>>> index 78cdfc6f315f2a..86cecf7a110540 100644
>>> --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
>>> +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
>>> @@ -62,7 +62,7 @@ static int write_timestamp(struct i915_request
>>> *rq, int slot)
>>> return PTR_ERR(cs);
>>> cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
>>> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
>>> + if (GRAPHICS_VER(rq->i915) >= 8)
>>> cmd++;
>>> *cs++ = cmd;
>>> *cs++ = i915_mmio_reg_offset(timestamp_reg(rq->engine));
>>> diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c
>>> b/drivers/gpu/drm/i915/gt/selftest_mocs.c
>>> index a8446ab825012f..d73e438fb85fab 100644
>>> --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
>>> +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
>>> @@ -137,7 +137,7 @@ static int read_mocs_table(struct i915_request *rq,
>>> if (!table)
>>> return 0;
>>> - if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915))
>>> + if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915))
>>> addr = global_mocs_offset() + gt->uncore->gsi_offset;
>>> else
>>> addr = mocs_offset(rq->engine);
>>> diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c
>>> b/drivers/gpu/drm/i915/gt/selftest_rc6.c
>>> index 2ceeadecc639cc..a7189c2d660cc5 100644
>>> --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
>>> +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
>>> @@ -140,7 +140,7 @@ static const u32 *__live_rc6_ctx(struct
>>> intel_context *ce)
>>> }
>>> cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
>>> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
>>> + if (GRAPHICS_VER(rq->i915) >= 8)
>>> cmd++;
>>> *cs++ = cmd;
>>> diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c
>>> b/drivers/gpu/drm/i915/gt/selftest_timeline.c
>>> index 39c3ec12df1abb..fa36cf920bdee9 100644
>>> --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
>>> +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
>>> @@ -459,12 +459,12 @@ static int emit_ggtt_store_dw(struct
>>> i915_request *rq, u32 addr, u32 value)
>>> if (IS_ERR(cs))
>>> return PTR_ERR(cs);
>>> - if (GRAPHICS_VER(rq->engine->i915) >= 8) {
>>> + if (GRAPHICS_VER(rq->i915) >= 8) {
>>> *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>>> *cs++ = addr;
>>> *cs++ = 0;
>>> *cs++ = value;
>>> - } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
>>> + } else if (GRAPHICS_VER(rq->i915) >= 4) {
>>> *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>>> *cs++ = 0;
>>> *cs++ = addr;
>>> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c
>>> b/drivers/gpu/drm/i915/gvt/scheduler.c
>>> index f4055804aad1fe..a5c8005ec484c3 100644
>>> --- a/drivers/gpu/drm/i915/gvt/scheduler.c
>>> +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
>>> @@ -974,7 +974,7 @@ static void update_guest_context(struct
>>> intel_vgpu_workload *workload)
>>> context_page_num = rq->engine->context_size;
>>> context_page_num = context_page_num >> PAGE_SHIFT;
>>> - if (IS_BROADWELL(rq->engine->i915) && rq->engine->id == RCS0)
>>> + if (IS_BROADWELL(rq->i915) && rq->engine->id == RCS0)
>>> context_page_num = 19;
>>> context_base = (void *) ctx->lrc_reg_state -
>>> diff --git a/drivers/gpu/drm/i915/i915_perf.c
>>> b/drivers/gpu/drm/i915/i915_perf.c
>>> index 49c6f1ff11284f..04bc1f4a111504 100644
>>> --- a/drivers/gpu/drm/i915/i915_perf.c
>>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>>> @@ -1319,7 +1319,7 @@ __store_reg_to_mem(struct i915_request *rq,
>>> i915_reg_t reg, u32 ggtt_offset)
>>> u32 *cs, cmd;
>>> cmd = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
>>> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
>>> + if (GRAPHICS_VER(rq->i915) >= 8)
>>> cmd++;
>>> cs = intel_ring_begin(rq, 4);
>>> diff --git a/drivers/gpu/drm/i915/i915_request.c
>>> b/drivers/gpu/drm/i915/i915_request.c
>>> index c5fe199b046d01..9d83f064456cd9 100644
>>> --- a/drivers/gpu/drm/i915/i915_request.c
>>> +++ b/drivers/gpu/drm/i915/i915_request.c
>>> @@ -1341,7 +1341,7 @@ __i915_request_await_external(struct
>>> i915_request *rq, struct dma_fence *fence)
>>> {
>>> mark_external(rq);
>>> return i915_sw_fence_await_dma_fence(&rq->submit, fence,
>>> - i915_fence_context_timeout(rq->engine->i915,
>>> + i915_fence_context_timeout(rq->i915,
>>> fence->context),
>>> I915_FENCE_GFP);
>>> }
>>> diff --git a/drivers/gpu/drm/i915/i915_trace.h
>>> b/drivers/gpu/drm/i915/i915_trace.h
>>> index f6f9228a135185..ce1cbee1b39dd0 100644
>>> --- a/drivers/gpu/drm/i915/i915_trace.h
>>> +++ b/drivers/gpu/drm/i915/i915_trace.h
>>> @@ -277,7 +277,7 @@ TRACE_EVENT(i915_request_queue,
>>> ),
>>> TP_fast_assign(
>>> - __entry->dev = rq->engine->i915->drm.primary->index;
>>> + __entry->dev = rq->i915->drm.primary->index;
>>> __entry->class = rq->engine->uabi_class;
>>> __entry->instance = rq->engine->uabi_instance;
>>> __entry->ctx = rq->fence.context;
>>> @@ -304,7 +304,7 @@ DECLARE_EVENT_CLASS(i915_request,
>>> ),
>>> TP_fast_assign(
>>> - __entry->dev = rq->engine->i915->drm.primary->index;
>>> + __entry->dev = rq->i915->drm.primary->index;
>>> __entry->class = rq->engine->uabi_class;
>>> __entry->instance = rq->engine->uabi_instance;
>>> __entry->ctx = rq->fence.context;
>>> @@ -353,7 +353,7 @@ TRACE_EVENT(i915_request_in,
>>> ),
>>> TP_fast_assign(
>>> - __entry->dev = rq->engine->i915->drm.primary->index;
>>> + __entry->dev = rq->i915->drm.primary->index;
>>> __entry->class = rq->engine->uabi_class;
>>> __entry->instance = rq->engine->uabi_instance;
>>> __entry->ctx = rq->fence.context;
>>> @@ -382,7 +382,7 @@ TRACE_EVENT(i915_request_out,
>>> ),
>>> TP_fast_assign(
>>> - __entry->dev = rq->engine->i915->drm.primary->index;
>>> + __entry->dev = rq->i915->drm.primary->index;
>>> __entry->class = rq->engine->uabi_class;
>>> __entry->instance = rq->engine->uabi_instance;
>>> __entry->ctx = rq->fence.context;
>>> @@ -623,7 +623,7 @@ TRACE_EVENT(i915_request_wait_begin,
>>> * less desirable.
>>> */
>>> TP_fast_assign(
>>> - __entry->dev = rq->engine->i915->drm.primary->index;
>>> + __entry->dev = rq->i915->drm.primary->index;
>>> __entry->class = rq->engine->uabi_class;
>>> __entry->instance = rq->engine->uabi_instance;
>>> __entry->ctx = rq->fence.context;
>>> diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c
>>> b/drivers/gpu/drm/i915/selftests/i915_perf.c
>>> index d4608b220123ce..403134a7acec30 100644
>>> --- a/drivers/gpu/drm/i915/selftests/i915_perf.c
>>> +++ b/drivers/gpu/drm/i915/selftests/i915_perf.c
>>> @@ -168,7 +168,7 @@ static int write_timestamp(struct i915_request
>>> *rq, int slot)
>>> return PTR_ERR(cs);
>>> len = 5;
>>> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
>>> + if (GRAPHICS_VER(rq->i915) >= 8)
>>> len++;
>>> *cs++ = GFX_OP_PIPE_CONTROL(len);
>>> diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c
>>> b/drivers/gpu/drm/i915/selftests/igt_spinner.c
>>> index 618d9386d55494..3c5e0952f1b81b 100644
>>> --- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
>>> +++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
>>> @@ -159,15 +159,15 @@ igt_spinner_create_request(struct igt_spinner
>>> *spin,
>>> batch = spin->batch;
>>> - if (GRAPHICS_VER(rq->engine->i915) >= 8) {
>>> + if (GRAPHICS_VER(rq->i915) >= 8) {
>>> *batch++ = MI_STORE_DWORD_IMM_GEN4;
>>> *batch++ = lower_32_bits(hws_address(hws, rq));
>>> *batch++ = upper_32_bits(hws_address(hws, rq));
>>> - } else if (GRAPHICS_VER(rq->engine->i915) >= 6) {
>>> + } else if (GRAPHICS_VER(rq->i915) >= 6) {
>>> *batch++ = MI_STORE_DWORD_IMM_GEN4;
>>> *batch++ = 0;
>>> *batch++ = hws_address(hws, rq);
>>> - } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
>>> + } else if (GRAPHICS_VER(rq->i915) >= 4) {
>>> *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>>> *batch++ = 0;
>>> *batch++ = hws_address(hws, rq);
>>> @@ -179,11 +179,11 @@ igt_spinner_create_request(struct igt_spinner
>>> *spin,
>>> *batch++ = arbitration_command;
>>> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
>>> + if (GRAPHICS_VER(rq->i915) >= 8)
>>> *batch++ = MI_BATCH_BUFFER_START | BIT(8) | 1;
>>> - else if (IS_HASWELL(rq->engine->i915))
>>> + else if (IS_HASWELL(rq->i915))
>>> *batch++ = MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW;
>>> - else if (GRAPHICS_VER(rq->engine->i915) >= 6)
>>> + else if (GRAPHICS_VER(rq->i915) >= 6)
>>> *batch++ = MI_BATCH_BUFFER_START;
>>> else
>>> *batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
>>> @@ -201,7 +201,7 @@ igt_spinner_create_request(struct igt_spinner
>>> *spin,
>>> }
>>> flags = 0;
>>> - if (GRAPHICS_VER(rq->engine->i915) <= 5)
>>> + if (GRAPHICS_VER(rq->i915) <= 5)
>>> flags |= I915_DISPATCH_SECURE;
>>> err = engine->emit_bb_start(rq, i915_vma_offset(vma),
>>> PAGE_SIZE, flags);
>>
>> Nice cleanup, thank you!
>>
>> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> Apparently was possible ever since 7307e91bfcd0 ("drm/i915: Do not
>> access rq->engine without a reference") which is funnily related to
>> the other story we are discussing last few days.
>
> CI disagrees with my r-b though - I think could be direct request
> creation in measure_breadcrumb_dw.
Yes, it looks to be the cause, thx for spotting this.
Regards
Andrzej
>
> Regards,
>
> Tvrtko
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH v2] drm/i915: use direct alias for i915 in requests
2023-07-20 10:07 ` Tvrtko Ursulin
2023-07-20 10:48 ` Andrzej Hajda
@ 2023-07-20 11:30 ` Andrzej Hajda
2023-07-24 15:29 ` Andrzej Hajda
1 sibling, 1 reply; 17+ messages in thread
From: Andrzej Hajda @ 2023-07-20 11:30 UTC (permalink / raw)
To: intel-gfx; +Cc: Andrzej Hajda, Chris Wilson, Nirmoy Das
i915_request contains direct alias to i915, there is no point to go via
rq->engine->i915.
v2: added missing rq.i915 initialization in measure_breadcrumb_dw.
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Acked-by: Nirmoy Das <nirmoy.das@intel.com>
---
drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++--
drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 +++++++++---------
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
.../drm/i915/gt/intel_execlists_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_migrate.c | 10 +++++-----
.../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_rc6.c | 2 +-
drivers/gpu/drm/i915/gt/selftest_timeline.c | 4 ++--
drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
drivers/gpu/drm/i915/i915_perf.c | 2 +-
drivers/gpu/drm/i915/i915_request.c | 2 +-
drivers/gpu/drm/i915/i915_trace.h | 10 +++++-----
drivers/gpu/drm/i915/selftests/i915_perf.c | 2 +-
drivers/gpu/drm/i915/selftests/igt_spinner.c | 14 +++++++-------
18 files changed, 43 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index d3208a32561442..5a687a3686bd53 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2229,8 +2229,8 @@ static int i915_reset_gen7_sol_offsets(struct i915_request *rq)
u32 *cs;
int i;
- if (GRAPHICS_VER(rq->engine->i915) != 7 || rq->engine->id != RCS0) {
- drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs only\n");
+ if (GRAPHICS_VER(rq->i915) != 7 || rq->engine->id != RCS0) {
+ drm_dbg(&rq->i915->drm, "sol reset is gen7/rcs only\n");
return -EINVAL;
}
diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
index 1c82caf525c346..8fe0499308ffe5 100644
--- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
@@ -76,7 +76,7 @@ int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode)
cmd = MI_FLUSH;
if (mode & EMIT_INVALIDATE) {
cmd |= MI_EXE_FLUSH;
- if (IS_G4X(rq->engine->i915) || GRAPHICS_VER(rq->engine->i915) == 5)
+ if (IS_G4X(rq->i915) || GRAPHICS_VER(rq->i915) == 5)
cmd |= MI_INVALIDATE_ISP;
}
diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
index 23857cc08eca1f..3ba20ea030e8d1 100644
--- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
@@ -39,11 +39,11 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
* On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
* pipe control.
*/
- if (GRAPHICS_VER(rq->engine->i915) == 9)
+ if (GRAPHICS_VER(rq->i915) == 9)
vf_flush_wa = true;
/* WaForGAMHang:kbl */
- if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
+ if (IS_KBL_GRAPHICS_STEP(rq->i915, 0, STEP_C0))
dc_flush_wa = true;
}
@@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
static int mtl_dummy_pipe_control(struct i915_request *rq)
{
/* Wa_14016712196 */
- if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
- IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
+ if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||
+ IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {
u32 *cs;
/* dummy PIPE_CONTROL + depth flush */
@@ -267,7 +267,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
else if (engine->class == COMPUTE_CLASS)
flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
- if (!HAS_FLAT_CCS(rq->engine->i915))
+ if (!HAS_FLAT_CCS(rq->i915))
count = 8 + 4;
else
count = 8;
@@ -285,7 +285,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
- if (!HAS_FLAT_CCS(rq->engine->i915)) {
+ if (!HAS_FLAT_CCS(rq->i915)) {
/* hsdes: 1809175790 */
cs = gen12_emit_aux_table_inv(rq->engine->gt,
cs, GEN12_GFX_CCS_AUX_NV);
@@ -307,7 +307,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
if (mode & EMIT_INVALIDATE) {
cmd += 2;
- if (!HAS_FLAT_CCS(rq->engine->i915) &&
+ if (!HAS_FLAT_CCS(rq->i915) &&
(rq->engine->class == VIDEO_DECODE_CLASS ||
rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) {
aux_inv = rq->engine->mask &
@@ -754,7 +754,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
{
- struct drm_i915_private *i915 = rq->engine->i915;
+ struct drm_i915_private *i915 = rq->i915;
u32 flags = (PIPE_CONTROL_CS_STALL |
PIPE_CONTROL_TLB_INVALIDATE |
PIPE_CONTROL_TILE_CACHE_FLUSH |
@@ -775,7 +775,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
/* Wa_1409600907 */
flags |= PIPE_CONTROL_DEPTH_STALL;
- if (!HAS_3D_PIPELINE(rq->engine->i915))
+ if (!HAS_3D_PIPELINE(rq->i915))
flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
else if (rq->engine->class == COMPUTE_CLASS)
flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 0aff5bb13c538e..ee15486fed0daa 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1333,6 +1333,7 @@ static int measure_breadcrumb_dw(struct intel_context *ce)
if (!frame)
return -ENOMEM;
+ frame->rq.i915 = engine->i915;
frame->rq.engine = engine;
frame->rq.context = ce;
rcu_assign_pointer(frame->rq.timeline, ce->timeline);
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index d85b5a6d981f99..8a641bcf777cb4 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2718,7 +2718,7 @@ static int emit_pdps(struct i915_request *rq)
int err, i;
u32 *cs;
- GEM_BUG_ON(intel_vgpu_active(rq->engine->i915));
+ GEM_BUG_ON(intel_vgpu_active(rq->i915));
/*
* Beware ye of the dragons, this sequence is magic!
diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
index 6023288b0e2dd5..576e5ef0289ba5 100644
--- a/drivers/gpu/drm/i915/gt/intel_migrate.c
+++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
@@ -366,7 +366,7 @@ static int emit_pte(struct i915_request *rq,
u64 offset,
int length)
{
- bool has_64K_pages = HAS_64K_PAGES(rq->engine->i915);
+ bool has_64K_pages = HAS_64K_PAGES(rq->i915);
const u64 encode = rq->context->vm->pte_encode(0, pat_index,
is_lmem ? PTE_LM : 0);
struct intel_ring *ring = rq->ring;
@@ -375,7 +375,7 @@ static int emit_pte(struct i915_request *rq,
u32 page_size;
u32 *hdr, *cs;
- GEM_BUG_ON(GRAPHICS_VER(rq->engine->i915) < 8);
+ GEM_BUG_ON(GRAPHICS_VER(rq->i915) < 8);
page_size = I915_GTT_PAGE_SIZE;
dword_length = 0x400;
@@ -531,7 +531,7 @@ static int emit_copy_ccs(struct i915_request *rq,
u32 dst_offset, u8 dst_access,
u32 src_offset, u8 src_access, int size)
{
- struct drm_i915_private *i915 = rq->engine->i915;
+ struct drm_i915_private *i915 = rq->i915;
int mocs = rq->engine->gt->mocs.uc_index << 1;
u32 num_ccs_blks;
u32 *cs;
@@ -581,7 +581,7 @@ static int emit_copy_ccs(struct i915_request *rq,
static int emit_copy(struct i915_request *rq,
u32 dst_offset, u32 src_offset, int size)
{
- const int ver = GRAPHICS_VER(rq->engine->i915);
+ const int ver = GRAPHICS_VER(rq->i915);
u32 instance = rq->engine->instance;
u32 *cs;
@@ -917,7 +917,7 @@ intel_context_migrate_copy(struct intel_context *ce,
static int emit_clear(struct i915_request *rq, u32 offset, int size,
u32 value, bool is_lmem)
{
- struct drm_i915_private *i915 = rq->engine->i915;
+ struct drm_i915_private *i915 = rq->i915;
int mocs = rq->engine->gt->mocs.uc_index << 1;
const int ver = GRAPHICS_VER(i915);
int ring_sz;
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 3fd795c3263fd2..92085ffd23de0e 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -805,7 +805,7 @@ static int mi_set_context(struct i915_request *rq,
static int remap_l3_slice(struct i915_request *rq, int slice)
{
#define L3LOG_DW (GEN7_L3LOG_SIZE / sizeof(u32))
- u32 *cs, *remap_info = rq->engine->i915->l3_parity.remap_info[slice];
+ u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
int i;
if (!remap_info)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index b177c588698b08..589d009032fcd3 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -3249,7 +3249,7 @@ wa_list_srm(struct i915_request *rq,
const struct i915_wa_list *wal,
struct i915_vma *vma)
{
- struct drm_i915_private *i915 = rq->engine->i915;
+ struct drm_i915_private *i915 = rq->i915;
unsigned int i, count = 0;
const struct i915_wa *wa;
u32 srm, *cs;
@@ -3348,7 +3348,7 @@ static int engine_wa_list_verify(struct intel_context *ce,
err = 0;
for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
- if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg)))
+ if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))
continue;
if (!wa_verify(wal->gt, wa, results[i], wal->name, from))
diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
index 78cdfc6f315f2a..86cecf7a110540 100644
--- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
@@ -62,7 +62,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
return PTR_ERR(cs);
cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
- if (GRAPHICS_VER(rq->engine->i915) >= 8)
+ if (GRAPHICS_VER(rq->i915) >= 8)
cmd++;
*cs++ = cmd;
*cs++ = i915_mmio_reg_offset(timestamp_reg(rq->engine));
diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
index a8446ab825012f..d73e438fb85fab 100644
--- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
+++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
@@ -137,7 +137,7 @@ static int read_mocs_table(struct i915_request *rq,
if (!table)
return 0;
- if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915))
+ if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915))
addr = global_mocs_offset() + gt->uncore->gsi_offset;
else
addr = mocs_offset(rq->engine);
diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
index 2ceeadecc639cc..a7189c2d660cc5 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
@@ -140,7 +140,7 @@ static const u32 *__live_rc6_ctx(struct intel_context *ce)
}
cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
- if (GRAPHICS_VER(rq->engine->i915) >= 8)
+ if (GRAPHICS_VER(rq->i915) >= 8)
cmd++;
*cs++ = cmd;
diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
index 39c3ec12df1abb..fa36cf920bdee9 100644
--- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
+++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
@@ -459,12 +459,12 @@ static int emit_ggtt_store_dw(struct i915_request *rq, u32 addr, u32 value)
if (IS_ERR(cs))
return PTR_ERR(cs);
- if (GRAPHICS_VER(rq->engine->i915) >= 8) {
+ if (GRAPHICS_VER(rq->i915) >= 8) {
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*cs++ = addr;
*cs++ = 0;
*cs++ = value;
- } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
+ } else if (GRAPHICS_VER(rq->i915) >= 4) {
*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*cs++ = 0;
*cs++ = addr;
diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
index f4055804aad1fe..a5c8005ec484c3 100644
--- a/drivers/gpu/drm/i915/gvt/scheduler.c
+++ b/drivers/gpu/drm/i915/gvt/scheduler.c
@@ -974,7 +974,7 @@ static void update_guest_context(struct intel_vgpu_workload *workload)
context_page_num = rq->engine->context_size;
context_page_num = context_page_num >> PAGE_SHIFT;
- if (IS_BROADWELL(rq->engine->i915) && rq->engine->id == RCS0)
+ if (IS_BROADWELL(rq->i915) && rq->engine->id == RCS0)
context_page_num = 19;
context_base = (void *) ctx->lrc_reg_state -
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 49c6f1ff11284f..04bc1f4a111504 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1319,7 +1319,7 @@ __store_reg_to_mem(struct i915_request *rq, i915_reg_t reg, u32 ggtt_offset)
u32 *cs, cmd;
cmd = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
- if (GRAPHICS_VER(rq->engine->i915) >= 8)
+ if (GRAPHICS_VER(rq->i915) >= 8)
cmd++;
cs = intel_ring_begin(rq, 4);
diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
index c5fe199b046d01..9d83f064456cd9 100644
--- a/drivers/gpu/drm/i915/i915_request.c
+++ b/drivers/gpu/drm/i915/i915_request.c
@@ -1341,7 +1341,7 @@ __i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
{
mark_external(rq);
return i915_sw_fence_await_dma_fence(&rq->submit, fence,
- i915_fence_context_timeout(rq->engine->i915,
+ i915_fence_context_timeout(rq->i915,
fence->context),
I915_FENCE_GFP);
}
diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
index f6f9228a135185..ce1cbee1b39dd0 100644
--- a/drivers/gpu/drm/i915/i915_trace.h
+++ b/drivers/gpu/drm/i915/i915_trace.h
@@ -277,7 +277,7 @@ TRACE_EVENT(i915_request_queue,
),
TP_fast_assign(
- __entry->dev = rq->engine->i915->drm.primary->index;
+ __entry->dev = rq->i915->drm.primary->index;
__entry->class = rq->engine->uabi_class;
__entry->instance = rq->engine->uabi_instance;
__entry->ctx = rq->fence.context;
@@ -304,7 +304,7 @@ DECLARE_EVENT_CLASS(i915_request,
),
TP_fast_assign(
- __entry->dev = rq->engine->i915->drm.primary->index;
+ __entry->dev = rq->i915->drm.primary->index;
__entry->class = rq->engine->uabi_class;
__entry->instance = rq->engine->uabi_instance;
__entry->ctx = rq->fence.context;
@@ -353,7 +353,7 @@ TRACE_EVENT(i915_request_in,
),
TP_fast_assign(
- __entry->dev = rq->engine->i915->drm.primary->index;
+ __entry->dev = rq->i915->drm.primary->index;
__entry->class = rq->engine->uabi_class;
__entry->instance = rq->engine->uabi_instance;
__entry->ctx = rq->fence.context;
@@ -382,7 +382,7 @@ TRACE_EVENT(i915_request_out,
),
TP_fast_assign(
- __entry->dev = rq->engine->i915->drm.primary->index;
+ __entry->dev = rq->i915->drm.primary->index;
__entry->class = rq->engine->uabi_class;
__entry->instance = rq->engine->uabi_instance;
__entry->ctx = rq->fence.context;
@@ -623,7 +623,7 @@ TRACE_EVENT(i915_request_wait_begin,
* less desirable.
*/
TP_fast_assign(
- __entry->dev = rq->engine->i915->drm.primary->index;
+ __entry->dev = rq->i915->drm.primary->index;
__entry->class = rq->engine->uabi_class;
__entry->instance = rq->engine->uabi_instance;
__entry->ctx = rq->fence.context;
diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c b/drivers/gpu/drm/i915/selftests/i915_perf.c
index d4608b220123ce..403134a7acec30 100644
--- a/drivers/gpu/drm/i915/selftests/i915_perf.c
+++ b/drivers/gpu/drm/i915/selftests/i915_perf.c
@@ -168,7 +168,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
return PTR_ERR(cs);
len = 5;
- if (GRAPHICS_VER(rq->engine->i915) >= 8)
+ if (GRAPHICS_VER(rq->i915) >= 8)
len++;
*cs++ = GFX_OP_PIPE_CONTROL(len);
diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c
index 618d9386d55494..3c5e0952f1b81b 100644
--- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
+++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
@@ -159,15 +159,15 @@ igt_spinner_create_request(struct igt_spinner *spin,
batch = spin->batch;
- if (GRAPHICS_VER(rq->engine->i915) >= 8) {
+ if (GRAPHICS_VER(rq->i915) >= 8) {
*batch++ = MI_STORE_DWORD_IMM_GEN4;
*batch++ = lower_32_bits(hws_address(hws, rq));
*batch++ = upper_32_bits(hws_address(hws, rq));
- } else if (GRAPHICS_VER(rq->engine->i915) >= 6) {
+ } else if (GRAPHICS_VER(rq->i915) >= 6) {
*batch++ = MI_STORE_DWORD_IMM_GEN4;
*batch++ = 0;
*batch++ = hws_address(hws, rq);
- } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
+ } else if (GRAPHICS_VER(rq->i915) >= 4) {
*batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
*batch++ = 0;
*batch++ = hws_address(hws, rq);
@@ -179,11 +179,11 @@ igt_spinner_create_request(struct igt_spinner *spin,
*batch++ = arbitration_command;
- if (GRAPHICS_VER(rq->engine->i915) >= 8)
+ if (GRAPHICS_VER(rq->i915) >= 8)
*batch++ = MI_BATCH_BUFFER_START | BIT(8) | 1;
- else if (IS_HASWELL(rq->engine->i915))
+ else if (IS_HASWELL(rq->i915))
*batch++ = MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW;
- else if (GRAPHICS_VER(rq->engine->i915) >= 6)
+ else if (GRAPHICS_VER(rq->i915) >= 6)
*batch++ = MI_BATCH_BUFFER_START;
else
*batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
@@ -201,7 +201,7 @@ igt_spinner_create_request(struct igt_spinner *spin,
}
flags = 0;
- if (GRAPHICS_VER(rq->engine->i915) <= 5)
+ if (GRAPHICS_VER(rq->i915) <= 5)
flags |= I915_DISPATCH_SECURE;
err = engine->emit_bb_start(rq, i915_vma_offset(vma), PAGE_SIZE, flags);
--
2.34.1
^ permalink raw reply related [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: use direct alias for i915 in requests (rev2)
2023-07-19 15:07 [Intel-gfx] [PATCH] drm/i915: use direct alias for i915 in requests Andrzej Hajda
` (4 preceding siblings ...)
2023-07-20 9:51 ` [Intel-gfx] [PATCH] " Nirmoy Das
@ 2023-07-20 16:54 ` Patchwork
2023-07-20 16:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (5 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-07-20 16:54 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: use direct alias for i915 in requests (rev2)
URL : https://patchwork.freedesktop.org/series/120991/
State : warning
== Summary ==
Error: dim checkpatch failed
b6ff0087160e drm/i915: use direct alias for i915 in requests
-:138: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants
#138: FILE: drivers/gpu/drm/i915/gt/intel_execlists_submission.c:2721:
+ GEM_BUG_ON(intel_vgpu_active(rq->i915));
-:160: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants
#160: FILE: drivers/gpu/drm/i915/gt/intel_migrate.c:378:
+ GEM_BUG_ON(GRAPHICS_VER(rq->i915) < 8);
total: 0 errors, 2 warnings, 0 checks, 310 lines checked
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: use direct alias for i915 in requests (rev2)
2023-07-19 15:07 [Intel-gfx] [PATCH] drm/i915: use direct alias for i915 in requests Andrzej Hajda
` (5 preceding siblings ...)
2023-07-20 16:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: use direct alias for i915 in requests (rev2) Patchwork
@ 2023-07-20 16:54 ` Patchwork
2023-07-20 17:17 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (4 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-07-20 16:54 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: use direct alias for i915 in requests (rev2)
URL : https://patchwork.freedesktop.org/series/120991/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: use direct alias for i915 in requests (rev2)
2023-07-19 15:07 [Intel-gfx] [PATCH] drm/i915: use direct alias for i915 in requests Andrzej Hajda
` (6 preceding siblings ...)
2023-07-20 16:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-07-20 17:17 ` Patchwork
2023-07-21 13:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: use direct alias for i915 in requests (rev3) Patchwork
` (3 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-07-20 17:17 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 12793 bytes --]
== Series Details ==
Series: drm/i915: use direct alias for i915 in requests (rev2)
URL : https://patchwork.freedesktop.org/series/120991/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13399 -> Patchwork_120991v2
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_120991v2 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_120991v2, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/index.html
Participating hosts (43 -> 43)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_120991v2:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@coherency:
- bat-jsl-3: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13399/bat-jsl-3/igt@i915_selftest@live@coherency.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-jsl-3/igt@i915_selftest@live@coherency.html
* igt@i915_selftest@live@hangcheck:
- bat-jsl-3: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13399/bat-jsl-3/igt@i915_selftest@live@hangcheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-jsl-3/igt@i915_selftest@live@hangcheck.html
* igt@kms_busy@basic:
- fi-kbl-soraka: NOTRUN -> [INCOMPLETE][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/fi-kbl-soraka/igt@kms_busy@basic.html
Known issues
------------
Here are the changes found in Patchwork_120991v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@read_all_entries:
- bat-mtlp-6: [PASS][6] -> [DMESG-WARN][7] ([i915#8937])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13399/bat-mtlp-6/igt@debugfs_test@read_all_entries.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-mtlp-6/igt@debugfs_test@read_all_entries.html
* igt@i915_pm_rpm@basic-rte:
- fi-skl-guc: [PASS][8] -> [FAIL][9] ([i915#7940]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13399/fi-skl-guc/igt@i915_pm_rpm@basic-rte.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/fi-skl-guc/igt@i915_pm_rpm@basic-rte.html
* igt@i915_pm_rpm@module-reload:
- fi-cfl-8700k: [PASS][10] -> [FAIL][11] ([i915#7940])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13399/fi-cfl-8700k/igt@i915_pm_rpm@module-reload.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/fi-cfl-8700k/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][12] -> [DMESG-FAIL][13] ([i915#5334])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13399/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
- fi-kbl-soraka: [PASS][14] -> [DMESG-FAIL][15] ([i915#5334] / [i915#7872])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13399/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@guc_multi_lrc:
- bat-mtlp-8: NOTRUN -> [DMESG-WARN][16] ([i915#8937]) +23 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-mtlp-8/igt@i915_selftest@live@guc_multi_lrc.html
* igt@i915_selftest@live@hangcheck:
- fi-skl-guc: [PASS][17] -> [DMESG-FAIL][18] ([i915#8723])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13399/fi-skl-guc/igt@i915_selftest@live@hangcheck.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/fi-skl-guc/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@migrate:
- bat-mtlp-8: NOTRUN -> [DMESG-WARN][19] ([i915#7699] / [i915#8504] / [i915#8937])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-mtlp-8/igt@i915_selftest@live@migrate.html
* igt@i915_selftest@live@mman:
- bat-rpls-1: [PASS][20] -> [TIMEOUT][21] ([i915#6794] / [i915#7392])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13399/bat-rpls-1/igt@i915_selftest@live@mman.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-rpls-1/igt@i915_selftest@live@mman.html
* igt@i915_selftest@live@slpc:
- bat-rpls-2: NOTRUN -> [DMESG-WARN][22] ([i915#6367])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-rpls-2/igt@i915_selftest@live@slpc.html
- bat-mtlp-8: NOTRUN -> [DMESG-WARN][23] ([i915#6367] / [i915#8937])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-mtlp-8/igt@i915_selftest@live@slpc.html
* igt@i915_suspend@basic-s2idle-without-i915:
- bat-rpls-1: NOTRUN -> [WARN][24] ([i915#8747])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-rpls-1/igt@i915_suspend@basic-s2idle-without-i915.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-mtlp-8: NOTRUN -> [SKIP][25] ([i915#6645])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-mtlp-8/igt@i915_suspend@basic-s3-without-i915.html
- bat-rpls-1: NOTRUN -> [ABORT][26] ([i915#6687] / [i915#7978] / [i915#8668])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-rpls-1/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-rpls-2: NOTRUN -> [SKIP][27] ([i915#7828])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-rpls-2/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
- bat-mtlp-8: NOTRUN -> [SKIP][28] ([i915#7828])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-mtlp-8/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc:
- bat-rpls-2: NOTRUN -> [SKIP][29] ([i915#1845])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-rpls-2/igt@kms_pipe_crc_basic@suspend-read-crc.html
* igt@kms_psr@primary_mmap_gtt:
- bat-rplp-1: NOTRUN -> [SKIP][30] ([i915#1072]) +2 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-rplp-1: NOTRUN -> [ABORT][31] ([i915#8260] / [i915#8668])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-rplp-1/igt@kms_setmode@basic-clone-single-crtc.html
#### Possible fixes ####
* igt@core_auth@basic-auth:
- bat-mtlp-6: [DMESG-WARN][32] ([i915#8937]) -> [PASS][33]
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13399/bat-mtlp-6/igt@core_auth@basic-auth.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-mtlp-6/igt@core_auth@basic-auth.html
* igt@i915_pm_rpm@module-reload:
- fi-rkl-11600: [FAIL][34] ([i915#7940]) -> [PASS][35]
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13399/fi-rkl-11600/igt@i915_pm_rpm@module-reload.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/fi-rkl-11600/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@requests:
- bat-rpls-2: [ABORT][36] ([i915#7913] / [i915#7982]) -> [PASS][37]
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13399/bat-rpls-2/igt@i915_selftest@live@requests.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-rpls-2/igt@i915_selftest@live@requests.html
* igt@prime_self_import@basic-with_fd_dup:
- fi-kbl-soraka: [INCOMPLETE][38] -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13399/fi-kbl-soraka/igt@prime_self_import@basic-with_fd_dup.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/fi-kbl-soraka/igt@prime_self_import@basic-with_fd_dup.html
#### Warnings ####
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-guc: [FAIL][40] ([i915#7940]) -> [FAIL][41] ([i915#8843])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13399/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
* igt@i915_selftest@live@gt_tlb:
- bat-mtlp-8: [DMESG-FAIL][42] -> [DMESG-WARN][43] ([i915#8937])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13399/bat-mtlp-8/igt@i915_selftest@live@gt_tlb.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-mtlp-8/igt@i915_selftest@live@gt_tlb.html
* igt@i915_selftest@live@requests:
- bat-mtlp-8: [ABORT][44] ([i915#7982]) -> [DMESG-WARN][45] ([i915#8937])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13399/bat-mtlp-8/igt@i915_selftest@live@requests.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-mtlp-8/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@slpc:
- bat-mtlp-6: [DMESG-WARN][46] ([i915#8937]) -> [DMESG-WARN][47] ([i915#6367] / [i915#8937])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13399/bat-mtlp-6/igt@i915_selftest@live@slpc.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-mtlp-6/igt@i915_selftest@live@slpc.html
* igt@i915_selftest@live@workarounds:
- bat-mtlp-8: [DMESG-FAIL][48] ([i915#6763]) -> [DMESG-WARN][49] ([i915#8937])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13399/bat-mtlp-8/igt@i915_selftest@live@workarounds.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-mtlp-8/igt@i915_selftest@live@workarounds.html
* igt@kms_psr@primary_page_flip:
- bat-rplp-1: [ABORT][50] ([i915#8860]) -> [SKIP][51] ([i915#1072])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13399/bat-rplp-1/igt@kms_psr@primary_page_flip.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/bat-rplp-1/igt@kms_psr@primary_page_flip.html
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6687]: https://gitlab.freedesktop.org/drm/intel/issues/6687
[i915#6763]: https://gitlab.freedesktop.org/drm/intel/issues/6763
[i915#6794]: https://gitlab.freedesktop.org/drm/intel/issues/6794
[i915#7392]: https://gitlab.freedesktop.org/drm/intel/issues/7392
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
[i915#7978]: https://gitlab.freedesktop.org/drm/intel/issues/7978
[i915#7982]: https://gitlab.freedesktop.org/drm/intel/issues/7982
[i915#8260]: https://gitlab.freedesktop.org/drm/intel/issues/8260
[i915#8504]: https://gitlab.freedesktop.org/drm/intel/issues/8504
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#8723]: https://gitlab.freedesktop.org/drm/intel/issues/8723
[i915#8747]: https://gitlab.freedesktop.org/drm/intel/issues/8747
[i915#8843]: https://gitlab.freedesktop.org/drm/intel/issues/8843
[i915#8860]: https://gitlab.freedesktop.org/drm/intel/issues/8860
[i915#8937]: https://gitlab.freedesktop.org/drm/intel/issues/8937
Build changes
-------------
* Linux: CI_DRM_13399 -> Patchwork_120991v2
CI-20190529: 20190529
CI_DRM_13399: fcafac400c8ed8c9fe9419e94a6cd2dc3bc87da1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7396: 8e84faf33c2cf3482c7dff814d256089bc03db5d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_120991v2: fcafac400c8ed8c9fe9419e94a6cd2dc3bc87da1 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
7b642a32ede1 drm/i915: use direct alias for i915 in requests
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v2/index.html
[-- Attachment #2: Type: text/html, Size: 15464 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: use direct alias for i915 in requests (rev3)
2023-07-19 15:07 [Intel-gfx] [PATCH] drm/i915: use direct alias for i915 in requests Andrzej Hajda
` (7 preceding siblings ...)
2023-07-20 17:17 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2023-07-21 13:05 ` Patchwork
2023-07-21 13:05 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
11 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-07-21 13:05 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: use direct alias for i915 in requests (rev3)
URL : https://patchwork.freedesktop.org/series/120991/
State : warning
== Summary ==
Error: dim checkpatch failed
441eb942f415 drm/i915: use direct alias for i915 in requests
-:138: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants
#138: FILE: drivers/gpu/drm/i915/gt/intel_execlists_submission.c:2721:
+ GEM_BUG_ON(intel_vgpu_active(rq->i915));
-:160: WARNING:AVOID_BUG: Do not crash the kernel unless it is absolutely unavoidable--use WARN_ON_ONCE() plus recovery code (if feasible) instead of BUG() or variants
#160: FILE: drivers/gpu/drm/i915/gt/intel_migrate.c:378:
+ GEM_BUG_ON(GRAPHICS_VER(rq->i915) < 8);
total: 0 errors, 2 warnings, 0 checks, 310 lines checked
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: use direct alias for i915 in requests (rev3)
2023-07-19 15:07 [Intel-gfx] [PATCH] drm/i915: use direct alias for i915 in requests Andrzej Hajda
` (8 preceding siblings ...)
2023-07-21 13:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: use direct alias for i915 in requests (rev3) Patchwork
@ 2023-07-21 13:05 ` Patchwork
2023-07-21 13:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-07-21 16:00 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
11 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-07-21 13:05 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: use direct alias for i915 in requests (rev3)
URL : https://patchwork.freedesktop.org/series/120991/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: use direct alias for i915 in requests (rev3)
2023-07-19 15:07 [Intel-gfx] [PATCH] drm/i915: use direct alias for i915 in requests Andrzej Hajda
` (9 preceding siblings ...)
2023-07-21 13:05 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-07-21 13:19 ` Patchwork
2023-07-21 16:00 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
11 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-07-21 13:19 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6249 bytes --]
== Series Details ==
Series: drm/i915: use direct alias for i915 in requests (rev3)
URL : https://patchwork.freedesktop.org/series/120991/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13404 -> Patchwork_120991v3
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/index.html
Participating hosts (42 -> 42)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in Patchwork_120991v3 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_pm:
- bat-rpls-2: [PASS][1] -> [DMESG-FAIL][2] ([i915#4258] / [i915#7913])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/bat-rpls-2/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@requests:
- bat-mtlp-8: [PASS][3] -> [DMESG-FAIL][4] ([i915#8497])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/bat-mtlp-8/igt@i915_selftest@live@requests.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/bat-mtlp-8/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@slpc:
- bat-mtlp-8: [PASS][5] -> [DMESG-WARN][6] ([i915#6367])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/bat-mtlp-8/igt@i915_selftest@live@slpc.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/bat-mtlp-8/igt@i915_selftest@live@slpc.html
* igt@kms_chamelium_hpd@common-hpd-after-suspend:
- bat-mtlp-8: NOTRUN -> [SKIP][7] ([i915#7828])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/bat-mtlp-8/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
- fi-bsw-n3050: NOTRUN -> [SKIP][8] ([fdo#109271])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/fi-bsw-n3050/igt@kms_chamelium_hpd@common-hpd-after-suspend.html
* igt@kms_psr@primary_mmap_gtt:
- bat-rplp-1: NOTRUN -> [ABORT][9] ([i915#8434] / [i915#8442] / [i915#8668])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/bat-rplp-1/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_psr@sprite_plane_onoff:
- bat-rplp-1: NOTRUN -> [SKIP][10] ([i915#1072])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/bat-rplp-1/igt@kms_psr@sprite_plane_onoff.html
#### Possible fixes ####
* igt@i915_pm_rpm@basic-rte:
- fi-skl-guc: [FAIL][11] ([i915#7940]) -> [PASS][12] +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/fi-skl-guc/igt@i915_pm_rpm@basic-rte.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/fi-skl-guc/igt@i915_pm_rpm@basic-rte.html
* igt@i915_selftest@live@execlists:
- fi-bsw-n3050: [ABORT][13] ([i915#7913]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/fi-bsw-n3050/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_mocs:
- bat-mtlp-6: [DMESG-FAIL][15] ([i915#7059]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/bat-mtlp-6/igt@i915_selftest@live@gt_mocs.html
#### Warnings ####
* igt@i915_pm_rpm@basic-pci-d3-state:
- fi-cfl-8700k: [FAIL][17] ([i915#7691]) -> [FAIL][18] ([i915#7940])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/fi-cfl-8700k/igt@i915_pm_rpm@basic-pci-d3-state.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/fi-cfl-8700k/igt@i915_pm_rpm@basic-pci-d3-state.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-mtlp-8: [ABORT][19] -> [SKIP][20] ([i915#6645])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/bat-mtlp-8/igt@i915_suspend@basic-s3-without-i915.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/bat-mtlp-8/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_psr@cursor_plane_move:
- bat-rplp-1: [ABORT][21] ([i915#8434] / [i915#8668]) -> [SKIP][22] ([i915#1072])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/bat-rplp-1/igt@kms_psr@cursor_plane_move.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/bat-rplp-1/igt@kms_psr@cursor_plane_move.html
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7059]: https://gitlab.freedesktop.org/drm/intel/issues/7059
[i915#7691]: https://gitlab.freedesktop.org/drm/intel/issues/7691
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913
[i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
[i915#8434]: https://gitlab.freedesktop.org/drm/intel/issues/8434
[i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
[i915#8497]: https://gitlab.freedesktop.org/drm/intel/issues/8497
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
Build changes
-------------
* Linux: CI_DRM_13404 -> Patchwork_120991v3
CI-20190529: 20190529
CI_DRM_13404: 526f3e5b744ee37c2fd643a2efec898a1f967d36 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7398: 602cdd3c87fad86cab8b15fe4242f2a119ce48df @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_120991v3: 526f3e5b744ee37c2fd643a2efec898a1f967d36 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
947a6cfe76a5 drm/i915: use direct alias for i915 in requests
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/index.html
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^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: use direct alias for i915 in requests (rev3)
2023-07-19 15:07 [Intel-gfx] [PATCH] drm/i915: use direct alias for i915 in requests Andrzej Hajda
` (10 preceding siblings ...)
2023-07-21 13:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-07-21 16:00 ` Patchwork
11 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2023-07-21 16:00 UTC (permalink / raw)
To: Andrzej Hajda; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 38327 bytes --]
== Series Details ==
Series: drm/i915: use direct alias for i915 in requests (rev3)
URL : https://patchwork.freedesktop.org/series/120991/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13404_full -> Patchwork_120991v3_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/index.html
Participating hosts (10 -> 9)
------------------------------
Missing (1): pig-kbl-iris
Known issues
------------
Here are the changes found in Patchwork_120991v3_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_barrier_race@remote-request@rcs0:
- shard-dg2: [PASS][1] -> [ABORT][2] ([i915#7461] / [i915#8211] / [i915#8234])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-dg2-5/igt@gem_barrier_race@remote-request@rcs0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg2-3/igt@gem_barrier_race@remote-request@rcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][3] -> [FAIL][4] ([i915#2846])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-glk8/igt@gem_exec_fair@basic-deadline.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-glk2/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-apl4/igt@gem_exec_fair@basic-none-solo@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-apl2/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace:
- shard-mtlp: NOTRUN -> [SKIP][7] ([i915#4473] / [i915#4771])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@gem_exec_fair@basic-pace.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-rkl: [PASS][8] -> [FAIL][9] ([i915#2842]) +2 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-rkl-2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-rkl-6/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_reloc@basic-cpu-active:
- shard-mtlp: NOTRUN -> [SKIP][10] ([i915#3281]) +2 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@gem_exec_reloc@basic-cpu-active.html
* igt@gem_exec_suspend@basic-s4-devices@lmem0:
- shard-dg2: [PASS][11] -> [ABORT][12] ([i915#7975] / [i915#8213])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-dg2-11/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg2-8/igt@gem_exec_suspend@basic-s4-devices@lmem0.html
* igt@gem_exec_whisper@basic-contexts-priority-all:
- shard-mtlp: [PASS][13] -> [ABORT][14] ([i915#8131])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-mtlp-3/igt@gem_exec_whisper@basic-contexts-priority-all.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-8/igt@gem_exec_whisper@basic-contexts-priority-all.html
* igt@gem_fenced_exec_thrash@no-spare-fences:
- shard-mtlp: NOTRUN -> [SKIP][15] ([i915#4860]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-8/igt@gem_fenced_exec_thrash@no-spare-fences.html
* igt@gem_gtt_cpu_tlb:
- shard-mtlp: NOTRUN -> [SKIP][16] ([i915#4077])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@gem_gtt_cpu_tlb.html
* igt@gem_partial_pwrite_pread@write-snoop:
- shard-mtlp: NOTRUN -> [SKIP][17] ([i915#3282])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@gem_partial_pwrite_pread@write-snoop.html
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-mtlp: NOTRUN -> [SKIP][18] ([i915#8428])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@gem_render_copy@linear-to-vebox-y-tiled.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-mtlp: NOTRUN -> [SKIP][19] ([i915#3297])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-8/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gen9_exec_parse@bb-start-param:
- shard-mtlp: NOTRUN -> [SKIP][20] ([i915#2856])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@gen9_exec_parse@bb-start-param.html
* igt@i915_pm_rpm@cursor-dpms:
- shard-tglu: [PASS][21] -> [FAIL][22] ([i915#7940])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-tglu-10/igt@i915_pm_rpm@cursor-dpms.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-tglu-9/igt@i915_pm_rpm@cursor-dpms.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- shard-rkl: [PASS][23] -> [SKIP][24] ([i915#1397]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-rkl-1/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-apl: [PASS][25] -> [DMESG-FAIL][26] ([i915#5334])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-apl2/igt@i915_selftest@live@gt_heartbeat.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-apl1/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_pm:
- shard-rkl: [PASS][27] -> [DMESG-FAIL][28] ([i915#4258])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-rkl-1/igt@i915_selftest@live@gt_pm.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-rkl-4/igt@i915_selftest@live@gt_pm.html
* igt@i915_selftest@live@migrate:
- shard-mtlp: [PASS][29] -> [DMESG-FAIL][30] ([i915#7699])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-mtlp-1/igt@i915_selftest@live@migrate.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-2/igt@i915_selftest@live@migrate.html
* igt@kms_async_flips@crc@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [FAIL][31] ([i915#8247]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-rkl-6/igt@kms_async_flips@crc@pipe-a-hdmi-a-2.html
* igt@kms_async_flips@test-cursor:
- shard-mtlp: NOTRUN -> [SKIP][32] ([i915#6229])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@kms_async_flips@test-cursor.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-mtlp: NOTRUN -> [SKIP][33] ([fdo#111615]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- shard-mtlp: NOTRUN -> [SKIP][34] ([i915#3886] / [i915#6095]) +2 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@kms_ccs@pipe-c-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-d-bad-pixel-format-yf_tiled_ccs:
- shard-mtlp: NOTRUN -> [SKIP][35] ([i915#6095]) +5 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@kms_ccs@pipe-d-bad-pixel-format-yf_tiled_ccs.html
* igt@kms_cdclk@mode-transition@pipe-d-dp-4:
- shard-dg2: NOTRUN -> [SKIP][36] ([i915#4087] / [i915#7213]) +3 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg2-11/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html
* igt@kms_chamelium_audio@hdmi-audio:
- shard-mtlp: NOTRUN -> [SKIP][37] ([i915#7828])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@kms_chamelium_audio@hdmi-audio.html
* igt@kms_content_protection@legacy:
- shard-dg2: NOTRUN -> [SKIP][38] ([i915#7118])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg2-1/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@cursor-rapid-movement-512x512:
- shard-mtlp: NOTRUN -> [SKIP][39] ([i915#3359])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@kms_cursor_crc@cursor-rapid-movement-512x512.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-glk: [PASS][40] -> [FAIL][41] ([i915#2346])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc:
- shard-dg2: NOTRUN -> [SKIP][42] ([i915#3555])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg2-1/igt@kms_dither@fb-8bpc-vs-panel-6bpc.html
* igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][43] ([i915#3804])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-rkl-7/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html
* igt@kms_fence_pin_leak:
- shard-mtlp: NOTRUN -> [SKIP][44] ([i915#4881])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@kms_fence_pin_leak.html
* igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible:
- shard-mtlp: NOTRUN -> [SKIP][45] ([i915#3637])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@kms_flip@2x-flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2:
- shard-glk: [PASS][46] -> [FAIL][47] ([i915#79])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-glk4/igt@kms_flip@2x-flip-vs-expired-vblank@ab-hdmi-a1-hdmi-a2.html
* igt@kms_flip@dpms-vs-vblank-race-interruptible@a-edp1:
- shard-mtlp: [PASS][48] -> [DMESG-WARN][49] ([i915#1982]) +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-mtlp-2/igt@kms_flip@dpms-vs-vblank-race-interruptible@a-edp1.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@kms_flip@dpms-vs-vblank-race-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@d-dp4:
- shard-dg2: NOTRUN -> [FAIL][50] ([fdo#103375])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg2-11/igt@kms_flip@flip-vs-suspend-interruptible@d-dp4.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode:
- shard-mtlp: NOTRUN -> [SKIP][51] ([i915#2672]) +1 similar issue
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-default-mode.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite:
- shard-dg2: [PASS][52] -> [FAIL][53] ([i915#6880]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-dg2-12/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg2-12/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack-mmap-gtt:
- shard-mtlp: NOTRUN -> [SKIP][54] ([i915#8708]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@kms_frontbuffer_tracking@fbcpsr-1p-indfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-pri-indfb-multidraw:
- shard-mtlp: NOTRUN -> [SKIP][55] ([i915#1825]) +2 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@kms_frontbuffer_tracking@psr-2p-pri-indfb-multidraw.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-rkl: NOTRUN -> [SKIP][56] ([i915#3555] / [i915#8228])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-rkl-6/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_plane_lowres@tiling-x@pipe-c-edp-1:
- shard-mtlp: NOTRUN -> [SKIP][57] ([i915#3582]) +3 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@kms_plane_lowres@tiling-x@pipe-c-edp-1.html
* igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][58] ([i915#5176]) +5 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-rkl-4/igt@kms_plane_scaling@plane-downscale-with-modifiers-factor-0-25@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-d-dp-4:
- shard-dg2: NOTRUN -> [SKIP][59] ([i915#5176]) +7 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg2-11/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-d-dp-4.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c-dp-2:
- shard-dg2: NOTRUN -> [SKIP][60] ([i915#5235]) +11 similar issues
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg2-12/igt@kms_plane_scaling@planes-downscale-factor-0-25-unity-scaling@pipe-c-dp-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b-vga-1:
- shard-snb: NOTRUN -> [SKIP][61] ([fdo#109271]) +84 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-snb4/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b-vga-1.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-hdmi-a-1:
- shard-rkl: NOTRUN -> [SKIP][62] ([i915#5235]) +5 similar issues
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-rkl-7/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-25@pipe-b-hdmi-a-1.html
* igt@kms_prime@d3hot:
- shard-apl: NOTRUN -> [SKIP][63] ([fdo#109271]) +9 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-apl6/igt@kms_prime@d3hot.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-mtlp: NOTRUN -> [SKIP][64] ([i915#4348])
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@kms_psr2_su@page_flip-nv12.html
* igt@sysfs_heartbeat_interval@nopreempt@ccs0:
- shard-mtlp: [PASS][65] -> [FAIL][66] ([i915#6015])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-mtlp-7/igt@sysfs_heartbeat_interval@nopreempt@ccs0.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-4/igt@sysfs_heartbeat_interval@nopreempt@ccs0.html
* igt@v3d/v3d_submit_csd@bad-bo:
- shard-mtlp: NOTRUN -> [SKIP][67] ([i915#2575]) +1 similar issue
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@v3d/v3d_submit_csd@bad-bo.html
* igt@vc4/vc4_dmabuf_poll@poll-write-waits-until-write-done:
- shard-mtlp: NOTRUN -> [SKIP][68] ([i915#7711])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@vc4/vc4_dmabuf_poll@poll-write-waits-until-write-done.html
#### Possible fixes ####
* igt@drm_fdinfo@most-busy-check-all@rcs0:
- shard-rkl: [FAIL][69] ([i915#7742]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-rkl-2/igt@drm_fdinfo@most-busy-check-all@rcs0.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-rkl-2/igt@drm_fdinfo@most-busy-check-all@rcs0.html
* igt@gem_ctx_exec@basic-nohangcheck:
- shard-rkl: [FAIL][71] ([i915#6268]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-rkl-2/igt@gem_ctx_exec@basic-nohangcheck.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-rkl-2/igt@gem_ctx_exec@basic-nohangcheck.html
* igt@gem_eio@hibernate:
- shard-dg2: [ABORT][73] ([i915#7975] / [i915#8213]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-dg2-10/igt@gem_eio@hibernate.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg2-11/igt@gem_eio@hibernate.html
* igt@gem_eio@kms:
- shard-dg2: [INCOMPLETE][75] ([i915#7892]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-dg2-7/igt@gem_eio@kms.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg2-6/igt@gem_eio@kms.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglu: [FAIL][77] ([i915#2842]) -> [PASS][78]
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-tglu-6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-tglu-2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-rkl: [FAIL][79] ([i915#2842]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-rkl-2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-rkl-6/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-glk: [FAIL][81] ([i915#2842]) -> [PASS][82]
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-glk9/igt@gem_exec_fair@basic-pace@rcs0.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-glk8/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg2: [TIMEOUT][83] ([i915#5493]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-dg2-10/igt@gem_lmem_swapping@smem-oom@lmem0.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg2-2/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_softpin@evict-active:
- {shard-dg1}: [ABORT][85] ([i915#4983]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-dg1-19/igt@gem_softpin@evict-active.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg1-15/igt@gem_softpin@evict-active.html
* igt@i915_pipe_stress@stress-xrgb8888-untiled:
- shard-mtlp: [FAIL][87] ([i915#8691]) -> [PASS][88]
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-mtlp-5/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
* igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a:
- shard-rkl: [SKIP][89] ([i915#1937]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-rkl-1/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-rkl-7/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-hdmi-a.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-glk: [DMESG-WARN][91] ([i915#118]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-glk8/igt@i915_pm_rc6_residency@rc6-fence.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-glk1/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle@bcs0:
- {shard-dg1}: [FAIL][93] ([i915#3591]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-dg1-19/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html
* igt@i915_pm_rpm@gem-execbuf-stress@lmem0:
- {shard-dg1}: [FAIL][95] ([i915#7940]) -> [PASS][96]
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-dg1-16/igt@i915_pm_rpm@gem-execbuf-stress@lmem0.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg1-12/igt@i915_pm_rpm@gem-execbuf-stress@lmem0.html
* igt@i915_pm_rpm@modeset-lpsp:
- shard-rkl: [SKIP][97] ([i915#1397]) -> [PASS][98]
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-rkl-1/igt@i915_pm_rpm@modeset-lpsp.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-rkl-7/igt@i915_pm_rpm@modeset-lpsp.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- {shard-dg1}: [SKIP][99] ([i915#1397]) -> [PASS][100]
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-dg1-19/igt@i915_pm_rpm@modeset-non-lpsp.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg1-15/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress:
- shard-dg2: [SKIP][101] ([i915#1397]) -> [PASS][102] +1 similar issue
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-dg2-10/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg2-2/igt@i915_pm_rpm@modeset-non-lpsp-stress.html
* igt@i915_selftest@live@client:
- shard-snb: [ABORT][103] -> [PASS][104]
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-snb7/igt@i915_selftest@live@client.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-snb1/igt@i915_selftest@live@client.html
* igt@i915_selftest@live@slpc:
- shard-mtlp: [DMESG-WARN][105] ([i915#6367]) -> [PASS][106]
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-mtlp-1/igt@i915_selftest@live@slpc.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-2/igt@i915_selftest@live@slpc.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1:
- shard-mtlp: [FAIL][107] ([i915#2521]) -> [PASS][108]
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-mtlp-5/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-mtlp: [FAIL][109] ([i915#5138]) -> [PASS][110]
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-8/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-mtlp: [FAIL][111] ([i915#3743]) -> [PASS][112]
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-mtlp-6/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_ccs@pipe-b-crc-primary-basic-4_tiled_dg2_mc_ccs:
- shard-dg2: [FAIL][113] -> [PASS][114]
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-dg2-11/igt@kms_ccs@pipe-b-crc-primary-basic-4_tiled_dg2_mc_ccs.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg2-7/igt@kms_ccs@pipe-b-crc-primary-basic-4_tiled_dg2_mc_ccs.html
* igt@kms_cursor_legacy@cursor-vs-flip-legacy:
- shard-mtlp: [FAIL][115] ([i915#8248]) -> [PASS][116]
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-mtlp-2/igt@kms_cursor_legacy@cursor-vs-flip-legacy.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-3/igt@kms_cursor_legacy@cursor-vs-flip-legacy.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [FAIL][117] ([i915#2346]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
- shard-apl: [FAIL][119] ([i915#2346]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
- shard-dg2: [FAIL][121] ([i915#6880]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-dg2-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg2-12/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: [ABORT][123] ([i915#180] / [i915#8213]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-apl6/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-apl6/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@sysfs_heartbeat_interval@nopreempt@vcs0:
- shard-mtlp: [FAIL][125] ([i915#6015]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-mtlp-7/igt@sysfs_heartbeat_interval@nopreempt@vcs0.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-4/igt@sysfs_heartbeat_interval@nopreempt@vcs0.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-idle@bcs0:
- shard-tglu: [WARN][127] ([i915#2681]) -> [FAIL][128] ([i915#2681] / [i915#3591])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-tglu-7/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-tglu-7/igt@i915_pm_rc6_residency@rc6-idle@bcs0.html
* igt@i915_pm_rc6_residency@rc6-idle@vecs0:
- shard-tglu: [FAIL][129] ([i915#2681] / [i915#3591]) -> [WARN][130] ([i915#2681])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-tglu-7/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-tglu-7/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
* igt@kms_content_protection@content_type_change:
- shard-dg2: [SKIP][131] ([i915#7118]) -> [SKIP][132] ([i915#7118] / [i915#7162])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-dg2-10/igt@kms_content_protection@content_type_change.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg2-11/igt@kms_content_protection@content_type_change.html
* igt@kms_content_protection@type1:
- shard-dg2: [SKIP][133] ([i915#7118] / [i915#7162]) -> [SKIP][134] ([i915#7118])
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-dg2-12/igt@kms_content_protection@type1.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg2-3/igt@kms_content_protection@type1.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-rkl: [SKIP][135] ([i915#3955]) -> [SKIP][136] ([fdo#110189] / [i915#3955]) +1 similar issue
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-rkl-7/igt@kms_fbcon_fbt@psr-suspend.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-rkl-1/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-rkl: [SKIP][137] ([fdo#109285] / [i915#4098]) -> [SKIP][138] ([fdo#109285])
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-rkl-2/igt@kms_force_connector_basic@force-load-detect.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-rkl-6/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_multipipe_modeset@basic-max-pipe-crc-check:
- shard-rkl: [SKIP][139] ([i915#4816]) -> [SKIP][140] ([i915#4070] / [i915#4816])
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-rkl-4/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-rkl-1/igt@kms_multipipe_modeset@basic-max-pipe-crc-check.html
* igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem:
- shard-dg2: [CRASH][141] ([i915#7331]) -> [INCOMPLETE][142] ([i915#5493])
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-dg2-1/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-dg2-10/igt@prime_mmap@test_aperture_limit@test_aperture_limit-smem.html
* igt@sysfs_preempt_timeout@timeout@vecs0:
- shard-mtlp: [ABORT][143] ([i915#8521]) -> [TIMEOUT][144] ([i915#7947])
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13404/shard-mtlp-2/igt@sysfs_preempt_timeout@timeout@vecs0.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/shard-mtlp-7/igt@sysfs_preempt_timeout@timeout@vecs0.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3582]: https://gitlab.freedesktop.org/drm/intel/issues/3582
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3804]: https://gitlab.freedesktop.org/drm/intel/issues/3804
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4258]: https://gitlab.freedesktop.org/drm/intel/issues/4258
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4348]: https://gitlab.freedesktop.org/drm/intel/issues/4348
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4423]: https://gitlab.freedesktop.org/drm/intel/issues/4423
[i915#4473]: https://gitlab.freedesktop.org/drm/intel/issues/4473
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#6015]: https://gitlab.freedesktop.org/drm/intel/issues/6015
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6229]: https://gitlab.freedesktop.org/drm/intel/issues/6229
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6880]: https://gitlab.freedesktop.org/drm/intel/issues/6880
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
[i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
[i915#7331]: https://gitlab.freedesktop.org/drm/intel/issues/7331
[i915#7461]: https://gitlab.freedesktop.org/drm/intel/issues/7461
[i915#7691]: https://gitlab.freedesktop.org/drm/intel/issues/7691
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7892]: https://gitlab.freedesktop.org/drm/intel/issues/7892
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#7940]: https://gitlab.freedesktop.org/drm/intel/issues/7940
[i915#7947]: https://gitlab.freedesktop.org/drm/intel/issues/7947
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8131]: https://gitlab.freedesktop.org/drm/intel/issues/8131
[i915#8211]: https://gitlab.freedesktop.org/drm/intel/issues/8211
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8234]: https://gitlab.freedesktop.org/drm/intel/issues/8234
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8248]: https://gitlab.freedesktop.org/drm/intel/issues/8248
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8428]: https://gitlab.freedesktop.org/drm/intel/issues/8428
[i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
[i915#8521]: https://gitlab.freedesktop.org/drm/intel/issues/8521
[i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
[i915#8691]: https://gitlab.freedesktop.org/drm/intel/issues/8691
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8812]: https://gitlab.freedesktop.org/drm/intel/issues/8812
Build changes
-------------
* Linux: CI_DRM_13404 -> Patchwork_120991v3
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_13404: 526f3e5b744ee37c2fd643a2efec898a1f967d36 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7398: 602cdd3c87fad86cab8b15fe4242f2a119ce48df @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_120991v3: 526f3e5b744ee37c2fd643a2efec898a1f967d36 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_120991v3/index.html
[-- Attachment #2: Type: text/html, Size: 41473 bytes --]
^ permalink raw reply [flat|nested] 17+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915: use direct alias for i915 in requests
2023-07-20 11:30 ` [Intel-gfx] [PATCH v2] " Andrzej Hajda
@ 2023-07-24 15:29 ` Andrzej Hajda
0 siblings, 0 replies; 17+ messages in thread
From: Andrzej Hajda @ 2023-07-24 15:29 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson, Nirmoy Das
On 20.07.2023 13:30, Andrzej Hajda wrote:
> i915_request contains direct alias to i915, there is no point to go via
> rq->engine->i915.
>
> v2: added missing rq.i915 initialization in measure_breadcrumb_dw.
>
> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Acked-by: Nirmoy Das <nirmoy.das@intel.com>
Pushed to drm-intel-gt-next, thx.
Regards
Andrzej
> ---
> drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c | 4 ++--
> drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/gen8_engine_cs.c | 18 +++++++++---------
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 1 +
> .../drm/i915/gt/intel_execlists_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_migrate.c | 10 +++++-----
> .../gpu/drm/i915/gt/intel_ring_submission.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 4 ++--
> drivers/gpu/drm/i915/gt/selftest_engine_cs.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_mocs.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_rc6.c | 2 +-
> drivers/gpu/drm/i915/gt/selftest_timeline.c | 4 ++--
> drivers/gpu/drm/i915/gvt/scheduler.c | 2 +-
> drivers/gpu/drm/i915/i915_perf.c | 2 +-
> drivers/gpu/drm/i915/i915_request.c | 2 +-
> drivers/gpu/drm/i915/i915_trace.h | 10 +++++-----
> drivers/gpu/drm/i915/selftests/i915_perf.c | 2 +-
> drivers/gpu/drm/i915/selftests/igt_spinner.c | 14 +++++++-------
> 18 files changed, 43 insertions(+), 42 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index d3208a32561442..5a687a3686bd53 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -2229,8 +2229,8 @@ static int i915_reset_gen7_sol_offsets(struct i915_request *rq)
> u32 *cs;
> int i;
>
> - if (GRAPHICS_VER(rq->engine->i915) != 7 || rq->engine->id != RCS0) {
> - drm_dbg(&rq->engine->i915->drm, "sol reset is gen7/rcs only\n");
> + if (GRAPHICS_VER(rq->i915) != 7 || rq->engine->id != RCS0) {
> + drm_dbg(&rq->i915->drm, "sol reset is gen7/rcs only\n");
> return -EINVAL;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> index 1c82caf525c346..8fe0499308ffe5 100644
> --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c
> @@ -76,7 +76,7 @@ int gen4_emit_flush_rcs(struct i915_request *rq, u32 mode)
> cmd = MI_FLUSH;
> if (mode & EMIT_INVALIDATE) {
> cmd |= MI_EXE_FLUSH;
> - if (IS_G4X(rq->engine->i915) || GRAPHICS_VER(rq->engine->i915) == 5)
> + if (IS_G4X(rq->i915) || GRAPHICS_VER(rq->i915) == 5)
> cmd |= MI_INVALIDATE_ISP;
> }
>
> diff --git a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> index 23857cc08eca1f..3ba20ea030e8d1 100644
> --- a/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/gen8_engine_cs.c
> @@ -39,11 +39,11 @@ int gen8_emit_flush_rcs(struct i915_request *rq, u32 mode)
> * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL
> * pipe control.
> */
> - if (GRAPHICS_VER(rq->engine->i915) == 9)
> + if (GRAPHICS_VER(rq->i915) == 9)
> vf_flush_wa = true;
>
> /* WaForGAMHang:kbl */
> - if (IS_KBL_GRAPHICS_STEP(rq->engine->i915, 0, STEP_C0))
> + if (IS_KBL_GRAPHICS_STEP(rq->i915, 0, STEP_C0))
> dc_flush_wa = true;
> }
>
> @@ -180,8 +180,8 @@ u32 *gen12_emit_aux_table_inv(struct intel_gt *gt, u32 *cs, const i915_reg_t inv
> static int mtl_dummy_pipe_control(struct i915_request *rq)
> {
> /* Wa_14016712196 */
> - if (IS_MTL_GRAPHICS_STEP(rq->engine->i915, M, STEP_A0, STEP_B0) ||
> - IS_MTL_GRAPHICS_STEP(rq->engine->i915, P, STEP_A0, STEP_B0)) {
> + if (IS_MTL_GRAPHICS_STEP(rq->i915, M, STEP_A0, STEP_B0) ||
> + IS_MTL_GRAPHICS_STEP(rq->i915, P, STEP_A0, STEP_B0)) {
> u32 *cs;
>
> /* dummy PIPE_CONTROL + depth flush */
> @@ -267,7 +267,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
> else if (engine->class == COMPUTE_CLASS)
> flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
>
> - if (!HAS_FLAT_CCS(rq->engine->i915))
> + if (!HAS_FLAT_CCS(rq->i915))
> count = 8 + 4;
> else
> count = 8;
> @@ -285,7 +285,7 @@ int gen12_emit_flush_rcs(struct i915_request *rq, u32 mode)
>
> cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
>
> - if (!HAS_FLAT_CCS(rq->engine->i915)) {
> + if (!HAS_FLAT_CCS(rq->i915)) {
> /* hsdes: 1809175790 */
> cs = gen12_emit_aux_table_inv(rq->engine->gt,
> cs, GEN12_GFX_CCS_AUX_NV);
> @@ -307,7 +307,7 @@ int gen12_emit_flush_xcs(struct i915_request *rq, u32 mode)
> if (mode & EMIT_INVALIDATE) {
> cmd += 2;
>
> - if (!HAS_FLAT_CCS(rq->engine->i915) &&
> + if (!HAS_FLAT_CCS(rq->i915) &&
> (rq->engine->class == VIDEO_DECODE_CLASS ||
> rq->engine->class == VIDEO_ENHANCEMENT_CLASS)) {
> aux_inv = rq->engine->mask &
> @@ -754,7 +754,7 @@ u32 *gen12_emit_fini_breadcrumb_xcs(struct i915_request *rq, u32 *cs)
>
> u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> {
> - struct drm_i915_private *i915 = rq->engine->i915;
> + struct drm_i915_private *i915 = rq->i915;
> u32 flags = (PIPE_CONTROL_CS_STALL |
> PIPE_CONTROL_TLB_INVALIDATE |
> PIPE_CONTROL_TILE_CACHE_FLUSH |
> @@ -775,7 +775,7 @@ u32 *gen12_emit_fini_breadcrumb_rcs(struct i915_request *rq, u32 *cs)
> /* Wa_1409600907 */
> flags |= PIPE_CONTROL_DEPTH_STALL;
>
> - if (!HAS_3D_PIPELINE(rq->engine->i915))
> + if (!HAS_3D_PIPELINE(rq->i915))
> flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS;
> else if (rq->engine->class == COMPUTE_CLASS)
> flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS;
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> index 0aff5bb13c538e..ee15486fed0daa 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
> @@ -1333,6 +1333,7 @@ static int measure_breadcrumb_dw(struct intel_context *ce)
> if (!frame)
> return -ENOMEM;
>
> + frame->rq.i915 = engine->i915;
> frame->rq.engine = engine;
> frame->rq.context = ce;
> rcu_assign_pointer(frame->rq.timeline, ce->timeline);
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index d85b5a6d981f99..8a641bcf777cb4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2718,7 +2718,7 @@ static int emit_pdps(struct i915_request *rq)
> int err, i;
> u32 *cs;
>
> - GEM_BUG_ON(intel_vgpu_active(rq->engine->i915));
> + GEM_BUG_ON(intel_vgpu_active(rq->i915));
>
> /*
> * Beware ye of the dragons, this sequence is magic!
> diff --git a/drivers/gpu/drm/i915/gt/intel_migrate.c b/drivers/gpu/drm/i915/gt/intel_migrate.c
> index 6023288b0e2dd5..576e5ef0289ba5 100644
> --- a/drivers/gpu/drm/i915/gt/intel_migrate.c
> +++ b/drivers/gpu/drm/i915/gt/intel_migrate.c
> @@ -366,7 +366,7 @@ static int emit_pte(struct i915_request *rq,
> u64 offset,
> int length)
> {
> - bool has_64K_pages = HAS_64K_PAGES(rq->engine->i915);
> + bool has_64K_pages = HAS_64K_PAGES(rq->i915);
> const u64 encode = rq->context->vm->pte_encode(0, pat_index,
> is_lmem ? PTE_LM : 0);
> struct intel_ring *ring = rq->ring;
> @@ -375,7 +375,7 @@ static int emit_pte(struct i915_request *rq,
> u32 page_size;
> u32 *hdr, *cs;
>
> - GEM_BUG_ON(GRAPHICS_VER(rq->engine->i915) < 8);
> + GEM_BUG_ON(GRAPHICS_VER(rq->i915) < 8);
>
> page_size = I915_GTT_PAGE_SIZE;
> dword_length = 0x400;
> @@ -531,7 +531,7 @@ static int emit_copy_ccs(struct i915_request *rq,
> u32 dst_offset, u8 dst_access,
> u32 src_offset, u8 src_access, int size)
> {
> - struct drm_i915_private *i915 = rq->engine->i915;
> + struct drm_i915_private *i915 = rq->i915;
> int mocs = rq->engine->gt->mocs.uc_index << 1;
> u32 num_ccs_blks;
> u32 *cs;
> @@ -581,7 +581,7 @@ static int emit_copy_ccs(struct i915_request *rq,
> static int emit_copy(struct i915_request *rq,
> u32 dst_offset, u32 src_offset, int size)
> {
> - const int ver = GRAPHICS_VER(rq->engine->i915);
> + const int ver = GRAPHICS_VER(rq->i915);
> u32 instance = rq->engine->instance;
> u32 *cs;
>
> @@ -917,7 +917,7 @@ intel_context_migrate_copy(struct intel_context *ce,
> static int emit_clear(struct i915_request *rq, u32 offset, int size,
> u32 value, bool is_lmem)
> {
> - struct drm_i915_private *i915 = rq->engine->i915;
> + struct drm_i915_private *i915 = rq->i915;
> int mocs = rq->engine->gt->mocs.uc_index << 1;
> const int ver = GRAPHICS_VER(i915);
> int ring_sz;
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 3fd795c3263fd2..92085ffd23de0e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -805,7 +805,7 @@ static int mi_set_context(struct i915_request *rq,
> static int remap_l3_slice(struct i915_request *rq, int slice)
> {
> #define L3LOG_DW (GEN7_L3LOG_SIZE / sizeof(u32))
> - u32 *cs, *remap_info = rq->engine->i915->l3_parity.remap_info[slice];
> + u32 *cs, *remap_info = rq->i915->l3_parity.remap_info[slice];
> int i;
>
> if (!remap_info)
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index b177c588698b08..589d009032fcd3 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -3249,7 +3249,7 @@ wa_list_srm(struct i915_request *rq,
> const struct i915_wa_list *wal,
> struct i915_vma *vma)
> {
> - struct drm_i915_private *i915 = rq->engine->i915;
> + struct drm_i915_private *i915 = rq->i915;
> unsigned int i, count = 0;
> const struct i915_wa *wa;
> u32 srm, *cs;
> @@ -3348,7 +3348,7 @@ static int engine_wa_list_verify(struct intel_context *ce,
>
> err = 0;
> for (i = 0, wa = wal->list; i < wal->count; i++, wa++) {
> - if (mcr_range(rq->engine->i915, i915_mmio_reg_offset(wa->reg)))
> + if (mcr_range(rq->i915, i915_mmio_reg_offset(wa->reg)))
> continue;
>
> if (!wa_verify(wal->gt, wa, results[i], wal->name, from))
> diff --git a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> index 78cdfc6f315f2a..86cecf7a110540 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_engine_cs.c
> @@ -62,7 +62,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
> return PTR_ERR(cs);
>
> cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
> + if (GRAPHICS_VER(rq->i915) >= 8)
> cmd++;
> *cs++ = cmd;
> *cs++ = i915_mmio_reg_offset(timestamp_reg(rq->engine));
> diff --git a/drivers/gpu/drm/i915/gt/selftest_mocs.c b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> index a8446ab825012f..d73e438fb85fab 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_mocs.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_mocs.c
> @@ -137,7 +137,7 @@ static int read_mocs_table(struct i915_request *rq,
> if (!table)
> return 0;
>
> - if (HAS_GLOBAL_MOCS_REGISTERS(rq->engine->i915))
> + if (HAS_GLOBAL_MOCS_REGISTERS(rq->i915))
> addr = global_mocs_offset() + gt->uncore->gsi_offset;
> else
> addr = mocs_offset(rq->engine);
> diff --git a/drivers/gpu/drm/i915/gt/selftest_rc6.c b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> index 2ceeadecc639cc..a7189c2d660cc5 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_rc6.c
> @@ -140,7 +140,7 @@ static const u32 *__live_rc6_ctx(struct intel_context *ce)
> }
>
> cmd = MI_STORE_REGISTER_MEM | MI_USE_GGTT;
> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
> + if (GRAPHICS_VER(rq->i915) >= 8)
> cmd++;
>
> *cs++ = cmd;
> diff --git a/drivers/gpu/drm/i915/gt/selftest_timeline.c b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> index 39c3ec12df1abb..fa36cf920bdee9 100644
> --- a/drivers/gpu/drm/i915/gt/selftest_timeline.c
> +++ b/drivers/gpu/drm/i915/gt/selftest_timeline.c
> @@ -459,12 +459,12 @@ static int emit_ggtt_store_dw(struct i915_request *rq, u32 addr, u32 value)
> if (IS_ERR(cs))
> return PTR_ERR(cs);
>
> - if (GRAPHICS_VER(rq->engine->i915) >= 8) {
> + if (GRAPHICS_VER(rq->i915) >= 8) {
> *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> *cs++ = addr;
> *cs++ = 0;
> *cs++ = value;
> - } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
> + } else if (GRAPHICS_VER(rq->i915) >= 4) {
> *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> *cs++ = 0;
> *cs++ = addr;
> diff --git a/drivers/gpu/drm/i915/gvt/scheduler.c b/drivers/gpu/drm/i915/gvt/scheduler.c
> index f4055804aad1fe..a5c8005ec484c3 100644
> --- a/drivers/gpu/drm/i915/gvt/scheduler.c
> +++ b/drivers/gpu/drm/i915/gvt/scheduler.c
> @@ -974,7 +974,7 @@ static void update_guest_context(struct intel_vgpu_workload *workload)
> context_page_num = rq->engine->context_size;
> context_page_num = context_page_num >> PAGE_SHIFT;
>
> - if (IS_BROADWELL(rq->engine->i915) && rq->engine->id == RCS0)
> + if (IS_BROADWELL(rq->i915) && rq->engine->id == RCS0)
> context_page_num = 19;
>
> context_base = (void *) ctx->lrc_reg_state -
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 49c6f1ff11284f..04bc1f4a111504 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1319,7 +1319,7 @@ __store_reg_to_mem(struct i915_request *rq, i915_reg_t reg, u32 ggtt_offset)
> u32 *cs, cmd;
>
> cmd = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
> + if (GRAPHICS_VER(rq->i915) >= 8)
> cmd++;
>
> cs = intel_ring_begin(rq, 4);
> diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c
> index c5fe199b046d01..9d83f064456cd9 100644
> --- a/drivers/gpu/drm/i915/i915_request.c
> +++ b/drivers/gpu/drm/i915/i915_request.c
> @@ -1341,7 +1341,7 @@ __i915_request_await_external(struct i915_request *rq, struct dma_fence *fence)
> {
> mark_external(rq);
> return i915_sw_fence_await_dma_fence(&rq->submit, fence,
> - i915_fence_context_timeout(rq->engine->i915,
> + i915_fence_context_timeout(rq->i915,
> fence->context),
> I915_FENCE_GFP);
> }
> diff --git a/drivers/gpu/drm/i915/i915_trace.h b/drivers/gpu/drm/i915/i915_trace.h
> index f6f9228a135185..ce1cbee1b39dd0 100644
> --- a/drivers/gpu/drm/i915/i915_trace.h
> +++ b/drivers/gpu/drm/i915/i915_trace.h
> @@ -277,7 +277,7 @@ TRACE_EVENT(i915_request_queue,
> ),
>
> TP_fast_assign(
> - __entry->dev = rq->engine->i915->drm.primary->index;
> + __entry->dev = rq->i915->drm.primary->index;
> __entry->class = rq->engine->uabi_class;
> __entry->instance = rq->engine->uabi_instance;
> __entry->ctx = rq->fence.context;
> @@ -304,7 +304,7 @@ DECLARE_EVENT_CLASS(i915_request,
> ),
>
> TP_fast_assign(
> - __entry->dev = rq->engine->i915->drm.primary->index;
> + __entry->dev = rq->i915->drm.primary->index;
> __entry->class = rq->engine->uabi_class;
> __entry->instance = rq->engine->uabi_instance;
> __entry->ctx = rq->fence.context;
> @@ -353,7 +353,7 @@ TRACE_EVENT(i915_request_in,
> ),
>
> TP_fast_assign(
> - __entry->dev = rq->engine->i915->drm.primary->index;
> + __entry->dev = rq->i915->drm.primary->index;
> __entry->class = rq->engine->uabi_class;
> __entry->instance = rq->engine->uabi_instance;
> __entry->ctx = rq->fence.context;
> @@ -382,7 +382,7 @@ TRACE_EVENT(i915_request_out,
> ),
>
> TP_fast_assign(
> - __entry->dev = rq->engine->i915->drm.primary->index;
> + __entry->dev = rq->i915->drm.primary->index;
> __entry->class = rq->engine->uabi_class;
> __entry->instance = rq->engine->uabi_instance;
> __entry->ctx = rq->fence.context;
> @@ -623,7 +623,7 @@ TRACE_EVENT(i915_request_wait_begin,
> * less desirable.
> */
> TP_fast_assign(
> - __entry->dev = rq->engine->i915->drm.primary->index;
> + __entry->dev = rq->i915->drm.primary->index;
> __entry->class = rq->engine->uabi_class;
> __entry->instance = rq->engine->uabi_instance;
> __entry->ctx = rq->fence.context;
> diff --git a/drivers/gpu/drm/i915/selftests/i915_perf.c b/drivers/gpu/drm/i915/selftests/i915_perf.c
> index d4608b220123ce..403134a7acec30 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_perf.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_perf.c
> @@ -168,7 +168,7 @@ static int write_timestamp(struct i915_request *rq, int slot)
> return PTR_ERR(cs);
>
> len = 5;
> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
> + if (GRAPHICS_VER(rq->i915) >= 8)
> len++;
>
> *cs++ = GFX_OP_PIPE_CONTROL(len);
> diff --git a/drivers/gpu/drm/i915/selftests/igt_spinner.c b/drivers/gpu/drm/i915/selftests/igt_spinner.c
> index 618d9386d55494..3c5e0952f1b81b 100644
> --- a/drivers/gpu/drm/i915/selftests/igt_spinner.c
> +++ b/drivers/gpu/drm/i915/selftests/igt_spinner.c
> @@ -159,15 +159,15 @@ igt_spinner_create_request(struct igt_spinner *spin,
>
> batch = spin->batch;
>
> - if (GRAPHICS_VER(rq->engine->i915) >= 8) {
> + if (GRAPHICS_VER(rq->i915) >= 8) {
> *batch++ = MI_STORE_DWORD_IMM_GEN4;
> *batch++ = lower_32_bits(hws_address(hws, rq));
> *batch++ = upper_32_bits(hws_address(hws, rq));
> - } else if (GRAPHICS_VER(rq->engine->i915) >= 6) {
> + } else if (GRAPHICS_VER(rq->i915) >= 6) {
> *batch++ = MI_STORE_DWORD_IMM_GEN4;
> *batch++ = 0;
> *batch++ = hws_address(hws, rq);
> - } else if (GRAPHICS_VER(rq->engine->i915) >= 4) {
> + } else if (GRAPHICS_VER(rq->i915) >= 4) {
> *batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
> *batch++ = 0;
> *batch++ = hws_address(hws, rq);
> @@ -179,11 +179,11 @@ igt_spinner_create_request(struct igt_spinner *spin,
>
> *batch++ = arbitration_command;
>
> - if (GRAPHICS_VER(rq->engine->i915) >= 8)
> + if (GRAPHICS_VER(rq->i915) >= 8)
> *batch++ = MI_BATCH_BUFFER_START | BIT(8) | 1;
> - else if (IS_HASWELL(rq->engine->i915))
> + else if (IS_HASWELL(rq->i915))
> *batch++ = MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW;
> - else if (GRAPHICS_VER(rq->engine->i915) >= 6)
> + else if (GRAPHICS_VER(rq->i915) >= 6)
> *batch++ = MI_BATCH_BUFFER_START;
> else
> *batch++ = MI_BATCH_BUFFER_START | MI_BATCH_GTT;
> @@ -201,7 +201,7 @@ igt_spinner_create_request(struct igt_spinner *spin,
> }
>
> flags = 0;
> - if (GRAPHICS_VER(rq->engine->i915) <= 5)
> + if (GRAPHICS_VER(rq->i915) <= 5)
> flags |= I915_DISPATCH_SECURE;
> err = engine->emit_bb_start(rq, i915_vma_offset(vma), PAGE_SIZE, flags);
>
^ permalink raw reply [flat|nested] 17+ messages in thread
end of thread, other threads:[~2023-07-24 15:29 UTC | newest]
Thread overview: 17+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-07-19 15:07 [Intel-gfx] [PATCH] drm/i915: use direct alias for i915 in requests Andrzej Hajda
2023-07-19 19:10 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2023-07-19 19:10 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-07-19 19:29 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-07-20 9:46 ` [Intel-gfx] [PATCH] " Tvrtko Ursulin
2023-07-20 10:07 ` Tvrtko Ursulin
2023-07-20 10:48 ` Andrzej Hajda
2023-07-20 11:30 ` [Intel-gfx] [PATCH v2] " Andrzej Hajda
2023-07-24 15:29 ` Andrzej Hajda
2023-07-20 9:51 ` [Intel-gfx] [PATCH] " Nirmoy Das
2023-07-20 16:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: use direct alias for i915 in requests (rev2) Patchwork
2023-07-20 16:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-07-20 17:17 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-07-21 13:05 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: use direct alias for i915 in requests (rev3) Patchwork
2023-07-21 13:05 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-07-21 13:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-07-21 16:00 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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