* [Intel-gfx] [PATCH] drm/i915: Add Wa_18028616096 @ 2023-09-21 14:30 Shekhar Chauhan 2023-09-21 21:01 ` Gustavo Sousa 2023-09-22 0:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add Wa_18028616096 (rev3) Patchwork 0 siblings, 2 replies; 12+ messages in thread From: Shekhar Chauhan @ 2023-09-21 14:30 UTC (permalink / raw) To: intel-gfx Drop UGM per set fragment threshold to 3 BSpec: 54833 Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index a00ff51c681d..431c575c532b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1230,6 +1230,7 @@ #define DISABLE_D8_D16_COASLESCE REG_BIT(30) #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15) #define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4) +#define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32) #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32) #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32) #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 660d4f358eab..992041e3776c 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2914,6 +2914,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li * Wa_22015475538:dg2 */ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); + + /* Wa_18028616096:dg2 */ + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3); } if (IS_DG2_G11(i915)) { -- 2.34.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Add Wa_18028616096 2023-09-21 14:30 [Intel-gfx] [PATCH] drm/i915: Add Wa_18028616096 Shekhar Chauhan @ 2023-09-21 21:01 ` Gustavo Sousa 2023-09-22 4:04 ` Chauhan, Shekhar 2023-09-22 0:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add Wa_18028616096 (rev3) Patchwork 1 sibling, 1 reply; 12+ messages in thread From: Gustavo Sousa @ 2023-09-21 21:01 UTC (permalink / raw) To: Shekhar Chauhan, intel-gfx Quoting Shekhar Chauhan (2023-09-21 11:30:28-03:00) >Drop UGM per set fragment threshold to 3 > >BSpec: 54833 >Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com> >--- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ > 2 files changed, 4 insertions(+) > >diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h >index a00ff51c681d..431c575c532b 100644 >--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h >+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h >@@ -1230,6 +1230,7 @@ > #define DISABLE_D8_D16_COASLESCE REG_BIT(30) > #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15) > #define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4) >+#define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32) > #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32) > #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32) > #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32) >diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c >index 660d4f358eab..992041e3776c 100644 >--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >@@ -2914,6 +2914,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li > * Wa_22015475538:dg2 > */ > wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); >+ >+ /* Wa_18028616096:dg2 */ This is not a blocker, but I would prefer to remove the ":dg2" suffix. There was an effort to remove them from our driver[1], but it kinda of stalled. I myself agree that we would be better off without them. [1] https://lore.kernel.org/all/20221222082557.1364711-1-lucas.demarchi@intel.com >+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3); This workaround applies to (i) DG2 G10 from stepping C0 to forever and (ii) any stepping of DG2 G12. Here you are applying this workaround to any variant of DG2. It should be moved out of this "if" statement and rather be guarded by something like: if ((IS_DG2_G10(i915) && IS_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER)) || IS_DG2_G12(i915)) Note that we are there is still a pending decision for G11, so we may need to update this in the future. -- Gustavo Sousa > } > > if (IS_DG2_G11(i915)) { >-- >2.34.1 > ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Add Wa_18028616096 2023-09-21 21:01 ` Gustavo Sousa @ 2023-09-22 4:04 ` Chauhan, Shekhar 2023-09-22 12:17 ` Gustavo Sousa 0 siblings, 1 reply; 12+ messages in thread From: Chauhan, Shekhar @ 2023-09-22 4:04 UTC (permalink / raw) To: Gustavo Sousa, intel-gfx, matthew.d.roper [-- Attachment #1: Type: text/plain, Size: 3078 bytes --] Quoting Gustavo Sousa: On 9/22/2023 02:31, Gustavo Sousa wrote: > Quoting Shekhar Chauhan (2023-09-21 11:30:28-03:00) >> Drop UGM per set fragment threshold to 3 >> >> BSpec: 54833 >> Signed-off-by: Shekhar Chauhan<shekhar.chauhan@intel.com> >> --- >> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + >> drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ >> 2 files changed, 4 insertions(+) >> >> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h >> index a00ff51c681d..431c575c532b 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h >> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h >> @@ -1230,6 +1230,7 @@ >> #define DISABLE_D8_D16_COASLESCE REG_BIT(30) >> #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15) >> #define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4) >> +#define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32) >> #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32) >> #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32) >> #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32) >> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> index 660d4f358eab..992041e3776c 100644 >> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >> @@ -2914,6 +2914,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li >> * Wa_22015475538:dg2 >> */ >> wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); >> + >> + /* Wa_18028616096:dg2 */ > This is not a blocker, but I would prefer to remove the ":dg2" suffix. > > There was an effort to remove them from our driver[1], but it kinda of > stalled. I myself agree that we would be better off without them. > > [1]https://lore.kernel.org/all/20221222082557.1364711-1-lucas.demarchi@intel.com Ack'ed in the new version. > >> + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3); > This workaround applies to (i) DG2 G10 from stepping C0 to forever and > (ii) any stepping of DG2 G12. Here you are applying this workaround to > any variant of DG2. > > It should be moved out of this "if" statement and rather be guarded by > something like: > > if ((IS_DG2_G10(i915) && IS_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER)) || > IS_DG2_G12(i915)) > > Note that we are there is still a pending decision for G11, so we may > need to update this in the future. I believe we're only supporting production steppings for DG2, henceforth, not really interacting with the "older" steppings. Please have a look: https://lore.kernel.org/intel-gfx/20230816214201.534095-7-matthew.d.roper@intel.com/ Although, I could be wrong, if I am, I'll send in another version, modifying the patch as you've suggested. > -- > Gustavo Sousa > >> } >> >> if (IS_DG2_G11(i915)) { >> -- >> 2.34.1 >> -- -shekhar [-- Attachment #2: Type: text/html, Size: 40158 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Add Wa_18028616096 2023-09-22 4:04 ` Chauhan, Shekhar @ 2023-09-22 12:17 ` Gustavo Sousa 0 siblings, 0 replies; 12+ messages in thread From: Gustavo Sousa @ 2023-09-22 12:17 UTC (permalink / raw) To: Chauhan, Shekhar, intel-gfx, matthew.d.roper Quoting Chauhan, Shekhar (2023-09-22 01:04:36-03:00) >Quoting Gustavo Sousa: > >On 9/22/2023 02:31, Gustavo Sousa wrote: >> Quoting Shekhar Chauhan (2023-09-21 11:30:28-03:00) >>> Drop UGM per set fragment threshold to 3 >>> >>> BSpec: 54833 >>> Signed-off-by: Shekhar Chauhan<shekhar.chauhan@intel.com> >>> --- >>> drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + >>> drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ >>> 2 files changed, 4 insertions(+) >>> >>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h >>> index a00ff51c681d..431c575c532b 100644 >>> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h >>> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h >>> @@ -1230,6 +1230,7 @@ >>> #define DISABLE_D8_D16_COASLESCE REG_BIT(30) >>> #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15) >>> #define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4) >>> +#define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32) >>> #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32) >>> #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32) >>> #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32) >>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c >>> index 660d4f358eab..992041e3776c 100644 >>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >>> @@ -2914,6 +2914,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li >>> * Wa_22015475538:dg2 >>> */ >>> wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); >>> + >>> + /* Wa_18028616096:dg2 */ >> This is not a blocker, but I would prefer to remove the ":dg2" suffix. >> >> There was an effort to remove them from our driver[1], but it kinda of >> stalled. I myself agree that we would be better off without them. >> >> [1]https://lore.kernel.org/all/20221222082557.1364711-1-lucas.demarchi@intel.com >Ack'ed in the new version. >> >>> + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3); >> This workaround applies to (i) DG2 G10 from stepping C0 to forever and >> (ii) any stepping of DG2 G12. Here you are applying this workaround to >> any variant of DG2. >> >> It should be moved out of this "if" statement and rather be guarded by >> something like: >> >> if ((IS_DG2_G10(i915) && IS_GRAPHICS_STEP(i915, STEP_C0, STEP_FOREVER)) || >> IS_DG2_G12(i915)) >> >> Note that we are there is still a pending decision for G11, so we may >> need to update this in the future. > >I believe we're only supporting production steppings for DG2, >henceforth, not really interacting with the "older" steppings. > >Please have a look: > >https://lore.kernel.org/intel-gfx/20230816214201.534095-7-matthew.d.roper@intel.com/ Oh, I missed that. Thanks! So I believe we would have the following condition instead: if (IS_DG2_G10(i915) || IS_DG2_G12(i915)) , because we do not know yet if this will also apply to DG2 G11. -- Gustavo Sousa > >Although, I could be wrong, if I am, I'll send in another version, >modifying the patch as you've suggested. > >> -- >> Gustavo Sousa >> >>> } >>> >>> if (IS_DG2_G11(i915)) { >>> -- >>> 2.34.1 >>> >-- >-shekhar ^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add Wa_18028616096 (rev3) 2023-09-21 14:30 [Intel-gfx] [PATCH] drm/i915: Add Wa_18028616096 Shekhar Chauhan 2023-09-21 21:01 ` Gustavo Sousa @ 2023-09-22 0:46 ` Patchwork 1 sibling, 0 replies; 12+ messages in thread From: Patchwork @ 2023-09-22 0:46 UTC (permalink / raw) To: Shekhar Chauhan; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 8832 bytes --] == Series Details == Series: drm/i915: Add Wa_18028616096 (rev3) URL : https://patchwork.freedesktop.org/series/123951/ State : success == Summary == CI Bug Log - changes from CI_DRM_13667 -> Patchwork_123951v3 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/index.html Participating hosts (37 -> 38) ------------------------------ Additional (2): fi-kbl-soraka bat-dg2-9 Missing (1): fi-snb-2520m Known issues ------------ Here are the changes found in Patchwork_123951v3 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_huc_copy@huc-copy: - fi-kbl-soraka: NOTRUN -> [SKIP][1] ([fdo#109271] / [i915#2190]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-kbl-soraka: NOTRUN -> [SKIP][2] ([fdo#109271] / [i915#4613]) +3 other tests skip [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html * igt@gem_mmap@basic: - bat-dg2-9: NOTRUN -> [SKIP][3] ([i915#4083]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/bat-dg2-9/igt@gem_mmap@basic.html * igt@gem_mmap_gtt@basic: - bat-dg2-9: NOTRUN -> [SKIP][4] ([i915#4077]) +2 other tests skip [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/bat-dg2-9/igt@gem_mmap_gtt@basic.html * igt@gem_render_tiled_blits@basic: - bat-dg2-9: NOTRUN -> [SKIP][5] ([i915#4079]) +1 other test skip [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/bat-dg2-9/igt@gem_render_tiled_blits@basic.html * igt@i915_pm_rps@basic-api: - bat-dg2-9: NOTRUN -> [SKIP][6] ([i915#6621]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/bat-dg2-9/igt@i915_pm_rps@basic-api.html * igt@i915_selftest@live@gt_heartbeat: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][7] ([i915#5334] / [i915#7872]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@gt_pm: - fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][8] ([i915#1886] / [i915#7913]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy: - bat-dg2-9: NOTRUN -> [SKIP][9] ([i915#5190]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/bat-dg2-9/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg2-9: NOTRUN -> [SKIP][10] ([i915#4215] / [i915#5190]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/bat-dg2-9/igt@kms_addfb_basic@basic-y-tiled-legacy.html * igt@kms_addfb_basic@framebuffer-vs-set-tiling: - bat-dg2-9: NOTRUN -> [SKIP][11] ([i915#4212]) +6 other tests skip [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/bat-dg2-9/igt@kms_addfb_basic@framebuffer-vs-set-tiling.html * igt@kms_addfb_basic@tile-pitch-mismatch: - bat-dg2-9: NOTRUN -> [SKIP][12] ([i915#4212] / [i915#5608]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/bat-dg2-9/igt@kms_addfb_basic@tile-pitch-mismatch.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - bat-dg2-9: NOTRUN -> [SKIP][13] ([i915#4103] / [i915#4213] / [i915#5608]) +1 other test skip [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/bat-dg2-9/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt@kms_dsc@dsc-basic: - fi-kbl-soraka: NOTRUN -> [SKIP][14] ([fdo#109271]) +9 other tests skip [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/fi-kbl-soraka/igt@kms_dsc@dsc-basic.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg2-9: NOTRUN -> [SKIP][15] ([fdo#109285]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/bat-dg2-9/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_force_connector_basic@prune-stale-modes: - bat-dg2-9: NOTRUN -> [SKIP][16] ([i915#5274]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/bat-dg2-9/igt@kms_force_connector_basic@prune-stale-modes.html * igt@kms_psr@sprite_plane_onoff: - bat-dg2-9: NOTRUN -> [SKIP][17] ([i915#1072]) +3 other tests skip [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/bat-dg2-9/igt@kms_psr@sprite_plane_onoff.html * igt@kms_setmode@basic-clone-single-crtc: - bat-dg2-9: NOTRUN -> [SKIP][18] ([i915#3555]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/bat-dg2-9/igt@kms_setmode@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-flip: - bat-dg2-9: NOTRUN -> [SKIP][19] ([i915#3708]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/bat-dg2-9/igt@prime_vgem@basic-fence-flip.html * igt@prime_vgem@basic-fence-mmap: - bat-dg2-9: NOTRUN -> [SKIP][20] ([i915#3708] / [i915#4077]) +1 other test skip [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/bat-dg2-9/igt@prime_vgem@basic-fence-mmap.html * igt@prime_vgem@basic-write: - bat-dg2-9: NOTRUN -> [SKIP][21] ([i915#3291] / [i915#3708]) +2 other tests skip [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/bat-dg2-9/igt@prime_vgem@basic-write.html #### Possible fixes #### * igt@i915_selftest@live@gt_heartbeat: - fi-apl-guc: [DMESG-FAIL][22] ([i915#5334]) -> [PASS][23] [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13667/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html * igt@kms_hdmi_inject@inject-audio: - fi-kbl-guc: [FAIL][24] ([IGT#3]) -> [PASS][25] [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13667/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190 [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274 [i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608 [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621 [i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872 [i915#7913]: https://gitlab.freedesktop.org/drm/intel/issues/7913 Build changes ------------- * Linux: CI_DRM_13667 -> Patchwork_123951v3 CI-20190529: 20190529 CI_DRM_13667: 5e02013de5896d3099b06de0d2d93c6788111409 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_7496: 6a96d3ad178e468b74a58cc10dead2f57bc1558d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_123951v3: 5e02013de5896d3099b06de0d2d93c6788111409 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 0f848481fa91 drm/i915: Add Wa_18028616096 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_123951v3/index.html [-- Attachment #2: Type: text/html, Size: 10557 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH] drm/i915: Add Wa_18028616096 @ 2023-09-22 3:50 Shekhar Chauhan 0 siblings, 0 replies; 12+ messages in thread From: Shekhar Chauhan @ 2023-09-22 3:50 UTC (permalink / raw) To: intel-gfx; +Cc: matthew.d.roper Drop UGM per set fragment threshold to 3 BSpec: 54833 Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index a00ff51c681d..431c575c532b 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1230,6 +1230,7 @@ #define DISABLE_D8_D16_COASLESCE REG_BIT(30) #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15) #define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4) +#define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32) #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32) #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32) #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 660d4f358eab..317d5d8d320e 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2914,6 +2914,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li * Wa_22015475538:dg2 */ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); + + /* Wa_18028616096 */ + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3); } if (IS_DG2_G11(i915)) { -- 2.34.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH] drm/i915: Add Wa_18028616096 @ 2023-09-21 4:27 Shekhar Chauhan 2023-09-21 7:17 ` kernel test robot 2023-09-21 8:20 ` kernel test robot 0 siblings, 2 replies; 12+ messages in thread From: Shekhar Chauhan @ 2023-09-21 4:27 UTC (permalink / raw) To: intel-gfx Drop UGM per set fragment threshold to 3 BSpec: 54833 Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index a00ff51c681d..326224abe395 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1230,6 +1230,7 @@ #define DISABLE_D8_D16_COASLESCE REG_BIT(30) #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15) #define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4) +#define UGM_FRAGMENT_THRESHOLD_TO_3 MCR_REG(58 - 32) #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32) #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32) #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 660d4f358eab..992041e3776c 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2914,6 +2914,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li * Wa_22015475538:dg2 */ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); + + /* Wa_18028616096:dg2 */ + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3); } if (IS_DG2_G11(i915)) { -- 2.34.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Add Wa_18028616096 2023-09-21 4:27 Shekhar Chauhan @ 2023-09-21 7:17 ` kernel test robot 2023-09-21 8:20 ` kernel test robot 1 sibling, 0 replies; 12+ messages in thread From: kernel test robot @ 2023-09-21 7:17 UTC (permalink / raw) To: Shekhar Chauhan, intel-gfx; +Cc: oe-kbuild-all Hi Shekhar, kernel test robot noticed the following build errors: [auto build test ERROR on drm-tip/drm-tip] url: https://github.com/intel-lab-lkp/linux/commits/Shekhar-Chauhan/drm-i915-Add-Wa_18028616096/20230921-122837 base: git://anongit.freedesktop.org/drm/drm-tip drm-tip patch link: https://lore.kernel.org/r/20230921042727.362710-1-shekhar.chauhan%40intel.com patch subject: [Intel-gfx] [PATCH] drm/i915: Add Wa_18028616096 config: i386-randconfig-014-20230921 (https://download.01.org/0day-ci/archive/20230921/202309211509.sE4onxLs-lkp@intel.com/config) compiler: gcc-12 (Debian 12.2.0-14) 12.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230921/202309211509.sE4onxLs-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202309211509.sE4onxLs-lkp@intel.com/ All errors (new ones prefixed by >>): In file included from drivers/gpu/drm/i915/intel_uncore.h:34, from drivers/gpu/drm/i915/gt/intel_engine_types.h:26, from drivers/gpu/drm/i915/gt/intel_context_types.h:18, from drivers/gpu/drm/i915/gem/i915_gem_context_types.h:20, from drivers/gpu/drm/i915/i915_drv.h:42, from drivers/gpu/drm/i915/gt/intel_workarounds.c:6: drivers/gpu/drm/i915/gt/intel_workarounds.c: In function 'general_render_compute_wa_init': >> drivers/gpu/drm/i915/i915_reg_defs.h:273:25: error: incompatible type for argument 3 of 'wa_mcr_write_or' 273 | #define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg = (offset) }) | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ | | | i915_mcr_reg_t drivers/gpu/drm/i915/gt/intel_gt_regs.h:1235:49: note: in expansion of macro 'MCR_REG' 1235 | #define UGM_FRAGMENT_THRESHOLD_TO_3 MCR_REG(58 - 32) | ^~~~~~~ drivers/gpu/drm/i915/gt/intel_workarounds.c:2919:61: note: in expansion of macro 'UGM_FRAGMENT_THRESHOLD_TO_3' 2919 | wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/i915/gt/intel_workarounds.c:272:67: note: expected 'u32' {aka 'unsigned int'} but argument is of type 'i915_mcr_reg_t' 272 | wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set) | ~~~~^~~ vim +/wa_mcr_write_or +273 drivers/gpu/drm/i915/i915_reg_defs.h 2b25a93bf07c6b Matt Roper 2022-01-10 272 c6a53c90e3be8b Lucas De Marchi 2023-02-24 @273 #define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg = (offset) }) c6a53c90e3be8b Lucas De Marchi 2023-02-24 274 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Add Wa_18028616096 2023-09-21 4:27 Shekhar Chauhan 2023-09-21 7:17 ` kernel test robot @ 2023-09-21 8:20 ` kernel test robot 1 sibling, 0 replies; 12+ messages in thread From: kernel test robot @ 2023-09-21 8:20 UTC (permalink / raw) To: Shekhar Chauhan, intel-gfx; +Cc: llvm, oe-kbuild-all Hi Shekhar, kernel test robot noticed the following build errors: [auto build test ERROR on drm-tip/drm-tip] url: https://github.com/intel-lab-lkp/linux/commits/Shekhar-Chauhan/drm-i915-Add-Wa_18028616096/20230921-122837 base: git://anongit.freedesktop.org/drm/drm-tip drm-tip patch link: https://lore.kernel.org/r/20230921042727.362710-1-shekhar.chauhan%40intel.com patch subject: [Intel-gfx] [PATCH] drm/i915: Add Wa_18028616096 config: x86_64-rhel-8.3-rust (https://download.01.org/0day-ci/archive/20230921/202309211602.VPUFAm7i-lkp@intel.com/config) compiler: clang version 16.0.4 (https://github.com/llvm/llvm-project.git ae42196bc493ffe877a7e3dff8be32035dea4d07) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230921/202309211602.VPUFAm7i-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202309211602.VPUFAm7i-lkp@intel.com/ All errors (new ones prefixed by >>): >> drivers/gpu/drm/i915/gt/intel_workarounds.c:2919:47: error: passing 'const i915_mcr_reg_t' to parameter of incompatible type 'u32' (aka 'unsigned int') wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3); ^~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/i915/gt/intel_gt_regs.h:1235:40: note: expanded from macro 'UGM_FRAGMENT_THRESHOLD_TO_3' #define UGM_FRAGMENT_THRESHOLD_TO_3 MCR_REG(58 - 32) ^~~~~~~~~~~~~~~~ drivers/gpu/drm/i915/i915_reg_defs.h:273:25: note: expanded from macro 'MCR_REG' #define MCR_REG(offset) ((const i915_mcr_reg_t){ .reg = (offset) }) ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/i915/gt/intel_workarounds.c:272:67: note: passing argument to parameter 'set' here wa_mcr_write_or(struct i915_wa_list *wal, i915_mcr_reg_t reg, u32 set) ^ 1 error generated. vim +2919 drivers/gpu/drm/i915/gt/intel_workarounds.c 2828 2829 /* 2830 * The workarounds in this function apply to shared registers in 2831 * the general render reset domain that aren't tied to a 2832 * specific engine. Since all render+compute engines get reset 2833 * together, and the contents of these registers are lost during 2834 * the shared render domain reset, we'll define such workarounds 2835 * here and then add them to just a single RCS or CCS engine's 2836 * workaround list (whichever engine has the XXXX flag). 2837 */ 2838 static void 2839 general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal) 2840 { 2841 struct drm_i915_private *i915 = engine->i915; 2842 struct intel_gt *gt = engine->gt; 2843 2844 add_render_compute_tuning_settings(gt, wal); 2845 2846 if (GRAPHICS_VER(i915) >= 11) { 2847 /* This is not a Wa (although referred to as 2848 * WaSetInidrectStateOverride in places), this allows 2849 * applications that reference sampler states through 2850 * the BindlessSamplerStateBaseAddress to have their 2851 * border color relative to DynamicStateBaseAddress 2852 * rather than BindlessSamplerStateBaseAddress. 2853 * 2854 * Otherwise SAMPLER_STATE border colors have to be 2855 * copied in multiple heaps (DynamicStateBaseAddress & 2856 * BindlessSamplerStateBaseAddress) 2857 * 2858 * BSpec: 46052 2859 */ 2860 wa_mcr_masked_en(wal, 2861 GEN10_SAMPLER_MODE, 2862 GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE); 2863 } 2864 2865 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_B0, STEP_FOREVER) || 2866 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_B0, STEP_FOREVER)) 2867 /* Wa_14017856879 */ 2868 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN3, MTL_DISABLE_FIX_FOR_EOT_FLUSH); 2869 2870 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || 2871 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) 2872 /* 2873 * Wa_14017066071 2874 * Wa_14017654203 2875 */ 2876 wa_mcr_masked_en(wal, GEN10_SAMPLER_MODE, 2877 MTL_DISABLE_SAMPLER_SC_OOO); 2878 2879 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0)) 2880 /* Wa_22015279794 */ 2881 wa_mcr_masked_en(wal, GEN10_CACHE_MODE_SS, 2882 DISABLE_PREFETCH_INTO_IC); 2883 2884 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || 2885 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) || 2886 IS_DG2(i915)) { 2887 /* Wa_22013037850 */ 2888 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, 2889 DISABLE_128B_EVICTION_COMMAND_UDW); 2890 2891 /* Wa_18017747507 */ 2892 wa_masked_en(wal, VFG_PREEMPTION_CHICKEN, POLYGON_TRIFAN_LINELOOP_DISABLE); 2893 } 2894 2895 if (IS_GFX_GT_IP_STEP(gt, IP_VER(12, 70), STEP_A0, STEP_B0) || 2896 IS_GFX_GT_IP_STEP(gt, IP_VER(12, 71), STEP_A0, STEP_B0) || 2897 IS_PONTEVECCHIO(i915) || 2898 IS_DG2(i915)) { 2899 /* Wa_22014226127 */ 2900 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, DISABLE_D8_D16_COASLESCE); 2901 } 2902 2903 if (IS_PONTEVECCHIO(i915) || IS_DG2(i915)) { 2904 /* Wa_14015227452:dg2,pvc */ 2905 wa_mcr_masked_en(wal, GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE); 2906 2907 /* Wa_16015675438:dg2,pvc */ 2908 wa_masked_en(wal, FF_SLICE_CS_CHICKEN2, GEN12_PERF_FIX_BALANCING_CFE_DISABLE); 2909 } 2910 2911 if (IS_DG2(i915)) { 2912 /* 2913 * Wa_16011620976:dg2_g11 2914 * Wa_22015475538:dg2 2915 */ 2916 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); 2917 2918 /* Wa_18028616096:dg2 */ > 2919 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3); 2920 } 2921 2922 if (IS_DG2_G11(i915)) { 2923 /* 2924 * Wa_22012826095:dg2 2925 * Wa_22013059131:dg2 2926 */ 2927 wa_mcr_write_clr_set(wal, LSC_CHICKEN_BIT_0_UDW, 2928 MAXREQS_PER_BANK, 2929 REG_FIELD_PREP(MAXREQS_PER_BANK, 2)); 2930 2931 /* Wa_22013059131:dg2 */ 2932 wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, 2933 FORCE_1_SUB_MESSAGE_PER_FRAGMENT); 2934 2935 /* 2936 * Wa_22012654132 2937 * 2938 * Note that register 0xE420 is write-only and cannot be read 2939 * back for verification on DG2 (due to Wa_14012342262), so 2940 * we need to explicitly skip the readback. 2941 */ 2942 wa_mcr_add(wal, GEN10_CACHE_MODE_SS, 0, 2943 _MASKED_BIT_ENABLE(ENABLE_PREFETCH_INTO_IC), 2944 0 /* write-only, so skip validation */, 2945 true); 2946 } 2947 2948 if (IS_XEHPSDV(i915)) { 2949 /* Wa_1409954639 */ 2950 wa_mcr_masked_en(wal, 2951 GEN8_ROW_CHICKEN, 2952 SYSTOLIC_DOP_CLOCK_GATING_DIS); 2953 2954 /* Wa_1607196519 */ 2955 wa_mcr_masked_en(wal, 2956 GEN9_ROW_CHICKEN4, 2957 GEN12_DISABLE_GRF_CLEAR); 2958 2959 /* Wa_14010449647:xehpsdv */ 2960 wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, 2961 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); 2962 } 2963 } 2964 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH] drm/i915: Add Wa_18028616096 @ 2023-09-20 4:05 Shekhar Chauhan 2023-09-20 6:42 ` kernel test robot 2023-09-20 13:42 ` Gustavo Sousa 0 siblings, 2 replies; 12+ messages in thread From: Shekhar Chauhan @ 2023-09-20 4:05 UTC (permalink / raw) To: intel-gfx Drop UGM per set fragment threshold to 3 BSpec: 54833 Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com> --- drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h index a00ff51c681d..f8ab99affa15 100644 --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h @@ -1227,6 +1227,7 @@ #define EU_PERF_CNTL3 PERF_REG(0xe758) #define LSC_CHICKEN_BIT_0 MCR_REG(0xe7c8) +#define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58) #define DISABLE_D8_D16_COASLESCE REG_BIT(30) #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15) #define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4) diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 660d4f358eab..3f3977014ee7 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -2914,6 +2914,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li * Wa_22015475538:dg2 */ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); + + /* Wa_18028616096:dg2 */ + wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, UGM_FRAGMENT_THRESHOLD_TO_3); } if (IS_DG2_G11(i915)) { -- 2.34.1 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Add Wa_18028616096 2023-09-20 4:05 Shekhar Chauhan @ 2023-09-20 6:42 ` kernel test robot 2023-09-20 13:42 ` Gustavo Sousa 1 sibling, 0 replies; 12+ messages in thread From: kernel test robot @ 2023-09-20 6:42 UTC (permalink / raw) To: Shekhar Chauhan, intel-gfx; +Cc: oe-kbuild-all Hi Shekhar, kernel test robot noticed the following build errors: [auto build test ERROR on drm-tip/drm-tip] url: https://github.com/intel-lab-lkp/linux/commits/Shekhar-Chauhan/drm-i915-Add-Wa_18028616096/20230920-121417 base: git://anongit.freedesktop.org/drm/drm-tip drm-tip patch link: https://lore.kernel.org/r/20230920040547.181861-1-shekhar.chauhan%40intel.com patch subject: [Intel-gfx] [PATCH] drm/i915: Add Wa_18028616096 config: x86_64-randconfig-003-20230920 (https://download.01.org/0day-ci/archive/20230920/202309201405.PF0VVCts-lkp@intel.com/config) compiler: gcc-12 (Debian 12.2.0-14) 12.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20230920/202309201405.PF0VVCts-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot <lkp@intel.com> | Closes: https://lore.kernel.org/oe-kbuild-all/202309201405.PF0VVCts-lkp@intel.com/ All errors (new ones prefixed by >>): In file included from include/linux/container_of.h:5, from include/linux/plist.h:76, from include/linux/pm_qos.h:15, from drivers/gpu/drm/i915/i915_drv.h:35, from drivers/gpu/drm/i915/gt/intel_workarounds.c:6: drivers/gpu/drm/i915/gt/intel_workarounds.c: In function 'general_render_compute_wa_init': >> include/linux/build_bug.h:16:51: error: negative width in bit-field '<anonymous>' 16 | #define BUILD_BUG_ON_ZERO(e) ((int)(sizeof(struct { int:(-!!(e)); }))) | ^ drivers/gpu/drm/i915/i915_reg_defs.h:22:16: note: in expansion of macro 'BUILD_BUG_ON_ZERO' 22 | BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ | ^~~~~~~~~~~~~~~~~ drivers/gpu/drm/i915/gt/intel_gt_regs.h:1232:49: note: in expansion of macro 'REG_BIT' 1232 | #define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58) | ^~~~~~~ drivers/gpu/drm/i915/gt/intel_workarounds.c:2919:57: note: in expansion of macro 'UGM_FRAGMENT_THRESHOLD_TO_3' 2919 | wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, UGM_FRAGMENT_THRESHOLD_TO_3); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~ vim +16 include/linux/build_bug.h bc6245e5efd70c Ian Abbott 2017-07-10 6 bc6245e5efd70c Ian Abbott 2017-07-10 7 #ifdef __CHECKER__ bc6245e5efd70c Ian Abbott 2017-07-10 8 #define BUILD_BUG_ON_ZERO(e) (0) bc6245e5efd70c Ian Abbott 2017-07-10 9 #else /* __CHECKER__ */ bc6245e5efd70c Ian Abbott 2017-07-10 10 /* bc6245e5efd70c Ian Abbott 2017-07-10 11 * Force a compilation error if condition is true, but also produce a 8788994376d84d Rikard Falkeborn 2019-12-04 12 * result (of value 0 and type int), so the expression can be used bc6245e5efd70c Ian Abbott 2017-07-10 13 * e.g. in a structure initializer (or where-ever else comma expressions bc6245e5efd70c Ian Abbott 2017-07-10 14 * aren't permitted). bc6245e5efd70c Ian Abbott 2017-07-10 15 */ 8788994376d84d Rikard Falkeborn 2019-12-04 @16 #define BUILD_BUG_ON_ZERO(e) ((int)(sizeof(struct { int:(-!!(e)); }))) 527edbc18a70e7 Masahiro Yamada 2019-01-03 17 #endif /* __CHECKER__ */ 527edbc18a70e7 Masahiro Yamada 2019-01-03 18 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Add Wa_18028616096 2023-09-20 4:05 Shekhar Chauhan 2023-09-20 6:42 ` kernel test robot @ 2023-09-20 13:42 ` Gustavo Sousa 1 sibling, 0 replies; 12+ messages in thread From: Gustavo Sousa @ 2023-09-20 13:42 UTC (permalink / raw) To: Shekhar Chauhan, intel-gfx Quoting Shekhar Chauhan (2023-09-20 01:05:47-03:00) >Drop UGM per set fragment threshold to 3 > >BSpec: 54833 >Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com> >--- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++ > 2 files changed, 4 insertions(+) > >diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h >index a00ff51c681d..f8ab99affa15 100644 >--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h >+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h >@@ -1227,6 +1227,7 @@ > #define EU_PERF_CNTL3 PERF_REG(0xe758) > > #define LSC_CHICKEN_BIT_0 MCR_REG(0xe7c8) >+#define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58) You probably want to define this as: #define UGM_FRAGMENT_THRESHOLD_TO_3 REG_BIT(58 - 32) , and after the definition of LSC_CHICKEN_BIT_0_UDW. See more below... > #define DISABLE_D8_D16_COASLESCE REG_BIT(30) > #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15) > #define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4) >diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c >index 660d4f358eab..3f3977014ee7 100644 >--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c >+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c >@@ -2914,6 +2914,9 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li > * Wa_22015475538:dg2 > */ > wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0_UDW, DIS_CHAIN_2XSIMD8); >+ >+ /* Wa_18028616096:dg2 */ >+ wa_mcr_write_or(wal, LSC_CHICKEN_BIT_0, UGM_FRAGMENT_THRESHOLD_TO_3); ...and here, use LSC_CHICKEN_BIT_0_UDW as target. -- Gustavo Sousa > } > > if (IS_DG2_G11(i915)) { >-- >2.34.1 > ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2023-09-22 12:18 UTC | newest] Thread overview: 12+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-09-21 14:30 [Intel-gfx] [PATCH] drm/i915: Add Wa_18028616096 Shekhar Chauhan 2023-09-21 21:01 ` Gustavo Sousa 2023-09-22 4:04 ` Chauhan, Shekhar 2023-09-22 12:17 ` Gustavo Sousa 2023-09-22 0:46 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Add Wa_18028616096 (rev3) Patchwork -- strict thread matches above, loose matches on Subject: below -- 2023-09-22 3:50 [Intel-gfx] [PATCH] drm/i915: Add Wa_18028616096 Shekhar Chauhan 2023-09-21 4:27 Shekhar Chauhan 2023-09-21 7:17 ` kernel test robot 2023-09-21 8:20 ` kernel test robot 2023-09-20 4:05 Shekhar Chauhan 2023-09-20 6:42 ` kernel test robot 2023-09-20 13:42 ` Gustavo Sousa
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