* [PATCH] drm/i915/chv: fix HW readout of the port PLL fractional divider
@ 2015-07-02 11:29 Imre Deak
2015-07-02 13:33 ` Ville Syrjälä
2015-07-04 12:42 ` shuang.he
0 siblings, 2 replies; 5+ messages in thread
From: Imre Deak @ 2015-07-02 11:29 UTC (permalink / raw)
To: intel-gfx
Ville noticed that the PLL HW readout code parsed the fractional
divider value as if the fractional divider was always enabled. This may
result in a port clock state check mismatch if the preceeding modeset
disabled the fractional divider, but left a non-zero divider value in
the register.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5cc405d..2b7ebf1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8021,7 +8021,7 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
int pipe = pipe_config->cpu_transcoder;
enum dpio_channel port = vlv_pipe_to_channel(pipe);
intel_clock_t clock;
- u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
+ u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
int refclk = 100000;
mutex_lock(&dev_priv->sb_lock);
@@ -8029,10 +8029,13 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
+ pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
mutex_unlock(&dev_priv->sb_lock);
clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
- clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
+ clock.m2 = (pll_dw0 & 0xff) << 22;
+ if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
+ clock.m2 |= pll_dw2 & 0x3fffff;
clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
--
2.1.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/chv: fix HW readout of the port PLL fractional divider
2015-07-02 11:29 [PATCH] drm/i915/chv: fix HW readout of the port PLL fractional divider Imre Deak
@ 2015-07-02 13:33 ` Ville Syrjälä
2015-07-06 9:32 ` Daniel Vetter
2015-07-04 12:42 ` shuang.he
1 sibling, 1 reply; 5+ messages in thread
From: Ville Syrjälä @ 2015-07-02 13:33 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Jul 02, 2015 at 02:29:58PM +0300, Imre Deak wrote:
> Ville noticed that the PLL HW readout code parsed the fractional
> divider value as if the fractional divider was always enabled. This may
> result in a port clock state check mismatch if the preceeding modeset
> disabled the fractional divider, but left a non-zero divider value in
> the register.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 5cc405d..2b7ebf1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -8021,7 +8021,7 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
> int pipe = pipe_config->cpu_transcoder;
> enum dpio_channel port = vlv_pipe_to_channel(pipe);
> intel_clock_t clock;
> - u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
> + u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
> int refclk = 100000;
>
> mutex_lock(&dev_priv->sb_lock);
> @@ -8029,10 +8029,13 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
> pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
> pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
> pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
> + pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
> mutex_unlock(&dev_priv->sb_lock);
>
> clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
> - clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
> + clock.m2 = (pll_dw0 & 0xff) << 22;
> + if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
> + clock.m2 |= pll_dw2 & 0x3fffff;
> clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
> clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
> clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
> --
> 2.1.4
--
Ville Syrjälä
Intel OTC
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/chv: fix HW readout of the port PLL fractional divider
2015-07-02 13:33 ` Ville Syrjälä
@ 2015-07-06 9:32 ` Daniel Vetter
2015-07-06 9:34 ` Daniel Vetter
0 siblings, 1 reply; 5+ messages in thread
From: Daniel Vetter @ 2015-07-06 9:32 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Thu, Jul 02, 2015 at 04:33:42PM +0300, Ville Syrjälä wrote:
> On Thu, Jul 02, 2015 at 02:29:58PM +0300, Imre Deak wrote:
> > Ville noticed that the PLL HW readout code parsed the fractional
> > divider value as if the fractional divider was always enabled. This may
> > result in a port clock state check mismatch if the preceeding modeset
> > disabled the fractional divider, but left a non-zero divider value in
> > the register.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
>
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Queued for -fixes (with cc: stable), thanks for the patch.
-Daniel
>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 7 +++++--
> > 1 file changed, 5 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index 5cc405d..2b7ebf1 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -8021,7 +8021,7 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
> > int pipe = pipe_config->cpu_transcoder;
> > enum dpio_channel port = vlv_pipe_to_channel(pipe);
> > intel_clock_t clock;
> > - u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
> > + u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
> > int refclk = 100000;
> >
> > mutex_lock(&dev_priv->sb_lock);
> > @@ -8029,10 +8029,13 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
> > pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
> > pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
> > pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
> > + pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
> > mutex_unlock(&dev_priv->sb_lock);
> >
> > clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
> > - clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
> > + clock.m2 = (pll_dw0 & 0xff) << 22;
> > + if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
> > + clock.m2 |= pll_dw2 & 0x3fffff;
> > clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
> > clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
> > clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
> > --
> > 2.1.4
>
> --
> Ville Syrjälä
> Intel OTC
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/chv: fix HW readout of the port PLL fractional divider
2015-07-06 9:32 ` Daniel Vetter
@ 2015-07-06 9:34 ` Daniel Vetter
0 siblings, 0 replies; 5+ messages in thread
From: Daniel Vetter @ 2015-07-06 9:34 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Jul 06, 2015 at 11:32:47AM +0200, Daniel Vetter wrote:
> On Thu, Jul 02, 2015 at 04:33:42PM +0300, Ville Syrjälä wrote:
> > On Thu, Jul 02, 2015 at 02:29:58PM +0300, Imre Deak wrote:
> > > Ville noticed that the PLL HW readout code parsed the fractional
> > > divider value as if the fractional divider was always enabled. This may
> > > result in a port clock state check mismatch if the preceeding modeset
> > > disabled the fractional divider, but left a non-zero divider value in
> > > the register.
> > >
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> >
> > Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Queued for -fixes (with cc: stable), thanks for the patch.
Maybe doesn't justify stable, so dropped that again.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/chv: fix HW readout of the port PLL fractional divider
2015-07-02 11:29 [PATCH] drm/i915/chv: fix HW readout of the port PLL fractional divider Imre Deak
2015-07-02 13:33 ` Ville Syrjälä
@ 2015-07-04 12:42 ` shuang.he
1 sibling, 0 replies; 5+ messages in thread
From: shuang.he @ 2015-07-04 12:42 UTC (permalink / raw)
To: shuang.he, lei.a.liu, intel-gfx, imre.deak
Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
Task id: 6707
-------------------------------------Summary-------------------------------------
Platform Delta drm-intel-nightly Series Applied
ILK 302/302 302/302
SNB 312/316 312/316
IVB 343/343 343/343
BYT -1 287/287 286/287
HSW 380/380 380/380
-------------------------------------Detailed-------------------------------------
Platform Test drm-intel-nightly Series Applied
*BYT igt@gem_tiled_partial_pwrite_pread@reads PASS(1) FAIL(1)
Note: You need to pay more attention to line start with '*'
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2015-07-06 9:31 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2015-07-02 11:29 [PATCH] drm/i915/chv: fix HW readout of the port PLL fractional divider Imre Deak
2015-07-02 13:33 ` Ville Syrjälä
2015-07-06 9:32 ` Daniel Vetter
2015-07-06 9:34 ` Daniel Vetter
2015-07-04 12:42 ` shuang.he
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox