* [Intel-gfx] [PATCH] drm/i915/rc6: throw out set() wrapper
@ 2023-04-21 13:59 Jani Nikula
2023-04-21 14:52 ` Matt Roper
` (4 more replies)
0 siblings, 5 replies; 7+ messages in thread
From: Jani Nikula @ 2023-04-21 13:59 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Remove useless indirection that's just misdirection for the readers.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/gt/intel_rc6.c | 157 ++++++++++++++--------------
1 file changed, 76 insertions(+), 81 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 8f3cd68d14f8..908a3d0f2343 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -53,11 +53,6 @@ static struct drm_i915_private *rc6_to_i915(struct intel_rc6 *rc)
return rc6_to_gt(rc)->i915;
}
-static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)
-{
- intel_uncore_write_fw(uncore, reg, val);
-}
-
static void gen11_rc6_enable(struct intel_rc6 *rc6)
{
struct intel_gt *gt = rc6_to_gt(rc6);
@@ -72,19 +67,19 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
*/
if (!intel_uc_uses_guc_rc(>->uc)) {
/* 2b: Program RC6 thresholds.*/
- set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
- set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
+ intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
+ intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
- set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
- set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
+ intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
+ intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
for_each_engine(engine, rc6_to_gt(rc6), id)
- set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
+ intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
- set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
+ intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
- set(uncore, GEN6_RC_SLEEP, 0);
+ intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
- set(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
+ intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
}
/*
@@ -105,8 +100,8 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
* Broadwell+, To be conservative, we want to factor in a context
* switch on top (due to ksoftirqd).
*/
- set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
- set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
+ intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
+ intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
/* 3a: Enable RC6
*
@@ -141,7 +136,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
VDN_MFX_POWERGATE_ENABLE(i));
}
- set(uncore, GEN9_PG_ENABLE, pg_enable);
+ intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, pg_enable);
}
static void gen9_rc6_enable(struct intel_rc6 *rc6)
@@ -152,26 +147,26 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
/* 2b: Program RC6 thresholds.*/
if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 11) {
- set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
- set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
+ intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
+ intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
} else if (IS_SKYLAKE(rc6_to_i915(rc6))) {
/*
* WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
* when CPG is enabled
*/
- set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
+ intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
} else {
- set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
+ intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
}
- set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
- set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
+ intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
+ intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
for_each_engine(engine, rc6_to_gt(rc6), id)
- set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
+ intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
- set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
+ intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
- set(uncore, GEN6_RC_SLEEP, 0);
+ intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
/*
* 2c: Program Coarse Power Gating Policies.
@@ -194,11 +189,11 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
* conservative, we have to factor in a context switch on top (due
* to ksoftirqd).
*/
- set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
- set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
+ intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
+ intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
/* 3a: Enable RC6 */
- set(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
+ intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
rc6->ctl_enable =
GEN6_RC_CTL_HW_ENABLE |
@@ -210,8 +205,8 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
* - Render/Media PG need to be disabled with RC6.
*/
if (!NEEDS_WaRsDisableCoarsePowerGating(rc6_to_i915(rc6)))
- set(uncore, GEN9_PG_ENABLE,
- GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
+ intel_uncore_write_fw(uncore, GEN9_PG_ENABLE,
+ GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
}
static void gen8_rc6_enable(struct intel_rc6 *rc6)
@@ -221,13 +216,13 @@ static void gen8_rc6_enable(struct intel_rc6 *rc6)
enum intel_engine_id id;
/* 2b: Program RC6 thresholds.*/
- set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
- set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
- set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
+ intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
+ intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
+ intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
for_each_engine(engine, rc6_to_gt(rc6), id)
- set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
- set(uncore, GEN6_RC_SLEEP, 0);
- set(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
+ intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
+ intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
+ intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
/* 3: Enable RC6 */
rc6->ctl_enable =
@@ -245,20 +240,20 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
u32 rc6vids, rc6_mask;
int ret;
- set(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
- set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
- set(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
- set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
- set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
+ intel_uncore_write_fw(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
+ intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
+ intel_uncore_write_fw(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
+ intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
+ intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
for_each_engine(engine, rc6_to_gt(rc6), id)
- set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
+ intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
- set(uncore, GEN6_RC_SLEEP, 0);
- set(uncore, GEN6_RC1e_THRESHOLD, 1000);
- set(uncore, GEN6_RC6_THRESHOLD, 50000);
- set(uncore, GEN6_RC6p_THRESHOLD, 150000);
- set(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */
+ intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
+ intel_uncore_write_fw(uncore, GEN6_RC1e_THRESHOLD, 1000);
+ intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000);
+ intel_uncore_write_fw(uncore, GEN6_RC6p_THRESHOLD, 150000);
+ intel_uncore_write_fw(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */
/* We don't use those on Haswell */
rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
@@ -372,22 +367,22 @@ static void chv_rc6_enable(struct intel_rc6 *rc6)
enum intel_engine_id id;
/* 2a: Program RC6 thresholds.*/
- set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
- set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
- set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
+ intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
+ intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
+ intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
for_each_engine(engine, rc6_to_gt(rc6), id)
- set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
- set(uncore, GEN6_RC_SLEEP, 0);
+ intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
+ intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
/* TO threshold set to 500 us (0x186 * 1.28 us) */
- set(uncore, GEN6_RC6_THRESHOLD, 0x186);
+ intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x186);
/* Allows RC6 residency counter to work */
- set(uncore, VLV_COUNTER_CONTROL,
- _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
- VLV_MEDIA_RC6_COUNT_EN |
- VLV_RENDER_RC6_COUNT_EN));
+ intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
+ _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
+ VLV_MEDIA_RC6_COUNT_EN |
+ VLV_RENDER_RC6_COUNT_EN));
/* 3: Enable RC6 */
rc6->ctl_enable = GEN7_RC_CTL_TO_MODE;
@@ -399,22 +394,22 @@ static void vlv_rc6_enable(struct intel_rc6 *rc6)
struct intel_engine_cs *engine;
enum intel_engine_id id;
- set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
- set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
- set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
+ intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
+ intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
+ intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
for_each_engine(engine, rc6_to_gt(rc6), id)
- set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
+ intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
- set(uncore, GEN6_RC6_THRESHOLD, 0x557);
+ intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x557);
/* Allows RC6 residency counter to work */
- set(uncore, VLV_COUNTER_CONTROL,
- _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
- VLV_MEDIA_RC0_COUNT_EN |
- VLV_RENDER_RC0_COUNT_EN |
- VLV_MEDIA_RC6_COUNT_EN |
- VLV_RENDER_RC6_COUNT_EN));
+ intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
+ _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
+ VLV_MEDIA_RC0_COUNT_EN |
+ VLV_RENDER_RC0_COUNT_EN |
+ VLV_MEDIA_RC6_COUNT_EN |
+ VLV_RENDER_RC6_COUNT_EN));
rc6->ctl_enable =
GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
@@ -575,9 +570,9 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
if (GRAPHICS_VER(i915) >= 9)
- set(uncore, GEN9_PG_ENABLE, 0);
- set(uncore, GEN6_RC_CONTROL, 0);
- set(uncore, GEN6_RC_STATE, 0);
+ intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, 0);
+ intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, 0);
+ intel_uncore_write_fw(uncore, GEN6_RC_STATE, 0);
intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
}
@@ -684,7 +679,7 @@ void intel_rc6_unpark(struct intel_rc6 *rc6)
return;
/* Restore HW timers for automatic RC6 entry while busy */
- set(uncore, GEN6_RC_CONTROL, rc6->ctl_enable);
+ intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, rc6->ctl_enable);
}
void intel_rc6_park(struct intel_rc6 *rc6)
@@ -704,7 +699,7 @@ void intel_rc6_park(struct intel_rc6 *rc6)
return;
/* Turn off the HW timers and go directly to rc6 */
- set(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE);
+ intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE);
if (HAS_RC6pp(rc6_to_i915(rc6)))
target = 0x6; /* deepest rc6 */
@@ -712,7 +707,7 @@ void intel_rc6_park(struct intel_rc6 *rc6)
target = 0x5; /* deep rc6 */
else
target = 0x4; /* normal rc6 */
- set(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT);
+ intel_uncore_write_fw(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT);
}
void intel_rc6_disable(struct intel_rc6 *rc6)
@@ -735,7 +730,7 @@ void intel_rc6_fini(struct intel_rc6 *rc6)
/* We want the BIOS C6 state preserved across loads for MTL */
if (IS_METEORLAKE(rc6_to_i915(rc6)) && rc6->bios_state_captured)
- set(uncore, GEN6_RC_STATE, rc6->bios_rc_state);
+ intel_uncore_write_fw(uncore, GEN6_RC_STATE, rc6->bios_rc_state);
pctx = fetch_and_zero(&rc6->pctx);
if (pctx)
@@ -766,18 +761,18 @@ static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg)
* before we have set the default VLV_COUNTER_CONTROL value. So always
* set the high bit to be safe.
*/
- set(uncore, VLV_COUNTER_CONTROL,
- _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
+ intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
+ _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
upper = intel_uncore_read_fw(uncore, reg);
do {
tmp = upper;
- set(uncore, VLV_COUNTER_CONTROL,
- _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
+ intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
+ _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
lower = intel_uncore_read_fw(uncore, reg);
- set(uncore, VLV_COUNTER_CONTROL,
- _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
+ intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
+ _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
upper = intel_uncore_read_fw(uncore, reg);
} while (upper != tmp && --loop);
--
2.39.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/rc6: throw out set() wrapper
2023-04-21 13:59 [Intel-gfx] [PATCH] drm/i915/rc6: throw out set() wrapper Jani Nikula
@ 2023-04-21 14:52 ` Matt Roper
2023-05-02 9:59 ` Jani Nikula
2023-04-21 15:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
` (3 subsequent siblings)
4 siblings, 1 reply; 7+ messages in thread
From: Matt Roper @ 2023-04-21 14:52 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
On Fri, Apr 21, 2023 at 04:59:48PM +0300, Jani Nikula wrote:
> Remove useless indirection that's just misdirection for the readers.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_rc6.c | 157 ++++++++++++++--------------
> 1 file changed, 76 insertions(+), 81 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index 8f3cd68d14f8..908a3d0f2343 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -53,11 +53,6 @@ static struct drm_i915_private *rc6_to_i915(struct intel_rc6 *rc)
> return rc6_to_gt(rc)->i915;
> }
>
> -static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)
> -{
> - intel_uncore_write_fw(uncore, reg, val);
> -}
> -
> static void gen11_rc6_enable(struct intel_rc6 *rc6)
> {
> struct intel_gt *gt = rc6_to_gt(rc6);
> @@ -72,19 +67,19 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
> */
> if (!intel_uc_uses_guc_rc(>->uc)) {
> /* 2b: Program RC6 thresholds.*/
> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
> - set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
> + intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
>
> - set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> - set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> + intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> + intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> for_each_engine(engine, rc6_to_gt(rc6), id)
> - set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
> + intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>
> - set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
> + intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
>
> - set(uncore, GEN6_RC_SLEEP, 0);
> + intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
>
> - set(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
> + intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
> }
>
> /*
> @@ -105,8 +100,8 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
> * Broadwell+, To be conservative, we want to factor in a context
> * switch on top (due to ksoftirqd).
> */
> - set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
> - set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
> + intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
> + intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
>
> /* 3a: Enable RC6
> *
> @@ -141,7 +136,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
> VDN_MFX_POWERGATE_ENABLE(i));
> }
>
> - set(uncore, GEN9_PG_ENABLE, pg_enable);
> + intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, pg_enable);
> }
>
> static void gen9_rc6_enable(struct intel_rc6 *rc6)
> @@ -152,26 +147,26 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
>
> /* 2b: Program RC6 thresholds.*/
> if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 11) {
> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
> - set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
> + intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
> } else if (IS_SKYLAKE(rc6_to_i915(rc6))) {
> /*
> * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
> * when CPG is enabled
> */
> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
> } else {
> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
> }
>
> - set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> - set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> + intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> + intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> for_each_engine(engine, rc6_to_gt(rc6), id)
> - set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
> + intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>
> - set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
> + intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
>
> - set(uncore, GEN6_RC_SLEEP, 0);
> + intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
>
> /*
> * 2c: Program Coarse Power Gating Policies.
> @@ -194,11 +189,11 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
> * conservative, we have to factor in a context switch on top (due
> * to ksoftirqd).
> */
> - set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
> - set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
> + intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
> + intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
>
> /* 3a: Enable RC6 */
> - set(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
> + intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
>
> rc6->ctl_enable =
> GEN6_RC_CTL_HW_ENABLE |
> @@ -210,8 +205,8 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
> * - Render/Media PG need to be disabled with RC6.
> */
> if (!NEEDS_WaRsDisableCoarsePowerGating(rc6_to_i915(rc6)))
> - set(uncore, GEN9_PG_ENABLE,
> - GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
> + intel_uncore_write_fw(uncore, GEN9_PG_ENABLE,
> + GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
> }
>
> static void gen8_rc6_enable(struct intel_rc6 *rc6)
> @@ -221,13 +216,13 @@ static void gen8_rc6_enable(struct intel_rc6 *rc6)
> enum intel_engine_id id;
>
> /* 2b: Program RC6 thresholds.*/
> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
> - set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> - set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
> + intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> + intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> for_each_engine(engine, rc6_to_gt(rc6), id)
> - set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
> - set(uncore, GEN6_RC_SLEEP, 0);
> - set(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
> + intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
> + intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
> + intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
>
> /* 3: Enable RC6 */
> rc6->ctl_enable =
> @@ -245,20 +240,20 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
> u32 rc6vids, rc6_mask;
> int ret;
>
> - set(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
> - set(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
> - set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
> - set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
> + intel_uncore_write_fw(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
> + intel_uncore_write_fw(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
> + intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
> + intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
>
> for_each_engine(engine, rc6_to_gt(rc6), id)
> - set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
> + intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>
> - set(uncore, GEN6_RC_SLEEP, 0);
> - set(uncore, GEN6_RC1e_THRESHOLD, 1000);
> - set(uncore, GEN6_RC6_THRESHOLD, 50000);
> - set(uncore, GEN6_RC6p_THRESHOLD, 150000);
> - set(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */
> + intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
> + intel_uncore_write_fw(uncore, GEN6_RC1e_THRESHOLD, 1000);
> + intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000);
> + intel_uncore_write_fw(uncore, GEN6_RC6p_THRESHOLD, 150000);
> + intel_uncore_write_fw(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */
>
> /* We don't use those on Haswell */
> rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
> @@ -372,22 +367,22 @@ static void chv_rc6_enable(struct intel_rc6 *rc6)
> enum intel_engine_id id;
>
> /* 2a: Program RC6 thresholds.*/
> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
> - set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> - set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
> + intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> + intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
>
> for_each_engine(engine, rc6_to_gt(rc6), id)
> - set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
> - set(uncore, GEN6_RC_SLEEP, 0);
> + intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
> + intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
>
> /* TO threshold set to 500 us (0x186 * 1.28 us) */
> - set(uncore, GEN6_RC6_THRESHOLD, 0x186);
> + intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x186);
>
> /* Allows RC6 residency counter to work */
> - set(uncore, VLV_COUNTER_CONTROL,
> - _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
> - VLV_MEDIA_RC6_COUNT_EN |
> - VLV_RENDER_RC6_COUNT_EN));
> + intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
> + _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
> + VLV_MEDIA_RC6_COUNT_EN |
> + VLV_RENDER_RC6_COUNT_EN));
>
> /* 3: Enable RC6 */
> rc6->ctl_enable = GEN7_RC_CTL_TO_MODE;
> @@ -399,22 +394,22 @@ static void vlv_rc6_enable(struct intel_rc6 *rc6)
> struct intel_engine_cs *engine;
> enum intel_engine_id id;
>
> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
> - set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
> - set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
> + intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
> + intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
>
> for_each_engine(engine, rc6_to_gt(rc6), id)
> - set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
> + intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>
> - set(uncore, GEN6_RC6_THRESHOLD, 0x557);
> + intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x557);
>
> /* Allows RC6 residency counter to work */
> - set(uncore, VLV_COUNTER_CONTROL,
> - _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
> - VLV_MEDIA_RC0_COUNT_EN |
> - VLV_RENDER_RC0_COUNT_EN |
> - VLV_MEDIA_RC6_COUNT_EN |
> - VLV_RENDER_RC6_COUNT_EN));
> + intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
> + _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
> + VLV_MEDIA_RC0_COUNT_EN |
> + VLV_RENDER_RC0_COUNT_EN |
> + VLV_MEDIA_RC6_COUNT_EN |
> + VLV_RENDER_RC6_COUNT_EN));
>
> rc6->ctl_enable =
> GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
> @@ -575,9 +570,9 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
>
> intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> if (GRAPHICS_VER(i915) >= 9)
> - set(uncore, GEN9_PG_ENABLE, 0);
> - set(uncore, GEN6_RC_CONTROL, 0);
> - set(uncore, GEN6_RC_STATE, 0);
> + intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, 0);
> + intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, 0);
> + intel_uncore_write_fw(uncore, GEN6_RC_STATE, 0);
> intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
> }
>
> @@ -684,7 +679,7 @@ void intel_rc6_unpark(struct intel_rc6 *rc6)
> return;
>
> /* Restore HW timers for automatic RC6 entry while busy */
> - set(uncore, GEN6_RC_CONTROL, rc6->ctl_enable);
> + intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, rc6->ctl_enable);
> }
>
> void intel_rc6_park(struct intel_rc6 *rc6)
> @@ -704,7 +699,7 @@ void intel_rc6_park(struct intel_rc6 *rc6)
> return;
>
> /* Turn off the HW timers and go directly to rc6 */
> - set(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE);
> + intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE);
>
> if (HAS_RC6pp(rc6_to_i915(rc6)))
> target = 0x6; /* deepest rc6 */
> @@ -712,7 +707,7 @@ void intel_rc6_park(struct intel_rc6 *rc6)
> target = 0x5; /* deep rc6 */
> else
> target = 0x4; /* normal rc6 */
> - set(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT);
> + intel_uncore_write_fw(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT);
> }
>
> void intel_rc6_disable(struct intel_rc6 *rc6)
> @@ -735,7 +730,7 @@ void intel_rc6_fini(struct intel_rc6 *rc6)
>
> /* We want the BIOS C6 state preserved across loads for MTL */
> if (IS_METEORLAKE(rc6_to_i915(rc6)) && rc6->bios_state_captured)
> - set(uncore, GEN6_RC_STATE, rc6->bios_rc_state);
> + intel_uncore_write_fw(uncore, GEN6_RC_STATE, rc6->bios_rc_state);
>
> pctx = fetch_and_zero(&rc6->pctx);
> if (pctx)
> @@ -766,18 +761,18 @@ static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg)
> * before we have set the default VLV_COUNTER_CONTROL value. So always
> * set the high bit to be safe.
> */
> - set(uncore, VLV_COUNTER_CONTROL,
> - _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
> + intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
> + _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
> upper = intel_uncore_read_fw(uncore, reg);
> do {
> tmp = upper;
>
> - set(uncore, VLV_COUNTER_CONTROL,
> - _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
> + intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
> + _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
> lower = intel_uncore_read_fw(uncore, reg);
>
> - set(uncore, VLV_COUNTER_CONTROL,
> - _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
> + intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
> + _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
> upper = intel_uncore_read_fw(uncore, reg);
> } while (upper != tmp && --loop);
>
> --
> 2.39.2
>
--
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/rc6: throw out set() wrapper
2023-04-21 13:59 [Intel-gfx] [PATCH] drm/i915/rc6: throw out set() wrapper Jani Nikula
2023-04-21 14:52 ` Matt Roper
@ 2023-04-21 15:49 ` Patchwork
2023-04-21 16:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2023-04-21 15:49 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/rc6: throw out set() wrapper
URL : https://patchwork.freedesktop.org/series/116817/
State : warning
== Summary ==
Error: dim checkpatch failed
df045eca0cc1 drm/i915/rc6: throw out set() wrapper
-:38: WARNING:LONG_LINE_COMMENT: line length of 104 exceeds 100 columns
#38: FILE: drivers/gpu/drm/i915/gt/intel_rc6.c:73:
+ intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
total: 0 errors, 1 warnings, 0 checks, 298 lines checked
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/rc6: throw out set() wrapper
2023-04-21 13:59 [Intel-gfx] [PATCH] drm/i915/rc6: throw out set() wrapper Jani Nikula
2023-04-21 14:52 ` Matt Roper
2023-04-21 15:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2023-04-21 16:02 ` Patchwork
2023-04-22 0:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-04-24 6:43 ` [Intel-gfx] [PATCH] " Andrzej Hajda
4 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2023-04-21 16:02 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 4302 bytes --]
== Series Details ==
Series: drm/i915/rc6: throw out set() wrapper
URL : https://patchwork.freedesktop.org/series/116817/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13041 -> Patchwork_116817v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/index.html
Participating hosts (37 -> 36)
------------------------------
Missing (1): fi-snb-2520m
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_116817v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@hugepages:
- {bat-mtlp-8}: NOTRUN -> [DMESG-FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/bat-mtlp-8/igt@i915_selftest@live@hugepages.html
Known issues
------------
Here are the changes found in Patchwork_116817v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@gt_heartbeat:
- fi-apl-guc: [PASS][2] -> [DMESG-FAIL][3] ([i915#5334])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/fi-apl-guc/igt@i915_selftest@live@gt_heartbeat.html
#### Possible fixes ####
* igt@gem_exec_parallel@engines@basic:
- {bat-mtlp-8}: [FAIL][4] -> [PASS][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/bat-mtlp-8/igt@gem_exec_parallel@engines@basic.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/bat-mtlp-8/igt@gem_exec_parallel@engines@basic.html
* igt@i915_selftest@live@requests:
- {bat-mtlp-8}: [ABORT][6] ([i915#4983]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/bat-mtlp-8/igt@i915_selftest@live@requests.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/bat-mtlp-8/igt@i915_selftest@live@requests.html
* igt@i915_suspend@basic-s2idle-without-i915:
- fi-bsw-n3050: [DMESG-WARN][8] ([i915#1982]) -> [PASS][9]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/fi-bsw-n3050/igt@i915_suspend@basic-s2idle-without-i915.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/fi-bsw-n3050/igt@i915_suspend@basic-s2idle-without-i915.html
#### Warnings ####
* igt@i915_selftest@live@slpc:
- bat-rpls-1: [DMESG-FAIL][10] ([i915#6997]) -> [DMESG-FAIL][11] ([i915#6367] / [i915#7996])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/bat-rpls-1/igt@i915_selftest@live@slpc.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/bat-rpls-1/igt@i915_selftest@live@slpc.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#6367]: https://gitlab.freedesktop.org/drm/intel/issues/6367
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#6997]: https://gitlab.freedesktop.org/drm/intel/issues/6997
[i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7996]: https://gitlab.freedesktop.org/drm/intel/issues/7996
Build changes
-------------
* Linux: CI_DRM_13041 -> Patchwork_116817v1
CI-20190529: 20190529
CI_DRM_13041: a172f81b6b3534fd9e5c1e0f25764fceabdd8343 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7264: 2f0a07378e58e5c7d7b589b39ace7e3a2317f6b2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116817v1: a172f81b6b3534fd9e5c1e0f25764fceabdd8343 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
5df3ab695ba2 drm/i915/rc6: throw out set() wrapper
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/index.html
[-- Attachment #2: Type: text/html, Size: 4845 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/rc6: throw out set() wrapper
2023-04-21 13:59 [Intel-gfx] [PATCH] drm/i915/rc6: throw out set() wrapper Jani Nikula
` (2 preceding siblings ...)
2023-04-21 16:02 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-04-22 0:18 ` Patchwork
2023-04-24 6:43 ` [Intel-gfx] [PATCH] " Andrzej Hajda
4 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2023-04-22 0:18 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 14141 bytes --]
== Series Details ==
Series: drm/i915/rc6: throw out set() wrapper
URL : https://patchwork.freedesktop.org/series/116817/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13041_full -> Patchwork_116817v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_116817v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_116817v1_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (7 -> 7)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_116817v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@gem_ppgtt@blt-vs-render-ctx0:
- shard-snb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-snb1/igt@gem_ppgtt@blt-vs-render-ctx0.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-snb1/igt@gem_ppgtt@blt-vs-render-ctx0.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-apl: [PASS][3] -> [FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-apl3/igt@gem_ppgtt@flink-and-close-vma-leak.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-apl7/igt@gem_ppgtt@flink-and-close-vma-leak.html
Known issues
------------
Here are the changes found in Patchwork_116817v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][5] -> [FAIL][6] ([i915#2842])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-glk2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_huc_copy@huc-copy:
- shard-glk: NOTRUN -> [SKIP][7] ([fdo#109271] / [i915#2190])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-glk8/igt@gem_huc_copy@huc-copy.html
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [PASS][8] -> [ABORT][9] ([i915#5566])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-glk9/igt@gen9_exec_parse@allowed-all.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-glk3/igt@gen9_exec_parse@allowed-all.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-1:
- shard-apl: [PASS][10] -> [FAIL][11] ([i915#2521])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-apl3/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-1.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-apl7/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-dp-1.html
* igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling@pipe-b-vga-1:
- shard-snb: NOTRUN -> [SKIP][12] ([fdo#109271]) +7 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-snb5/igt@kms_plane_scaling@planes-downscale-factor-0-75-unity-scaling@pipe-b-vga-1.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb:
- shard-glk: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#658])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-glk8/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html
* igt@v3d/v3d_submit_csd@bad-multisync-in-sync:
- shard-glk: NOTRUN -> [SKIP][14] ([fdo#109271]) +11 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-glk8/igt@v3d/v3d_submit_csd@bad-multisync-in-sync.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][15] ([i915#2846]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-glk1/igt@gem_exec_fair@basic-deadline.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-glk4/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@bcs0:
- {shard-rkl}: [FAIL][17] ([i915#2842]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-rkl-3/igt@gem_exec_fair@basic-none@bcs0.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-rkl-4/igt@gem_exec_fair@basic-none@bcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-apl: [FAIL][19] ([i915#2842]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-apl6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-apl6/igt@gem_exec_fair@basic-pace-share@rcs0.html
- {shard-tglu}: [FAIL][21] ([i915#2842]) -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-tglu-4/igt@gem_exec_fair@basic-pace-share@rcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-tglu-4/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-glk: [FAIL][23] ([i915#2842]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-glk9/igt@gem_exec_fair@basic-pace@vecs0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-glk3/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- {shard-rkl}: [SKIP][25] ([i915#1397]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-rkl-7/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-rkl-1/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@i915_selftest@live@gt_heartbeat:
- shard-apl: [DMESG-FAIL][27] ([i915#5334]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-apl3/igt@i915_selftest@live@gt_heartbeat.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-apl7/igt@i915_selftest@live@gt_heartbeat.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-apl: [FAIL][29] ([i915#2346]) -> [PASS][30] +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-apl4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-apl3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_cursor_legacy@single-bo@pipe-b:
- {shard-rkl}: [INCOMPLETE][31] ([i915#8011]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-rkl-7/igt@kms_cursor_legacy@single-bo@pipe-b.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-rkl-1/igt@kms_cursor_legacy@single-bo@pipe-b.html
* igt@kms_plane_scaling@i915-max-src-size@pipe-a-hdmi-a-2:
- {shard-rkl}: [FAIL][33] ([i915#8292]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13041/shard-rkl-3/igt@kms_plane_scaling@i915-max-src-size@pipe-a-hdmi-a-2.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/shard-rkl-4/igt@kms_plane_scaling@i915-max-src-size@pipe-a-hdmi-a-2.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3989]: https://gitlab.freedesktop.org/drm/intel/issues/3989
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#4565]: https://gitlab.freedesktop.org/drm/intel/issues/4565
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4816]: https://gitlab.freedesktop.org/drm/intel/issues/4816
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4958]: https://gitlab.freedesktop.org/drm/intel/issues/4958
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
[i915#6301]: https://gitlab.freedesktop.org/drm/intel/issues/6301
[i915#6334]: https://gitlab.freedesktop.org/drm/intel/issues/6334
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#6590]: https://gitlab.freedesktop.org/drm/intel/issues/6590
[i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
[i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8011]: https://gitlab.freedesktop.org/drm/intel/issues/8011
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8347]: https://gitlab.freedesktop.org/drm/intel/issues/8347
[i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
Build changes
-------------
* Linux: CI_DRM_13041 -> Patchwork_116817v1
CI-20190529: 20190529
CI_DRM_13041: a172f81b6b3534fd9e5c1e0f25764fceabdd8343 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7264: 2f0a07378e58e5c7d7b589b39ace7e3a2317f6b2 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_116817v1: a172f81b6b3534fd9e5c1e0f25764fceabdd8343 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_116817v1/index.html
[-- Attachment #2: Type: text/html, Size: 10743 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/rc6: throw out set() wrapper
2023-04-21 13:59 [Intel-gfx] [PATCH] drm/i915/rc6: throw out set() wrapper Jani Nikula
` (3 preceding siblings ...)
2023-04-22 0:18 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2023-04-24 6:43 ` Andrzej Hajda
4 siblings, 0 replies; 7+ messages in thread
From: Andrzej Hajda @ 2023-04-24 6:43 UTC (permalink / raw)
To: Jani Nikula, intel-gfx
On 21.04.2023 15:59, Jani Nikula wrote:
> Remove useless indirection that's just misdirection for the readers.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_rc6.c | 157 ++++++++++++++--------------
> 1 file changed, 76 insertions(+), 81 deletions(-)
Reviewed-by: Andrzej Hajda <andrzej.hajda@intel.com>
Regards
Andrzej
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index 8f3cd68d14f8..908a3d0f2343 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -53,11 +53,6 @@ static struct drm_i915_private *rc6_to_i915(struct intel_rc6 *rc)
> return rc6_to_gt(rc)->i915;
> }
>
> -static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)
> -{
> - intel_uncore_write_fw(uncore, reg, val);
> -}
> -
> static void gen11_rc6_enable(struct intel_rc6 *rc6)
> {
> struct intel_gt *gt = rc6_to_gt(rc6);
> @@ -72,19 +67,19 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
> */
> if (!intel_uc_uses_guc_rc(>->uc)) {
> /* 2b: Program RC6 thresholds.*/
> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
> - set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
> + intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
>
> - set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> - set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> + intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> + intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> for_each_engine(engine, rc6_to_gt(rc6), id)
> - set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
> + intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>
> - set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
> + intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
>
> - set(uncore, GEN6_RC_SLEEP, 0);
> + intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
>
> - set(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
> + intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
> }
>
> /*
> @@ -105,8 +100,8 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
> * Broadwell+, To be conservative, we want to factor in a context
> * switch on top (due to ksoftirqd).
> */
> - set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
> - set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
> + intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
> + intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
>
> /* 3a: Enable RC6
> *
> @@ -141,7 +136,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
> VDN_MFX_POWERGATE_ENABLE(i));
> }
>
> - set(uncore, GEN9_PG_ENABLE, pg_enable);
> + intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, pg_enable);
> }
>
> static void gen9_rc6_enable(struct intel_rc6 *rc6)
> @@ -152,26 +147,26 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
>
> /* 2b: Program RC6 thresholds.*/
> if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 11) {
> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
> - set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
> + intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
> } else if (IS_SKYLAKE(rc6_to_i915(rc6))) {
> /*
> * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
> * when CPG is enabled
> */
> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
> } else {
> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
> }
>
> - set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> - set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> + intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> + intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> for_each_engine(engine, rc6_to_gt(rc6), id)
> - set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
> + intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>
> - set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
> + intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
>
> - set(uncore, GEN6_RC_SLEEP, 0);
> + intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
>
> /*
> * 2c: Program Coarse Power Gating Policies.
> @@ -194,11 +189,11 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
> * conservative, we have to factor in a context switch on top (due
> * to ksoftirqd).
> */
> - set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
> - set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
> + intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
> + intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
>
> /* 3a: Enable RC6 */
> - set(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
> + intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
>
> rc6->ctl_enable =
> GEN6_RC_CTL_HW_ENABLE |
> @@ -210,8 +205,8 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
> * - Render/Media PG need to be disabled with RC6.
> */
> if (!NEEDS_WaRsDisableCoarsePowerGating(rc6_to_i915(rc6)))
> - set(uncore, GEN9_PG_ENABLE,
> - GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
> + intel_uncore_write_fw(uncore, GEN9_PG_ENABLE,
> + GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
> }
>
> static void gen8_rc6_enable(struct intel_rc6 *rc6)
> @@ -221,13 +216,13 @@ static void gen8_rc6_enable(struct intel_rc6 *rc6)
> enum intel_engine_id id;
>
> /* 2b: Program RC6 thresholds.*/
> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
> - set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> - set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
> + intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> + intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> for_each_engine(engine, rc6_to_gt(rc6), id)
> - set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
> - set(uncore, GEN6_RC_SLEEP, 0);
> - set(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
> + intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
> + intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
> + intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
>
> /* 3: Enable RC6 */
> rc6->ctl_enable =
> @@ -245,20 +240,20 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
> u32 rc6vids, rc6_mask;
> int ret;
>
> - set(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
> - set(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
> - set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
> - set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
> + intel_uncore_write_fw(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
> + intel_uncore_write_fw(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
> + intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
> + intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
>
> for_each_engine(engine, rc6_to_gt(rc6), id)
> - set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
> + intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>
> - set(uncore, GEN6_RC_SLEEP, 0);
> - set(uncore, GEN6_RC1e_THRESHOLD, 1000);
> - set(uncore, GEN6_RC6_THRESHOLD, 50000);
> - set(uncore, GEN6_RC6p_THRESHOLD, 150000);
> - set(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */
> + intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
> + intel_uncore_write_fw(uncore, GEN6_RC1e_THRESHOLD, 1000);
> + intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000);
> + intel_uncore_write_fw(uncore, GEN6_RC6p_THRESHOLD, 150000);
> + intel_uncore_write_fw(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */
>
> /* We don't use those on Haswell */
> rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
> @@ -372,22 +367,22 @@ static void chv_rc6_enable(struct intel_rc6 *rc6)
> enum intel_engine_id id;
>
> /* 2a: Program RC6 thresholds.*/
> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
> - set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> - set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
> + intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
> + intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
>
> for_each_engine(engine, rc6_to_gt(rc6), id)
> - set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
> - set(uncore, GEN6_RC_SLEEP, 0);
> + intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
> + intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
>
> /* TO threshold set to 500 us (0x186 * 1.28 us) */
> - set(uncore, GEN6_RC6_THRESHOLD, 0x186);
> + intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x186);
>
> /* Allows RC6 residency counter to work */
> - set(uncore, VLV_COUNTER_CONTROL,
> - _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
> - VLV_MEDIA_RC6_COUNT_EN |
> - VLV_RENDER_RC6_COUNT_EN));
> + intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
> + _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
> + VLV_MEDIA_RC6_COUNT_EN |
> + VLV_RENDER_RC6_COUNT_EN));
>
> /* 3: Enable RC6 */
> rc6->ctl_enable = GEN7_RC_CTL_TO_MODE;
> @@ -399,22 +394,22 @@ static void vlv_rc6_enable(struct intel_rc6 *rc6)
> struct intel_engine_cs *engine;
> enum intel_engine_id id;
>
> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
> - set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
> - set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
> + intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
> + intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
>
> for_each_engine(engine, rc6_to_gt(rc6), id)
> - set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
> + intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>
> - set(uncore, GEN6_RC6_THRESHOLD, 0x557);
> + intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x557);
>
> /* Allows RC6 residency counter to work */
> - set(uncore, VLV_COUNTER_CONTROL,
> - _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
> - VLV_MEDIA_RC0_COUNT_EN |
> - VLV_RENDER_RC0_COUNT_EN |
> - VLV_MEDIA_RC6_COUNT_EN |
> - VLV_RENDER_RC6_COUNT_EN));
> + intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
> + _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
> + VLV_MEDIA_RC0_COUNT_EN |
> + VLV_RENDER_RC0_COUNT_EN |
> + VLV_MEDIA_RC6_COUNT_EN |
> + VLV_RENDER_RC6_COUNT_EN));
>
> rc6->ctl_enable =
> GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
> @@ -575,9 +570,9 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
>
> intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
> if (GRAPHICS_VER(i915) >= 9)
> - set(uncore, GEN9_PG_ENABLE, 0);
> - set(uncore, GEN6_RC_CONTROL, 0);
> - set(uncore, GEN6_RC_STATE, 0);
> + intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, 0);
> + intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, 0);
> + intel_uncore_write_fw(uncore, GEN6_RC_STATE, 0);
> intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
> }
>
> @@ -684,7 +679,7 @@ void intel_rc6_unpark(struct intel_rc6 *rc6)
> return;
>
> /* Restore HW timers for automatic RC6 entry while busy */
> - set(uncore, GEN6_RC_CONTROL, rc6->ctl_enable);
> + intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, rc6->ctl_enable);
> }
>
> void intel_rc6_park(struct intel_rc6 *rc6)
> @@ -704,7 +699,7 @@ void intel_rc6_park(struct intel_rc6 *rc6)
> return;
>
> /* Turn off the HW timers and go directly to rc6 */
> - set(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE);
> + intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE);
>
> if (HAS_RC6pp(rc6_to_i915(rc6)))
> target = 0x6; /* deepest rc6 */
> @@ -712,7 +707,7 @@ void intel_rc6_park(struct intel_rc6 *rc6)
> target = 0x5; /* deep rc6 */
> else
> target = 0x4; /* normal rc6 */
> - set(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT);
> + intel_uncore_write_fw(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT);
> }
>
> void intel_rc6_disable(struct intel_rc6 *rc6)
> @@ -735,7 +730,7 @@ void intel_rc6_fini(struct intel_rc6 *rc6)
>
> /* We want the BIOS C6 state preserved across loads for MTL */
> if (IS_METEORLAKE(rc6_to_i915(rc6)) && rc6->bios_state_captured)
> - set(uncore, GEN6_RC_STATE, rc6->bios_rc_state);
> + intel_uncore_write_fw(uncore, GEN6_RC_STATE, rc6->bios_rc_state);
>
> pctx = fetch_and_zero(&rc6->pctx);
> if (pctx)
> @@ -766,18 +761,18 @@ static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg)
> * before we have set the default VLV_COUNTER_CONTROL value. So always
> * set the high bit to be safe.
> */
> - set(uncore, VLV_COUNTER_CONTROL,
> - _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
> + intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
> + _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
> upper = intel_uncore_read_fw(uncore, reg);
> do {
> tmp = upper;
>
> - set(uncore, VLV_COUNTER_CONTROL,
> - _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
> + intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
> + _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
> lower = intel_uncore_read_fw(uncore, reg);
>
> - set(uncore, VLV_COUNTER_CONTROL,
> - _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
> + intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
> + _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
> upper = intel_uncore_read_fw(uncore, reg);
> } while (upper != tmp && --loop);
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/rc6: throw out set() wrapper
2023-04-21 14:52 ` Matt Roper
@ 2023-05-02 9:59 ` Jani Nikula
0 siblings, 0 replies; 7+ messages in thread
From: Jani Nikula @ 2023-05-02 9:59 UTC (permalink / raw)
To: Matt Roper; +Cc: intel-gfx, Andrzej Hajda
On Fri, 21 Apr 2023, Matt Roper <matthew.d.roper@intel.com> wrote:
> On Fri, Apr 21, 2023 at 04:59:48PM +0300, Jani Nikula wrote:
>> Remove useless indirection that's just misdirection for the readers.
>>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Thanks for the reviews, pushed to drm-intel-gt-next.
BR,
Jani.
>
>> ---
>> drivers/gpu/drm/i915/gt/intel_rc6.c | 157 ++++++++++++++--------------
>> 1 file changed, 76 insertions(+), 81 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
>> index 8f3cd68d14f8..908a3d0f2343 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
>> @@ -53,11 +53,6 @@ static struct drm_i915_private *rc6_to_i915(struct intel_rc6 *rc)
>> return rc6_to_gt(rc)->i915;
>> }
>>
>> -static void set(struct intel_uncore *uncore, i915_reg_t reg, u32 val)
>> -{
>> - intel_uncore_write_fw(uncore, reg, val);
>> -}
>> -
>> static void gen11_rc6_enable(struct intel_rc6 *rc6)
>> {
>> struct intel_gt *gt = rc6_to_gt(rc6);
>> @@ -72,19 +67,19 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
>> */
>> if (!intel_uc_uses_guc_rc(>->uc)) {
>> /* 2b: Program RC6 thresholds.*/
>> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
>> - set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
>> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
>> + intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
>>
>> - set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
>> - set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
>> + intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
>> + intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
>> for_each_engine(engine, rc6_to_gt(rc6), id)
>> - set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>> + intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>>
>> - set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
>> + intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
>>
>> - set(uncore, GEN6_RC_SLEEP, 0);
>> + intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
>>
>> - set(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
>> + intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
>> }
>>
>> /*
>> @@ -105,8 +100,8 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
>> * Broadwell+, To be conservative, we want to factor in a context
>> * switch on top (due to ksoftirqd).
>> */
>> - set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
>> - set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
>> + intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
>> + intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
>>
>> /* 3a: Enable RC6
>> *
>> @@ -141,7 +136,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
>> VDN_MFX_POWERGATE_ENABLE(i));
>> }
>>
>> - set(uncore, GEN9_PG_ENABLE, pg_enable);
>> + intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, pg_enable);
>> }
>>
>> static void gen9_rc6_enable(struct intel_rc6 *rc6)
>> @@ -152,26 +147,26 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
>>
>> /* 2b: Program RC6 thresholds.*/
>> if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 11) {
>> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
>> - set(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
>> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
>> + intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
>> } else if (IS_SKYLAKE(rc6_to_i915(rc6))) {
>> /*
>> * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
>> * when CPG is enabled
>> */
>> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
>> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
>> } else {
>> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
>> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
>> }
>>
>> - set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
>> - set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
>> + intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
>> + intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
>> for_each_engine(engine, rc6_to_gt(rc6), id)
>> - set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>> + intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>>
>> - set(uncore, GUC_MAX_IDLE_COUNT, 0xA);
>> + intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
>>
>> - set(uncore, GEN6_RC_SLEEP, 0);
>> + intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
>>
>> /*
>> * 2c: Program Coarse Power Gating Policies.
>> @@ -194,11 +189,11 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
>> * conservative, we have to factor in a context switch on top (due
>> * to ksoftirqd).
>> */
>> - set(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
>> - set(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
>> + intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
>> + intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
>>
>> /* 3a: Enable RC6 */
>> - set(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
>> + intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
>>
>> rc6->ctl_enable =
>> GEN6_RC_CTL_HW_ENABLE |
>> @@ -210,8 +205,8 @@ static void gen9_rc6_enable(struct intel_rc6 *rc6)
>> * - Render/Media PG need to be disabled with RC6.
>> */
>> if (!NEEDS_WaRsDisableCoarsePowerGating(rc6_to_i915(rc6)))
>> - set(uncore, GEN9_PG_ENABLE,
>> - GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
>> + intel_uncore_write_fw(uncore, GEN9_PG_ENABLE,
>> + GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
>> }
>>
>> static void gen8_rc6_enable(struct intel_rc6 *rc6)
>> @@ -221,13 +216,13 @@ static void gen8_rc6_enable(struct intel_rc6 *rc6)
>> enum intel_engine_id id;
>>
>> /* 2b: Program RC6 thresholds.*/
>> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
>> - set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
>> - set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
>> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
>> + intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
>> + intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
>> for_each_engine(engine, rc6_to_gt(rc6), id)
>> - set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>> - set(uncore, GEN6_RC_SLEEP, 0);
>> - set(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
>> + intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>> + intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
>> + intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
>>
>> /* 3: Enable RC6 */
>> rc6->ctl_enable =
>> @@ -245,20 +240,20 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
>> u32 rc6vids, rc6_mask;
>> int ret;
>>
>> - set(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
>> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
>> - set(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
>> - set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
>> - set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
>> + intel_uncore_write_fw(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
>> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
>> + intel_uncore_write_fw(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
>> + intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
>> + intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
>>
>> for_each_engine(engine, rc6_to_gt(rc6), id)
>> - set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>> + intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>>
>> - set(uncore, GEN6_RC_SLEEP, 0);
>> - set(uncore, GEN6_RC1e_THRESHOLD, 1000);
>> - set(uncore, GEN6_RC6_THRESHOLD, 50000);
>> - set(uncore, GEN6_RC6p_THRESHOLD, 150000);
>> - set(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */
>> + intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
>> + intel_uncore_write_fw(uncore, GEN6_RC1e_THRESHOLD, 1000);
>> + intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000);
>> + intel_uncore_write_fw(uncore, GEN6_RC6p_THRESHOLD, 150000);
>> + intel_uncore_write_fw(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */
>>
>> /* We don't use those on Haswell */
>> rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
>> @@ -372,22 +367,22 @@ static void chv_rc6_enable(struct intel_rc6 *rc6)
>> enum intel_engine_id id;
>>
>> /* 2a: Program RC6 thresholds.*/
>> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
>> - set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
>> - set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
>> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
>> + intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
>> + intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
>>
>> for_each_engine(engine, rc6_to_gt(rc6), id)
>> - set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>> - set(uncore, GEN6_RC_SLEEP, 0);
>> + intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>> + intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
>>
>> /* TO threshold set to 500 us (0x186 * 1.28 us) */
>> - set(uncore, GEN6_RC6_THRESHOLD, 0x186);
>> + intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x186);
>>
>> /* Allows RC6 residency counter to work */
>> - set(uncore, VLV_COUNTER_CONTROL,
>> - _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
>> - VLV_MEDIA_RC6_COUNT_EN |
>> - VLV_RENDER_RC6_COUNT_EN));
>> + intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
>> + _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
>> + VLV_MEDIA_RC6_COUNT_EN |
>> + VLV_RENDER_RC6_COUNT_EN));
>>
>> /* 3: Enable RC6 */
>> rc6->ctl_enable = GEN7_RC_CTL_TO_MODE;
>> @@ -399,22 +394,22 @@ static void vlv_rc6_enable(struct intel_rc6 *rc6)
>> struct intel_engine_cs *engine;
>> enum intel_engine_id id;
>>
>> - set(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
>> - set(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
>> - set(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
>> + intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
>> + intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
>> + intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
>>
>> for_each_engine(engine, rc6_to_gt(rc6), id)
>> - set(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>> + intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
>>
>> - set(uncore, GEN6_RC6_THRESHOLD, 0x557);
>> + intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x557);
>>
>> /* Allows RC6 residency counter to work */
>> - set(uncore, VLV_COUNTER_CONTROL,
>> - _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
>> - VLV_MEDIA_RC0_COUNT_EN |
>> - VLV_RENDER_RC0_COUNT_EN |
>> - VLV_MEDIA_RC6_COUNT_EN |
>> - VLV_RENDER_RC6_COUNT_EN));
>> + intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
>> + _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
>> + VLV_MEDIA_RC0_COUNT_EN |
>> + VLV_RENDER_RC0_COUNT_EN |
>> + VLV_MEDIA_RC6_COUNT_EN |
>> + VLV_RENDER_RC6_COUNT_EN));
>>
>> rc6->ctl_enable =
>> GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
>> @@ -575,9 +570,9 @@ static void __intel_rc6_disable(struct intel_rc6 *rc6)
>>
>> intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
>> if (GRAPHICS_VER(i915) >= 9)
>> - set(uncore, GEN9_PG_ENABLE, 0);
>> - set(uncore, GEN6_RC_CONTROL, 0);
>> - set(uncore, GEN6_RC_STATE, 0);
>> + intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, 0);
>> + intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, 0);
>> + intel_uncore_write_fw(uncore, GEN6_RC_STATE, 0);
>> intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
>> }
>>
>> @@ -684,7 +679,7 @@ void intel_rc6_unpark(struct intel_rc6 *rc6)
>> return;
>>
>> /* Restore HW timers for automatic RC6 entry while busy */
>> - set(uncore, GEN6_RC_CONTROL, rc6->ctl_enable);
>> + intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, rc6->ctl_enable);
>> }
>>
>> void intel_rc6_park(struct intel_rc6 *rc6)
>> @@ -704,7 +699,7 @@ void intel_rc6_park(struct intel_rc6 *rc6)
>> return;
>>
>> /* Turn off the HW timers and go directly to rc6 */
>> - set(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE);
>> + intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE);
>>
>> if (HAS_RC6pp(rc6_to_i915(rc6)))
>> target = 0x6; /* deepest rc6 */
>> @@ -712,7 +707,7 @@ void intel_rc6_park(struct intel_rc6 *rc6)
>> target = 0x5; /* deep rc6 */
>> else
>> target = 0x4; /* normal rc6 */
>> - set(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT);
>> + intel_uncore_write_fw(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT);
>> }
>>
>> void intel_rc6_disable(struct intel_rc6 *rc6)
>> @@ -735,7 +730,7 @@ void intel_rc6_fini(struct intel_rc6 *rc6)
>>
>> /* We want the BIOS C6 state preserved across loads for MTL */
>> if (IS_METEORLAKE(rc6_to_i915(rc6)) && rc6->bios_state_captured)
>> - set(uncore, GEN6_RC_STATE, rc6->bios_rc_state);
>> + intel_uncore_write_fw(uncore, GEN6_RC_STATE, rc6->bios_rc_state);
>>
>> pctx = fetch_and_zero(&rc6->pctx);
>> if (pctx)
>> @@ -766,18 +761,18 @@ static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg)
>> * before we have set the default VLV_COUNTER_CONTROL value. So always
>> * set the high bit to be safe.
>> */
>> - set(uncore, VLV_COUNTER_CONTROL,
>> - _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
>> + intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
>> + _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
>> upper = intel_uncore_read_fw(uncore, reg);
>> do {
>> tmp = upper;
>>
>> - set(uncore, VLV_COUNTER_CONTROL,
>> - _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
>> + intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
>> + _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
>> lower = intel_uncore_read_fw(uncore, reg);
>>
>> - set(uncore, VLV_COUNTER_CONTROL,
>> - _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
>> + intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
>> + _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
>> upper = intel_uncore_read_fw(uncore, reg);
>> } while (upper != tmp && --loop);
>>
>> --
>> 2.39.2
>>
--
Jani Nikula, Intel Open Source Graphics Center
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-05-02 9:59 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
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2023-04-21 13:59 [Intel-gfx] [PATCH] drm/i915/rc6: throw out set() wrapper Jani Nikula
2023-04-21 14:52 ` Matt Roper
2023-05-02 9:59 ` Jani Nikula
2023-04-21 15:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
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