From: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 01/28] drm/i915: Adjust the sentinel assert to match implementation
Date: Tue, 9 Jun 2020 12:45:29 +0100 [thread overview]
Message-ID: <6d257ff7-5699-8a46-63fe-dc4805a876e7@linux.intel.com> (raw)
In-Reply-To: <159169962594.24308.17590896872287208474@build.alporthouse.com>
On 09/06/2020 11:47, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2020-06-09 11:39:11)
>>
>> On 09/06/2020 11:29, Chris Wilson wrote:
>>> Quoting Tvrtko Ursulin (2020-06-09 07:59:27)
>>>> 666
>>>> On 08/06/2020 10:33, Chris Wilson wrote:
>>>>> Quoting Tvrtko Ursulin (2020-06-08 08:44:01)
>>>>>>
>>>>>> On 07/06/2020 23:20, Chris Wilson wrote:
>>>>>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>>>>
>>>>>>> Sentinels are supposed to be last reqeusts in the elsp queue, not the
>>>>>>> only one, so adjust the assert accordingly.
>>>>>>>
>>>>>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>>>> ---
>>>>>>> drivers/gpu/drm/i915/gt/intel_lrc.c | 14 +++-----------
>>>>>>> 1 file changed, 3 insertions(+), 11 deletions(-)
>>>>>>>
>>>>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>>>>>> index d55a5e0466e5..db8a170b0e5c 100644
>>>>>>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>>>>>>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>>>>>>> @@ -1635,9 +1635,9 @@ assert_pending_valid(const struct intel_engine_execlists *execlists,
>>>>>>> ccid = ce->lrc.ccid;
>>>>>>>
>>>>>>> /*
>>>>>>> - * Sentinels are supposed to be lonely so they flush the
>>>>>>> - * current exection off the HW. Check that they are the
>>>>>>> - * only request in the pending submission.
>>>>>>> + * Sentinels are supposed to be the last request so they flush
>>>>>>> + * the current exection off the HW. Check that they are the only
>>>>>>> + * request in the pending submission.
>>>>>>> */
>>>>>>> if (sentinel) {
>>>>>>> GEM_TRACE_ERR("%s: context:%llx after sentinel in pending[%zd]\n",
>>>>>>> @@ -1646,15 +1646,7 @@ assert_pending_valid(const struct intel_engine_execlists *execlists,
>>>>>>> port - execlists->pending);
>>>>>>> return false;
>>>>>>> }
>>>>>>> -
>>>>>>> sentinel = i915_request_has_sentinel(rq);
>>>>>>
>>>>>> FWIW I was changing it to "sentinel |= ..." so it keeps working if we
>>>>>> decide to use more than 2 elsp ports on Icelake one day.
>>>>>
>>>>> But it will always fail on the next port...
>>>>
>>>> I don't follow. Sentinel has to be last so if it fails on the next port
>>>> it is correct to do so, no?
>>>
>>> Exactly. We only check the first port after setting sentinel, if that
>>> port is occupied we fail. Hence why we don't need |=, since there is no
>>> continuation.
>>
>> But if more than two ports we also overwrite the bools so: sentinel,
>> non-sentinel, sentinel would not catch. I was just future proofing it. :)
>
> [0] -> sentinel
> [1] != NULL -> ERROR
>
> [0] -> not sentinel
> [1] -> sentinel
> [2] != NULL -> ERROR
>
> We fail if anything comes after a sentinel.
:) Joke is on me.
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2020-06-09 11:45 UTC|newest]
Thread overview: 51+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-07 22:20 [Intel-gfx] [PATCH 01/28] drm/i915: Adjust the sentinel assert to match implementation Chris Wilson
2020-06-07 22:20 ` [Intel-gfx] [PATCH 02/28] drm/i915/selftests: Make the hanging request non-preemptible Chris Wilson
2020-06-08 20:58 ` Mika Kuoppala
2020-06-07 22:20 ` [Intel-gfx] [PATCH 03/28] drm/i915/selftests: Teach hang-self to target only itself Chris Wilson
2020-06-10 13:21 ` Mika Kuoppala
2020-06-07 22:20 ` [Intel-gfx] [PATCH 04/28] drm/i915/selftests: Remove live_suppress_wait_preempt Chris Wilson
2020-06-11 11:38 ` Tvrtko Ursulin
2020-06-07 22:20 ` [Intel-gfx] [PATCH 05/28] drm/i915/selftests: Trim execlists runtime Chris Wilson
2020-06-12 23:05 ` Andi Shyti
2020-06-07 22:20 ` [Intel-gfx] [PATCH 06/28] drm/i915/gt: Use virtual_engine during execlists_dequeue Chris Wilson
2020-06-07 22:20 ` [Intel-gfx] [PATCH 07/28] drm/i915/gt: Decouple inflight virtual engines Chris Wilson
2020-06-07 22:20 ` [Intel-gfx] [PATCH 08/28] drm/i915/gt: Resubmit the virtual engine on schedule-out Chris Wilson
2020-06-07 22:20 ` [Intel-gfx] [PATCH 09/28] drm/i915: Add list_for_each_entry_safe_continue_reverse Chris Wilson
2020-06-07 22:20 ` [Intel-gfx] [PATCH 10/28] drm/i915/gem: Separate reloc validation into an earlier step Chris Wilson
2020-06-09 7:47 ` Tvrtko Ursulin
2020-06-09 10:48 ` Chris Wilson
2020-06-07 22:20 ` [Intel-gfx] [PATCH 11/28] drm/i915/gem: Lift GPU relocation allocation Chris Wilson
2020-06-07 22:20 ` [Intel-gfx] [PATCH 12/28] drm/i915/gem: Build the reloc request first Chris Wilson
2020-06-07 22:20 ` [Intel-gfx] [PATCH 13/28] drm/i915/gem: Add all GPU reloc awaits/signals en masse Chris Wilson
2020-06-07 22:20 ` [Intel-gfx] [PATCH 14/28] dma-buf: Proxy fence, an unsignaled fence placeholder Chris Wilson
2020-06-07 22:20 ` [Intel-gfx] [PATCH 15/28] drm/i915: Lift waiter/signaler iterators Chris Wilson
2020-06-07 22:20 ` [Intel-gfx] [PATCH 16/28] drm/i915: Unpeel awaits on a proxy fence Chris Wilson
2020-06-07 22:20 ` [Intel-gfx] [PATCH 17/28] drm/i915/gem: Make relocations atomic within execbuf Chris Wilson
2020-06-07 22:20 ` [Intel-gfx] [PATCH 18/28] drm/i915: Strip out internal priorities Chris Wilson
2020-06-07 22:20 ` [Intel-gfx] [PATCH 19/28] drm/i915: Remove I915_USER_PRIORITY_SHIFT Chris Wilson
2020-06-07 22:21 ` [Intel-gfx] [PATCH 20/28] drm/i915: Replace engine->schedule() with a known request operation Chris Wilson
2020-06-07 22:21 ` [Intel-gfx] [PATCH 21/28] drm/i915/gt: Do not suspend bonded requests if one hangs Chris Wilson
2020-06-07 22:21 ` [Intel-gfx] [PATCH 22/28] drm/i915: Teach the i915_dependency to use a double-lock Chris Wilson
2020-06-07 22:21 ` [Intel-gfx] [PATCH 23/28] drm/i915: Restructure priority inheritance Chris Wilson
2020-06-07 22:21 ` [Intel-gfx] [PATCH 24/28] ipi-dag Chris Wilson
2020-06-07 22:21 ` [Intel-gfx] [PATCH 25/28] drm/i915/gt: Check for a completed last request once Chris Wilson
2020-06-07 22:21 ` [Intel-gfx] [PATCH 26/28] drm/i915: Fair low-latency scheduling Chris Wilson
2020-06-16 9:07 ` Thomas Hellström (Intel)
2020-06-16 10:12 ` Chris Wilson
2020-06-16 12:11 ` Thomas Hellström (Intel)
2020-06-16 12:44 ` Chris Wilson
2020-06-16 10:54 ` Chris Wilson
2020-06-07 22:21 ` [Intel-gfx] [PATCH 27/28] drm/i915/gt: Specify a deadline for the heartbeat Chris Wilson
2020-06-07 22:21 ` [Intel-gfx] [PATCH 28/28] drm/i915: Replace the priority boosting for the display with a deadline Chris Wilson
2020-06-07 22:49 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/28] drm/i915: Adjust the sentinel assert to match implementation Patchwork
2020-06-07 22:51 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2020-06-07 23:12 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-06-08 0:58 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-06-08 7:44 ` [Intel-gfx] [PATCH 01/28] " Tvrtko Ursulin
2020-06-08 9:33 ` Chris Wilson
2020-06-09 6:59 ` Tvrtko Ursulin
2020-06-09 10:29 ` Chris Wilson
2020-06-09 10:39 ` Tvrtko Ursulin
2020-06-09 10:47 ` Chris Wilson
2020-06-09 11:45 ` Tvrtko Ursulin [this message]
2020-06-08 20:43 ` Mika Kuoppala
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=6d257ff7-5699-8a46-63fe-dc4805a876e7@linux.intel.com \
--to=tvrtko.ursulin@linux.intel.com \
--cc=chris@chris-wilson.co.uk \
--cc=intel-gfx@lists.freedesktop.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox