[Intel-gfx] [PATCH v7 0/2] drm/i915/mtl: handle some MTL scaler limitations

[Intel-gfx] [PATCH v7 0/2] drm/i915/mtl: handle some MTL scaler limitations

[Luca Coelho]

Hi,

Here's an updated version of the patches after Ville's last comments.
The versioning history is in the patches themselves.

Please review.

Cheers,
Luca.


Animesh Manna (1):
  drm/i915/mtl: update scaler source and destination limits for MTL

Luca Coelho (1):
  drm/i915/mtl: limit second scaler vertical scaling in ver >= 14

 drivers/gpu/drm/i915/display/intel_atomic.c | 85 ++++++++++++++++++---
 drivers/gpu/drm/i915/display/skl_scaler.c   | 40 ++++++++--
 2 files changed, 107 insertions(+), 18 deletions(-)

-- 
2.39.0

[Intel-gfx] [PATCH v7 1/2] drm/i915/mtl: limit second scaler vertical scaling in ver >= 14

[Luca Coelho]

In newer hardware versions (i.e. display version >= 14), the second
scaler doesn't support vertical scaling.

The current implementation of the scaling limits is simplified and
only occurs when the planes are created, so we don't know which scaler
is being used.

In order to handle separate scaling limits for horizontal and vertical
scaling, and different limits per scaler, split the checks in two
phases.  We first do a simple check during plane creation and use the
best-case scenario (because we don't know the scaler that may be used
at a later point) and then do a more specific check when the scalers
are actually being set up.

Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---

In v2:
   * fix DRM_PLANE_NO_SCALING renamed macros;

In v3:
   * No changes.

In v4:
   * Got rid of the changes in the general planes max scale code;
   * Added a couple of FIXMEs;
   * Made intel_atomic_setup_scaler() return an int with errors;

In v5:
   * Just resent with a cover letter.

In v6:
   * Now the correct version again (same as v4).

In v7:
   * Constify a couple of local variables;
   * Return -EINVAL, instead of -EOPNOTSUPP and -EBUSY;
   * Add another FIXME;
   * Remove unnecessary undoing of change in error cases.


 drivers/gpu/drm/i915/display/intel_atomic.c | 85 ++++++++++++++++++---
 1 file changed, 75 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 6621aa245caf..a9a3f3715279 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -41,6 +41,7 @@
 #include "intel_global_state.h"
 #include "intel_hdcp.h"
 #include "intel_psr.h"
+#include "intel_fb.h"
 #include "skl_universal_plane.h"
 
 /**
@@ -310,11 +311,11 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
 	kfree(crtc_state);
 }
 
-static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
-				      int num_scalers_need, struct intel_crtc *intel_crtc,
-				      const char *name, int idx,
-				      struct intel_plane_state *plane_state,
-				      int *scaler_id)
+static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
+				     int num_scalers_need, struct intel_crtc *intel_crtc,
+				     const char *name, int idx,
+				     struct intel_plane_state *plane_state,
+				     int *scaler_id)
 {
 	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
 	int j;
@@ -334,7 +335,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
 
 	if (drm_WARN(&dev_priv->drm, *scaler_id < 0,
 		     "Cannot find scaler for %s:%d\n", name, idx))
-		return;
+		return -EINVAL;
 
 	/* set scaler mode */
 	if (plane_state && plane_state->hw.fb &&
@@ -375,9 +376,71 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
 		mode = SKL_PS_SCALER_MODE_DYN;
 	}
 
+	/*
+	 * FIXME: we should also check the scaler factors for pfit, so
+	 * this shouldn't be tied directly to planes.
+	 */
+	if (plane_state && plane_state->hw.fb) {
+		const struct drm_framebuffer *fb = plane_state->hw.fb;
+		const struct drm_rect *src = &plane_state->uapi.src;
+		const struct drm_rect *dst = &plane_state->uapi.dst;
+		int hscale, vscale, max_vscale, max_hscale;
+
+		/*
+		 * FIXME: When two scalers are needed, but only one of
+		 * them needs to downscale, we should make sure that
+		 * the one that needs downscaling support is assigned
+		 * as the first scaler, so we don't reject downscaling
+		 * unnecessarily.
+		 */
+
+		if (DISPLAY_VER(dev_priv) >= 14) {
+			/*
+			 * On versions 14 and up, only the first
+			 * scaler supports a vertical scaling factor
+			 * of more than 1.0, while a horizontal
+			 * scaling factor of 3.0 is supported.
+			 */
+			max_hscale = 0x30000 - 1;
+			if (*scaler_id == 0)
+				max_vscale = 0x30000 - 1;
+			else
+				max_vscale = 0x10000;
+
+		} else if (DISPLAY_VER(dev_priv) >= 10 ||
+			   !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
+			max_hscale = 0x30000 - 1;
+			max_vscale = 0x30000 - 1;
+		} else {
+			max_hscale = 0x20000 - 1;
+			max_vscale = 0x20000 - 1;
+		}
+
+		/*
+		 * FIXME: We should change the if-else block above to
+		 * support HQ vs dynamic scaler properly.
+		 */
+
+		/* Check if required scaling is within limits */
+		hscale = drm_rect_calc_hscale(src, dst, 1, max_hscale);
+		vscale = drm_rect_calc_vscale(src, dst, 1, max_vscale);
+
+		if (hscale < 0 || vscale < 0) {
+			drm_dbg_kms(&dev_priv->drm,
+				    "Scaler %d doesn't support required plane scaling\n",
+				    *scaler_id);
+			drm_rect_debug_print("src: ", src, true);
+			drm_rect_debug_print("dst: ", dst, false);
+
+			return -EINVAL;
+		}
+	}
+
 	drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n",
 		    intel_crtc->pipe, *scaler_id, name, idx);
 	scaler_state->scalers[*scaler_id].mode = mode;
+
+	return 0;
 }
 
 /**
@@ -437,7 +500,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
 	for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
 		int *scaler_id;
 		const char *name;
-		int idx;
+		int idx, ret;
 
 		/* skip if scaler not required */
 		if (!(scaler_state->scaler_users & (1 << i)))
@@ -494,9 +557,11 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
 			scaler_id = &plane_state->scaler_id;
 		}
 
-		intel_atomic_setup_scaler(scaler_state, num_scalers_need,
-					  intel_crtc, name, idx,
-					  plane_state, scaler_id);
+		ret = intel_atomic_setup_scaler(scaler_state, num_scalers_need,
+						intel_crtc, name, idx,
+						plane_state, scaler_id);
+		if (ret < 0)
+			return ret;
 	}
 
 	return 0;
-- 
2.39.0

[Intel-gfx] [PATCH v7 2/2] drm/i915/mtl: update scaler source and destination limits for MTL

[Luca Coelho]

From: Animesh Manna <animesh.manna@intel.com>

The max source and destination limits for scalers in MTL have changed.
Use the new values accordingly.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Animesh Manna <animesh.manna@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
---

In v2:
   * No changes;

In v3:
   * Removed stray reviewed-by tag;
   * Added my s-o-b.

In v4:
   * No changes.

In v5:
   * Just resent with a cover letter.

In v6:
   * Now the correct version again (same as v4).

In v7:
   * Update to new MTL limits according to the bspec.


 drivers/gpu/drm/i915/display/skl_scaler.c | 40 ++++++++++++++++++-----
 1 file changed, 32 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
index d7390067b7d4..01e881293612 100644
--- a/drivers/gpu/drm/i915/display/skl_scaler.c
+++ b/drivers/gpu/drm/i915/display/skl_scaler.c
@@ -87,6 +87,10 @@ static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
 #define ICL_MAX_SRC_H 4096
 #define ICL_MAX_DST_W 5120
 #define ICL_MAX_DST_H 4096
+#define MTL_MAX_SRC_W 4096
+#define MTL_MAX_SRC_H 8192
+#define MTL_MAX_DST_W 8192
+#define MTL_MAX_DST_H 8192
 #define SKL_MIN_YUV_420_SRC_W 16
 #define SKL_MIN_YUV_420_SRC_H 16
 
@@ -103,6 +107,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	const struct drm_display_mode *adjusted_mode =
 		&crtc_state->hw.adjusted_mode;
+	int min_src_w, min_src_h, min_dst_w, min_dst_h;
+	int max_src_w, max_src_h, max_dst_w, max_dst_h;
 
 	/*
 	 * Src coordinates are already rotated by 270 degrees for
@@ -157,15 +163,33 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 		return -EINVAL;
 	}
 
+	min_src_w = SKL_MIN_SRC_W;
+	min_src_h = SKL_MIN_SRC_H;
+	min_dst_w = SKL_MIN_DST_W;
+	min_dst_h = SKL_MIN_DST_H;
+
+	if (DISPLAY_VER(dev_priv) < 11) {
+		max_src_w = SKL_MAX_SRC_W;
+		max_src_h = SKL_MAX_SRC_H;
+		max_dst_w = SKL_MAX_DST_W;
+		max_dst_h = SKL_MAX_DST_H;
+	} else if (DISPLAY_VER(dev_priv) < 14) {
+		max_src_w = ICL_MAX_SRC_W;
+		max_src_h = ICL_MAX_SRC_H;
+		max_dst_w = ICL_MAX_DST_W;
+		max_dst_h = ICL_MAX_DST_H;
+	} else {
+		max_src_w = MTL_MAX_SRC_W;
+		max_src_h = MTL_MAX_SRC_H;
+		max_dst_w = MTL_MAX_DST_W;
+		max_dst_h = MTL_MAX_DST_H;
+	}
+
 	/* range checks */
-	if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
-	    dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
-	    (DISPLAY_VER(dev_priv) >= 11 &&
-	     (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
-	      dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
-	    (DISPLAY_VER(dev_priv) < 11 &&
-	     (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
-	      dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H)))	{
+	if (src_w < min_src_w || src_h < min_src_h ||
+	    dst_w < min_dst_w || dst_h < min_dst_h ||
+	    src_w > max_src_w || src_h > max_src_h ||
+	    dst_w > max_dst_w || dst_h > max_dst_h) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "scaler_user index %u.%u: src %ux%u dst %ux%u "
 			    "size is out of scaler range\n",
-- 
2.39.0

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/mtl: handle some MTL scaler limitations

[Patchwork]

== Series Details ==

Series: drm/i915/mtl: handle some MTL scaler limitations
URL   : https://patchwork.freedesktop.org/series/112211/
State : warning

== Summary ==

Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
+./arch/x86/include/asm/bitops.h:117:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:148:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:150:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:154:26: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:156:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:174:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:176:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:180:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:182:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:186:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:188:9: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:192:35: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:16: warning: unreplaced symbol 'oldbit'
+./arch/x86/include/asm/bitops.h:195:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:237:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:239:9: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:66:1: warning: unreplaced symbol 'return'
+./arch/x86/include/asm/bitops.h:92:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:100:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:100:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:105:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:107:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:108:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:109:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:111:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:111:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:112:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:112:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:121:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:128:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:166:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:168:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:169:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:170:9: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:19: warning: unreplaced symbol 'val'
+./include/asm-generic/bitops/generic-non-atomic.h:172:25: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:172:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:28:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:30:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:31:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:33:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:37:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:39:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:40:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:42:16: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:55:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:57:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:58:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:60:15: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:73:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:75:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:76:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:77:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:79:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:79:20: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:17: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:80:23: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:80:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:93:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/generic-non-atomic.h:95:9: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/generic-non-atomic.h:96:9: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:97:9: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:10: warning: unreplaced symbol 'p'
+./include/asm-generic/bitops/generic-non-atomic.h:99:14: warning: unreplaced symbol 'old'
+./include/asm-generic/bitops/generic-non-atomic.h:99:21: warning: unreplaced symbol 'mask'
+./include/asm-generic/bitops/instrumented-non-atomic.h:100:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:112:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:115:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:127:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:130:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:139:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:142:9: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:26:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:42:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:58:1: warning: unreplaced symbol 'return'
+./include/asm-generic/bitops/instrumented-non-atomic.h:97:1: warning: unreplaced symbol 'return'

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/mtl: handle some MTL scaler limitations

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 4424 bytes --]

== Series Details ==

Series: drm/i915/mtl: handle some MTL scaler limitations
URL   : https://patchwork.freedesktop.org/series/112211/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12524 -> Patchwork_112211v1
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/index.html

Participating hosts (45 -> 45)
------------------------------

  Additional (1): bat-atsm-1 
  Missing    (1): fi-rkl-11600 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_112211v1:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@i915_pm_rpm@module-reload:
    - {bat-adlp-9}:       [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/bat-adlp-9/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/bat-adlp-9/igt@i915_pm_rpm@module-reload.html

  
Known issues
------------

  Here are the changes found in Patchwork_112211v1 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@gem_exec_gttfill@basic:
    - fi-pnv-d510:        [FAIL][3] ([i915#7229]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/fi-pnv-d510/igt@gem_exec_gttfill@basic.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/fi-pnv-d510/igt@gem_exec_gttfill@basic.html

  * igt@i915_selftest@live@migrate:
    - bat-adlp-4:         [DMESG-FAIL][5] ([i915#7699]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/bat-adlp-4/igt@i915_selftest@live@migrate.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/bat-adlp-4/igt@i915_selftest@live@migrate.html

  * igt@i915_selftest@live@workarounds:
    - {bat-rpls-1}:       [DMESG-WARN][7] -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/bat-rpls-1/igt@i915_selftest@live@workarounds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/bat-rpls-1/igt@i915_selftest@live@workarounds.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#1836]: https://gitlab.freedesktop.org/drm/intel/issues/1836
  [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
  [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867
  [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
  [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
  [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
  [i915#6077]: https://gitlab.freedesktop.org/drm/intel/issues/6077
  [i915#6078]: https://gitlab.freedesktop.org/drm/intel/issues/6078
  [i915#6093]: https://gitlab.freedesktop.org/drm/intel/issues/6093
  [i915#6094]: https://gitlab.freedesktop.org/drm/intel/issues/6094
  [i915#6166]: https://gitlab.freedesktop.org/drm/intel/issues/6166
  [i915#6311]: https://gitlab.freedesktop.org/drm/intel/issues/6311
  [i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
  [i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
  [i915#7229]: https://gitlab.freedesktop.org/drm/intel/issues/7229
  [i915#7357]: https://gitlab.freedesktop.org/drm/intel/issues/7357
  [i915#7699]: https://gitlab.freedesktop.org/drm/intel/issues/7699


Build changes
-------------

  * Linux: CI_DRM_12524 -> Patchwork_112211v1

  CI-20190529: 20190529
  CI_DRM_12524: a29956c69a562e85ef8657e39382bc207a339941 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7102: bacfdc84a9c02556c5441deb21e3a3f18a07347d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_112211v1: a29956c69a562e85ef8657e39382bc207a339941 @ git://anongit.freedesktop.org/gfx-ci/linux


### Linux commits

6433bac0d11d drm/i915/mtl: update scaler source and destination limits for MTL
37adcc27d4c3 drm/i915/mtl: limit second scaler vertical scaling in ver >= 14

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/index.html

[-- Attachment #2: Type: text/html, Size: 3989 bytes --]

Re: [Intel-gfx] [PATCH v7 2/2] drm/i915/mtl: update scaler source and destination limits for MTL

[Nautiyal, Ankit K]

On 12/23/2022 6:35 PM, Luca Coelho wrote:
> From: Animesh Manna <animesh.manna@intel.com>
>
> The max source and destination limits for scalers in MTL have changed.
> Use the new values accordingly.
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> ---
>
> In v2:
>     * No changes;
>
> In v3:
>     * Removed stray reviewed-by tag;
>     * Added my s-o-b.
>
> In v4:
>     * No changes.
>
> In v5:
>     * Just resent with a cover letter.
>
> In v6:
>     * Now the correct version again (same as v4).
>
> In v7:
>     * Update to new MTL limits according to the bspec.
>
>
>   drivers/gpu/drm/i915/display/skl_scaler.c | 40 ++++++++++++++++++-----
>   1 file changed, 32 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
> index d7390067b7d4..01e881293612 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -87,6 +87,10 @@ static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
>   #define ICL_MAX_SRC_H 4096
>   #define ICL_MAX_DST_W 5120
>   #define ICL_MAX_DST_H 4096
> +#define MTL_MAX_SRC_W 4096
> +#define MTL_MAX_SRC_H 8192
> +#define MTL_MAX_DST_W 8192
> +#define MTL_MAX_DST_H 8192
>   #define SKL_MIN_YUV_420_SRC_W 16
>   #define SKL_MIN_YUV_420_SRC_H 16
>   
> @@ -103,6 +107,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   	const struct drm_display_mode *adjusted_mode =
>   		&crtc_state->hw.adjusted_mode;
> +	int min_src_w, min_src_h, min_dst_w, min_dst_h;
> +	int max_src_w, max_src_h, max_dst_w, max_dst_h;
>   
>   	/*
>   	 * Src coordinates are already rotated by 270 degrees for
> @@ -157,15 +163,33 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>   		return -EINVAL;
>   	}
>   
> +	min_src_w = SKL_MIN_SRC_W;
> +	min_src_h = SKL_MIN_SRC_H;
> +	min_dst_w = SKL_MIN_DST_W;
> +	min_dst_h = SKL_MIN_DST_H;
> +
> +	if (DISPLAY_VER(dev_priv) < 11) {
> +		max_src_w = SKL_MAX_SRC_W;
> +		max_src_h = SKL_MAX_SRC_H;
> +		max_dst_w = SKL_MAX_DST_W;
> +		max_dst_h = SKL_MAX_DST_H;
> +	} else if (DISPLAY_VER(dev_priv) < 14) {
> +		max_src_w = ICL_MAX_SRC_W;
> +		max_src_h = ICL_MAX_SRC_H;
> +		max_dst_w = ICL_MAX_DST_W;
> +		max_dst_h = ICL_MAX_DST_H;

Hi Luca,

Recently there is a change in Bspec:50441 and now for Gen 12 scalers, 
the MAX_SRC_W is 5120 pixels and MAX_SRC_H is 8192.

MAX_DST_W, and MAX_DST_H are 8192.

As we are refactoring this part, can we include a separate patch for Gen 
12 in this series?

Thanks & Regards,

Ankit


> +	} else {
> +		max_src_w = MTL_MAX_SRC_W;
> +		max_src_h = MTL_MAX_SRC_H;
> +		max_dst_w = MTL_MAX_DST_W;
> +		max_dst_h = MTL_MAX_DST_H;
> +	}
> +
>   	/* range checks */
> -	if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
> -	    dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
> -	    (DISPLAY_VER(dev_priv) >= 11 &&
> -	     (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
> -	      dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
> -	    (DISPLAY_VER(dev_priv) < 11 &&
> -	     (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
> -	      dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H)))	{
> +	if (src_w < min_src_w || src_h < min_src_h ||
> +	    dst_w < min_dst_w || dst_h < min_dst_h ||
> +	    src_w > max_src_w || src_h > max_src_h ||
> +	    dst_w > max_dst_w || dst_h > max_dst_h) {
>   		drm_dbg_kms(&dev_priv->drm,
>   			    "scaler_user index %u.%u: src %ux%u dst %ux%u "
>   			    "size is out of scaler range\n",

Re: [Intel-gfx] [PATCH v7 2/2] drm/i915/mtl: update scaler source and destination limits for MTL

[Nautiyal, Ankit K]

On 12/23/2022 7:37 PM, Nautiyal, Ankit K wrote:
>
> On 12/23/2022 6:35 PM, Luca Coelho wrote:
>> From: Animesh Manna <animesh.manna@intel.com>
>>
>> The max source and destination limits for scalers in MTL have changed.
>> Use the new values accordingly.
>>
>> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
>> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
>> ---
>>
>> In v2:
>>     * No changes;
>>
>> In v3:
>>     * Removed stray reviewed-by tag;
>>     * Added my s-o-b.
>>
>> In v4:
>>     * No changes.
>>
>> In v5:
>>     * Just resent with a cover letter.
>>
>> In v6:
>>     * Now the correct version again (same as v4).
>>
>> In v7:
>>     * Update to new MTL limits according to the bspec.
>>
>>
>>   drivers/gpu/drm/i915/display/skl_scaler.c | 40 ++++++++++++++++++-----
>>   1 file changed, 32 insertions(+), 8 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c 
>> b/drivers/gpu/drm/i915/display/skl_scaler.c
>> index d7390067b7d4..01e881293612 100644
>> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
>> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
>> @@ -87,6 +87,10 @@ static u16 skl_scaler_calc_phase(int sub, int 
>> scale, bool chroma_cosited)
>>   #define ICL_MAX_SRC_H 4096
>>   #define ICL_MAX_DST_W 5120
>>   #define ICL_MAX_DST_H 4096
>> +#define MTL_MAX_SRC_W 4096
>> +#define MTL_MAX_SRC_H 8192
>> +#define MTL_MAX_DST_W 8192
>> +#define MTL_MAX_DST_H 8192
>>   #define SKL_MIN_YUV_420_SRC_W 16
>>   #define SKL_MIN_YUV_420_SRC_H 16
>>   @@ -103,6 +107,8 @@ skl_update_scaler(struct intel_crtc_state 
>> *crtc_state, bool force_detach,
>>       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>>       const struct drm_display_mode *adjusted_mode =
>>           &crtc_state->hw.adjusted_mode;
>> +    int min_src_w, min_src_h, min_dst_w, min_dst_h;
>> +    int max_src_w, max_src_h, max_dst_w, max_dst_h;
>>         /*
>>        * Src coordinates are already rotated by 270 degrees for
>> @@ -157,15 +163,33 @@ skl_update_scaler(struct intel_crtc_state 
>> *crtc_state, bool force_detach,
>>           return -EINVAL;
>>       }
>>   +    min_src_w = SKL_MIN_SRC_W;
>> +    min_src_h = SKL_MIN_SRC_H;
>> +    min_dst_w = SKL_MIN_DST_W;
>> +    min_dst_h = SKL_MIN_DST_H;
>> +
>> +    if (DISPLAY_VER(dev_priv) < 11) {
>> +        max_src_w = SKL_MAX_SRC_W;
>> +        max_src_h = SKL_MAX_SRC_H;
>> +        max_dst_w = SKL_MAX_DST_W;
>> +        max_dst_h = SKL_MAX_DST_H;
>> +    } else if (DISPLAY_VER(dev_priv) < 14) {
>> +        max_src_w = ICL_MAX_SRC_W;
>> +        max_src_h = ICL_MAX_SRC_H;
>> +        max_dst_w = ICL_MAX_DST_W;
>> +        max_dst_h = ICL_MAX_DST_H;
>
> Hi Luca,
>
> Recently there is a change in Bspec:50441 and now for Gen 12 scalers, 
> the MAX_SRC_W is 5120 pixels and MAX_SRC_H is 8192.


Slight correction : this is for both Gen12,and 13.

Regards,

Ankit


>
> MAX_DST_W, and MAX_DST_H are 8192.
>
> As we are refactoring this part, can we include a separate patch for 
> Gen 12 in this series?
>
> Thanks & Regards,
>
> Ankit
>
>
>> +    } else {
>> +        max_src_w = MTL_MAX_SRC_W;
>> +        max_src_h = MTL_MAX_SRC_H;
>> +        max_dst_w = MTL_MAX_DST_W;
>> +        max_dst_h = MTL_MAX_DST_H;
>> +    }
>> +
>>       /* range checks */
>> -    if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
>> -        dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
>> -        (DISPLAY_VER(dev_priv) >= 11 &&
>> -         (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
>> -          dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
>> -        (DISPLAY_VER(dev_priv) < 11 &&
>> -         (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
>> -          dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H)))    {
>> +    if (src_w < min_src_w || src_h < min_src_h ||
>> +        dst_w < min_dst_w || dst_h < min_dst_h ||
>> +        src_w > max_src_w || src_h > max_src_h ||
>> +        dst_w > max_dst_w || dst_h > max_dst_h) {
>>           drm_dbg_kms(&dev_priv->drm,
>>                   "scaler_user index %u.%u: src %ux%u dst %ux%u "
>>                   "size is out of scaler range\n",

[Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/mtl: handle some MTL scaler limitations

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 17465 bytes --]

== Series Details ==

Series: drm/i915/mtl: handle some MTL scaler limitations
URL   : https://patchwork.freedesktop.org/series/112211/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_12524_full -> Patchwork_112211v1_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/index.html

Participating hosts (13 -> 10)
------------------------------

  Missing    (3): pig-skl-6260u pig-kbl-iris pig-glk-j5005 

Known issues
------------

  Here are the changes found in Patchwork_112211v1_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-glk:          [PASS][1] -> [FAIL][2] ([i915#2842]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-glk5/igt@gem_exec_fair@basic-throttle@rcs0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-glk1/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1:
    - shard-glk:          NOTRUN -> [SKIP][3] ([fdo#109271])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-glk4/igt@kms_dither@fb-8bpc-vs-panel-6bpc@pipe-a-hdmi-a-1.html

  * igt@kms_flip@plain-flip-fb-recreate@a-hdmi-a1:
    - shard-glk:          [PASS][4] -> [FAIL][5] ([i915#2122])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-glk4/igt@kms_flip@plain-flip-fb-recreate@a-hdmi-a1.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-glk9/igt@kms_flip@plain-flip-fb-recreate@a-hdmi-a1.html

  * igt@perf@stress-open-close:
    - shard-glk:          [PASS][6] -> [INCOMPLETE][7] ([i915#5213])
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-glk4/igt@perf@stress-open-close.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-glk9/igt@perf@stress-open-close.html

  
#### Possible fixes ####

  * igt@feature_discovery@psr2:
    - {shard-rkl}:        [SKIP][8] ([i915#658]) -> [PASS][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-5/igt@feature_discovery@psr2.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-rkl-6/igt@feature_discovery@psr2.html

  * igt@gem_ctx_persistence@engines-hang@bcs0:
    - {shard-rkl}:        [SKIP][10] ([i915#6252]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-5/igt@gem_ctx_persistence@engines-hang@bcs0.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-rkl-1/igt@gem_ctx_persistence@engines-hang@bcs0.html

  * igt@gem_exec_reloc@basic-wc:
    - {shard-rkl}:        [SKIP][12] ([i915#3281]) -> [PASS][13] +3 similar issues
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-3/igt@gem_exec_reloc@basic-wc.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-rkl-5/igt@gem_exec_reloc@basic-wc.html

  * igt@gem_mmap_gtt@coherency:
    - {shard-rkl}:        [SKIP][14] ([fdo#111656]) -> [PASS][15]
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-3/igt@gem_mmap_gtt@coherency.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-rkl-5/igt@gem_mmap_gtt@coherency.html

  * igt@gem_partial_pwrite_pread@reads:
    - {shard-rkl}:        [SKIP][16] ([i915#3282]) -> [PASS][17] +1 similar issue
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-3/igt@gem_partial_pwrite_pread@reads.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-rkl-5/igt@gem_partial_pwrite_pread@reads.html

  * igt@gen9_exec_parse@unaligned-access:
    - {shard-rkl}:        [SKIP][18] ([i915#2527]) -> [PASS][19]
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-3/igt@gen9_exec_parse@unaligned-access.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-rkl-5/igt@gen9_exec_parse@unaligned-access.html

  * igt@i915_hangman@gt-engine-error@bcs0:
    - {shard-rkl}:        [SKIP][20] ([i915#6258]) -> [PASS][21]
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-5/igt@i915_hangman@gt-engine-error@bcs0.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-rkl-6/igt@i915_hangman@gt-engine-error@bcs0.html

  * igt@i915_pm_rc6_residency@rc6-idle@vcs0:
    - {shard-rkl}:        [WARN][22] ([i915#2681]) -> [PASS][23]
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-5/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-rkl-3/igt@i915_pm_rc6_residency@rc6-idle@vcs0.html

  * igt@i915_pm_rpm@drm-resources-equal:
    - {shard-rkl}:        [SKIP][24] ([fdo#109308]) -> [PASS][25]
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-1/igt@i915_pm_rpm@drm-resources-equal.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-rkl-6/igt@i915_pm_rpm@drm-resources-equal.html

  * igt@i915_pm_rpm@fences:
    - {shard-rkl}:        [SKIP][26] ([i915#1849]) -> [PASS][27]
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-5/igt@i915_pm_rpm@fences.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-rkl-6/igt@i915_pm_rpm@fences.html

  * igt@i915_pm_rpm@modeset-non-lpsp:
    - {shard-dg1}:        [SKIP][28] ([i915#1397]) -> [PASS][29] +2 similar issues
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-dg1-14/igt@i915_pm_rpm@modeset-non-lpsp.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-dg1-15/igt@i915_pm_rpm@modeset-non-lpsp.html

  * igt@kms_big_fb@x-tiled-32bpp-rotate-0:
    - {shard-rkl}:        [SKIP][30] ([i915#1845] / [i915#4098]) -> [PASS][31] +20 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-1/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-rkl-6/igt@kms_big_fb@x-tiled-32bpp-rotate-0.html

  * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size:
    - shard-glk:          [FAIL][32] ([i915#2346]) -> [PASS][33] +1 similar issue
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-glk5/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-glk1/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html

  * igt@kms_flip@plain-flip-ts-check@c-hdmi-a1:
    - shard-glk:          [FAIL][34] ([i915#2122]) -> [PASS][35]
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-glk3/igt@kms_flip@plain-flip-ts-check@c-hdmi-a1.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-glk8/igt@kms_flip@plain-flip-ts-check@c-hdmi-a1.html

  * igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite:
    - {shard-rkl}:        [SKIP][36] ([i915#1849] / [i915#4098]) -> [PASS][37] +5 similar issues
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-rkl-6/igt@kms_frontbuffer_tracking@psr-1p-offscren-pri-shrfb-draw-pwrite.html

  * igt@kms_psr@cursor_blt:
    - {shard-rkl}:        [SKIP][38] ([i915#1072]) -> [PASS][39] +1 similar issue
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-1/igt@kms_psr@cursor_blt.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-rkl-6/igt@kms_psr@cursor_blt.html

  * igt@kms_psr_stress_test@flip-primary-invalidate-overlay:
    - {shard-rkl}:        [SKIP][40] ([i915#5461]) -> [PASS][41]
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-1/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-rkl-6/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html

  * igt@kms_universal_plane@disable-primary-vs-flip-pipe-a:
    - {shard-rkl}:        [SKIP][42] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][43]
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_12524/shard-rkl-1/igt@kms_universal_plane@disable-primary-vs-flip-pipe-a.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/shard-rkl-6/igt@kms_universal_plane@disable-primary-vs-flip-pipe-a.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
  [fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
  [fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
  [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
  [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
  [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
  [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
  [fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
  [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
  [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
  [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
  [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
  [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
  [fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
  [fdo#111656]: https://bugs.freedesktop.org/show_bug.cgi?id=111656
  [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
  [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
  [fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
  [fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
  [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
  [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
  [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
  [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
  [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
  [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
  [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
  [i915#1937]: https://gitlab.freedesktop.org/drm/intel/issues/1937
  [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
  [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
  [i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
  [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
  [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
  [i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
  [i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
  [i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
  [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
  [i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
  [i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
  [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
  [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
  [i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
  [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
  [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
  [i915#315]: https://gitlab.freedesktop.org/drm/intel/issues/315
  [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
  [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
  [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
  [i915#3323]: https://gitlab.freedesktop.org/drm/intel/issues/3323
  [i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
  [i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
  [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
  [i915#3547]: https://gitlab.freedesktop.org/drm/intel/issues/3547
  [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
  [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
  [i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
  [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
  [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
  [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
  [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
  [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
  [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
  [i915#3825]: https://gitlab.freedesktop.org/drm/intel/issues/3825
  [i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
  [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
  [i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
  [i915#3966]: https://gitlab.freedesktop.org/drm/intel/issues/3966
  [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
  [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
  [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
  [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
  [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
  [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
  [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
  [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767
  [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
  [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
  [i915#5213]: https://gitlab.freedesktop.org/drm/intel/issues/5213
  [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
  [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
  [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
  [i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
  [i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
  [i915#5327]: https://gitlab.freedesktop.org/drm/intel/issues/5327
  [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
  [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
  [i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
  [i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
  [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
  [i915#6117]: https://gitlab.freedesktop.org/drm/intel/issues/6117
  [i915#6245]: https://gitlab.freedesktop.org/drm/intel/issues/6245
  [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248
  [i915#6252]: https://gitlab.freedesktop.org/drm/intel/issues/6252
  [i915#6258]: https://gitlab.freedesktop.org/drm/intel/issues/6258
  [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268
  [i915#6412]: https://gitlab.freedesktop.org/drm/intel/issues/6412
  [i915#6433]: https://gitlab.freedesktop.org/drm/intel/issues/6433
  [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497
  [i915#6524]: https://gitlab.freedesktop.org/drm/intel/issues/6524
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#6768]: https://gitlab.freedesktop.org/drm/intel/issues/6768
  [i915#6944]: https://gitlab.freedesktop.org/drm/intel/issues/6944
  [i915#6946]: https://gitlab.freedesktop.org/drm/intel/issues/6946
  [i915#6953]: https://gitlab.freedesktop.org/drm/intel/issues/6953
  [i915#7037]: https://gitlab.freedesktop.org/drm/intel/issues/7037
  [i915#7116]: https://gitlab.freedesktop.org/drm/intel/issues/7116
  [i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
  [i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
  [i915#7582]: https://gitlab.freedesktop.org/drm/intel/issues/7582
  [i915#7651]: https://gitlab.freedesktop.org/drm/intel/issues/7651
  [i915#7681]: https://gitlab.freedesktop.org/drm/intel/issues/7681
  [i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
  [i915#7707]: https://gitlab.freedesktop.org/drm/intel/issues/7707


Build changes
-------------

  * Linux: CI_DRM_12524 -> Patchwork_112211v1
  * Piglit: piglit_4509 -> None

  CI-20190529: 20190529
  CI_DRM_12524: a29956c69a562e85ef8657e39382bc207a339941 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_7102: bacfdc84a9c02556c5441deb21e3a3f18a07347d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_112211v1: a29956c69a562e85ef8657e39382bc207a339941 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_112211v1/index.html

[-- Attachment #2: Type: text/html, Size: 12368 bytes --]

Re: [Intel-gfx] [PATCH v7 2/2] drm/i915/mtl: update scaler source and destination limits for MTL

[Coelho, Luciano]

On Fri, 2022-12-23 at 19:42 +0530, Nautiyal, Ankit K wrote:
> On 12/23/2022 7:37 PM, Nautiyal, Ankit K wrote:
> > 
> > On 12/23/2022 6:35 PM, Luca Coelho wrote:
> > > From: Animesh Manna <animesh.manna@intel.com>
> > > 
> > > The max source and destination limits for scalers in MTL have changed.
> > > Use the new values accordingly.
> > > 
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > > Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> > > ---
> > > 
> > > In v2:
> > >     * No changes;
> > > 
> > > In v3:
> > >     * Removed stray reviewed-by tag;
> > >     * Added my s-o-b.
> > > 
> > > In v4:
> > >     * No changes.
> > > 
> > > In v5:
> > >     * Just resent with a cover letter.
> > > 
> > > In v6:
> > >     * Now the correct version again (same as v4).
> > > 
> > > In v7:
> > >     * Update to new MTL limits according to the bspec.
> > > 
> > > 
> > >   drivers/gpu/drm/i915/display/skl_scaler.c | 40 ++++++++++++++++++-----
> > >   1 file changed, 32 insertions(+), 8 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c 
> > > b/drivers/gpu/drm/i915/display/skl_scaler.c
> > > index d7390067b7d4..01e881293612 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> > > @@ -87,6 +87,10 @@ static u16 skl_scaler_calc_phase(int sub, int 
> > > scale, bool chroma_cosited)
> > >   #define ICL_MAX_SRC_H 4096
> > >   #define ICL_MAX_DST_W 5120
> > >   #define ICL_MAX_DST_H 4096
> > > +#define MTL_MAX_SRC_W 4096
> > > +#define MTL_MAX_SRC_H 8192
> > > +#define MTL_MAX_DST_W 8192
> > > +#define MTL_MAX_DST_H 8192
> > >   #define SKL_MIN_YUV_420_SRC_W 16
> > >   #define SKL_MIN_YUV_420_SRC_H 16
> > >   @@ -103,6 +107,8 @@ skl_update_scaler(struct intel_crtc_state 
> > > *crtc_state, bool force_detach,
> > >       struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > >       const struct drm_display_mode *adjusted_mode =
> > >           &crtc_state->hw.adjusted_mode;
> > > +    int min_src_w, min_src_h, min_dst_w, min_dst_h;
> > > +    int max_src_w, max_src_h, max_dst_w, max_dst_h;
> > >         /*
> > >        * Src coordinates are already rotated by 270 degrees for
> > > @@ -157,15 +163,33 @@ skl_update_scaler(struct intel_crtc_state 
> > > *crtc_state, bool force_detach,
> > >           return -EINVAL;
> > >       }
> > >   +    min_src_w = SKL_MIN_SRC_W;
> > > +    min_src_h = SKL_MIN_SRC_H;
> > > +    min_dst_w = SKL_MIN_DST_W;
> > > +    min_dst_h = SKL_MIN_DST_H;
> > > +
> > > +    if (DISPLAY_VER(dev_priv) < 11) {
> > > +        max_src_w = SKL_MAX_SRC_W;
> > > +        max_src_h = SKL_MAX_SRC_H;
> > > +        max_dst_w = SKL_MAX_DST_W;
> > > +        max_dst_h = SKL_MAX_DST_H;
> > > +    } else if (DISPLAY_VER(dev_priv) < 14) {
> > > +        max_src_w = ICL_MAX_SRC_W;
> > > +        max_src_h = ICL_MAX_SRC_H;
> > > +        max_dst_w = ICL_MAX_DST_W;
> > > +        max_dst_h = ICL_MAX_DST_H;
> > 
> > Hi Luca,
> > 
> > Recently there is a change in Bspec:50441 and now for Gen 12 scalers, 
> > the MAX_SRC_W is 5120 pixels and MAX_SRC_H is 8192.
> 
> 
> Slight correction : this is for both Gen12,and 13.
> 
> Regards,
> 
> Ankit
> 
> 
> > 
> > MAX_DST_W, and MAX_DST_H are 8192.
> > 
> > As we are refactoring this part, can we include a separate patch for 
> > Gen 12 in this series?

Thanks for pointing out, Ankit!

But since my series is specifically targeting MTL, I'm going to send it
as a stand-alone patch, if that's ok.

--
Cheers,
Luca.

Re: [Intel-gfx] [PATCH v7 0/2] drm/i915/mtl: handle some MTL scaler limitations

[Coelho, Luciano]

On Fri, 2022-12-23 at 15:05 +0200, Luca Coelho wrote:
> Hi,
> 
> Here's an updated version of the patches after Ville's last comments.
> The versioning history is in the patches themselves.
> 
> Please review.
> 
> Cheers,
> Luca.
> 
> 
> Animesh Manna (1):
>   drm/i915/mtl: update scaler source and destination limits for MTL
> 
> Luca Coelho (1):
>   drm/i915/mtl: limit second scaler vertical scaling in ver >= 14
> 
>  drivers/gpu/drm/i915/display/intel_atomic.c | 85 ++++++++++++++++++---
>  drivers/gpu/drm/i915/display/skl_scaler.c   | 40 ++++++++--
>  2 files changed, 107 insertions(+), 18 deletions(-)
> 

Hi Ville,

Can you please review this new revision of my patchset? For some reason
I forgot to CC you on this one. 😞

Thanks!

--
Cheers,
Luca.

Re: [Intel-gfx] [PATCH v7 1/2] drm/i915/mtl: limit second scaler vertical scaling in ver >= 14

[Lisovskiy, Stanislav]

On Fri, Dec 23, 2022 at 03:05:08PM +0200, Luca Coelho wrote:
> In newer hardware versions (i.e. display version >= 14), the second
> scaler doesn't support vertical scaling.
> 
> The current implementation of the scaling limits is simplified and
> only occurs when the planes are created, so we don't know which scaler
> is being used.
> 
> In order to handle separate scaling limits for horizontal and vertical
> scaling, and different limits per scaler, split the checks in two
> phases.  We first do a simple check during plane creation and use the
> best-case scenario (because we don't know the scaler that may be used
> at a later point) and then do a more specific check when the scalers
> are actually being set up.
> 
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> ---
> 
> In v2:
>    * fix DRM_PLANE_NO_SCALING renamed macros;
> 
> In v3:
>    * No changes.
> 
> In v4:
>    * Got rid of the changes in the general planes max scale code;
>    * Added a couple of FIXMEs;
>    * Made intel_atomic_setup_scaler() return an int with errors;
> 
> In v5:
>    * Just resent with a cover letter.
> 
> In v6:
>    * Now the correct version again (same as v4).
> 
> In v7:
>    * Constify a couple of local variables;
>    * Return -EINVAL, instead of -EOPNOTSUPP and -EBUSY;
>    * Add another FIXME;
>    * Remove unnecessary undoing of change in error cases.
> 
> 
>  drivers/gpu/drm/i915/display/intel_atomic.c | 85 ++++++++++++++++++---
>  1 file changed, 75 insertions(+), 10 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 6621aa245caf..a9a3f3715279 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> @@ -41,6 +41,7 @@
>  #include "intel_global_state.h"
>  #include "intel_hdcp.h"
>  #include "intel_psr.h"
> +#include "intel_fb.h"
>  #include "skl_universal_plane.h"
>  
>  /**
> @@ -310,11 +311,11 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
>  	kfree(crtc_state);
>  }
>  
> -static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
> -				      int num_scalers_need, struct intel_crtc *intel_crtc,
> -				      const char *name, int idx,
> -				      struct intel_plane_state *plane_state,
> -				      int *scaler_id)
> +static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
> +				     int num_scalers_need, struct intel_crtc *intel_crtc,
> +				     const char *name, int idx,
> +				     struct intel_plane_state *plane_state,
> +				     int *scaler_id)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
>  	int j;
> @@ -334,7 +335,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
>  
>  	if (drm_WARN(&dev_priv->drm, *scaler_id < 0,
>  		     "Cannot find scaler for %s:%d\n", name, idx))
> -		return;
> +		return -EINVAL;

As I understand that change is a bit irrelevant to the patch topic,
ideally it should be reflected in the commit message, that we are doing
this and most importantly why.
However I'm not going to be picky here, as it is a small thing, just
as a side note.

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

>  
>  	/* set scaler mode */
>  	if (plane_state && plane_state->hw.fb &&
> @@ -375,9 +376,71 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
>  		mode = SKL_PS_SCALER_MODE_DYN;
>  	}
>  
> +	/*
> +	 * FIXME: we should also check the scaler factors for pfit, so
> +	 * this shouldn't be tied directly to planes.
> +	 */
> +	if (plane_state && plane_state->hw.fb) {
> +		const struct drm_framebuffer *fb = plane_state->hw.fb;
> +		const struct drm_rect *src = &plane_state->uapi.src;
> +		const struct drm_rect *dst = &plane_state->uapi.dst;
> +		int hscale, vscale, max_vscale, max_hscale;
> +
> +		/*
> +		 * FIXME: When two scalers are needed, but only one of
> +		 * them needs to downscale, we should make sure that
> +		 * the one that needs downscaling support is assigned
> +		 * as the first scaler, so we don't reject downscaling
> +		 * unnecessarily.
> +		 */
> +
> +		if (DISPLAY_VER(dev_priv) >= 14) {
> +			/*
> +			 * On versions 14 and up, only the first
> +			 * scaler supports a vertical scaling factor
> +			 * of more than 1.0, while a horizontal
> +			 * scaling factor of 3.0 is supported.
> +			 */
> +			max_hscale = 0x30000 - 1;
> +			if (*scaler_id == 0)
> +				max_vscale = 0x30000 - 1;
> +			else
> +				max_vscale = 0x10000;
> +
> +		} else if (DISPLAY_VER(dev_priv) >= 10 ||
> +			   !intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
> +			max_hscale = 0x30000 - 1;
> +			max_vscale = 0x30000 - 1;
> +		} else {
> +			max_hscale = 0x20000 - 1;
> +			max_vscale = 0x20000 - 1;
> +		}
> +
> +		/*
> +		 * FIXME: We should change the if-else block above to
> +		 * support HQ vs dynamic scaler properly.
> +		 */
> +
> +		/* Check if required scaling is within limits */
> +		hscale = drm_rect_calc_hscale(src, dst, 1, max_hscale);
> +		vscale = drm_rect_calc_vscale(src, dst, 1, max_vscale);
> +
> +		if (hscale < 0 || vscale < 0) {
> +			drm_dbg_kms(&dev_priv->drm,
> +				    "Scaler %d doesn't support required plane scaling\n",
> +				    *scaler_id);
> +			drm_rect_debug_print("src: ", src, true);
> +			drm_rect_debug_print("dst: ", dst, false);
> +
> +			return -EINVAL;
> +		}
> +	}
> +
>  	drm_dbg_kms(&dev_priv->drm, "Attached scaler id %u.%u to %s:%d\n",
>  		    intel_crtc->pipe, *scaler_id, name, idx);
>  	scaler_state->scalers[*scaler_id].mode = mode;
> +
> +	return 0;
>  }
>  
>  /**
> @@ -437,7 +500,7 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>  	for (i = 0; i < sizeof(scaler_state->scaler_users) * 8; i++) {
>  		int *scaler_id;
>  		const char *name;
> -		int idx;
> +		int idx, ret;
>  
>  		/* skip if scaler not required */
>  		if (!(scaler_state->scaler_users & (1 << i)))
> @@ -494,9 +557,11 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
>  			scaler_id = &plane_state->scaler_id;
>  		}
>  
> -		intel_atomic_setup_scaler(scaler_state, num_scalers_need,
> -					  intel_crtc, name, idx,
> -					  plane_state, scaler_id);
> +		ret = intel_atomic_setup_scaler(scaler_state, num_scalers_need,
> +						intel_crtc, name, idx,
> +						plane_state, scaler_id);
> +		if (ret < 0)
> +			return ret;
>  	}
>  
>  	return 0;
> -- 
> 2.39.0
> 

Re: [Intel-gfx] [PATCH v7 2/2] drm/i915/mtl: update scaler source and destination limits for MTL

[Lisovskiy, Stanislav]

On Fri, Dec 23, 2022 at 03:05:09PM +0200, Luca Coelho wrote:
> From: Animesh Manna <animesh.manna@intel.com>
> 
> The max source and destination limits for scalers in MTL have changed.
> Use the new values accordingly.
> 
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> ---
> 
> In v2:
>    * No changes;
> 
> In v3:
>    * Removed stray reviewed-by tag;
>    * Added my s-o-b.
> 
> In v4:
>    * No changes.
> 
> In v5:
>    * Just resent with a cover letter.
> 
> In v6:
>    * Now the correct version again (same as v4).
> 
> In v7:
>    * Update to new MTL limits according to the bspec.
> 
> 
>  drivers/gpu/drm/i915/display/skl_scaler.c | 40 ++++++++++++++++++-----
>  1 file changed, 32 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c b/drivers/gpu/drm/i915/display/skl_scaler.c
> index d7390067b7d4..01e881293612 100644
> --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> @@ -87,6 +87,10 @@ static u16 skl_scaler_calc_phase(int sub, int scale, bool chroma_cosited)
>  #define ICL_MAX_SRC_H 4096
>  #define ICL_MAX_DST_W 5120
>  #define ICL_MAX_DST_H 4096
> +#define MTL_MAX_SRC_W 4096
> +#define MTL_MAX_SRC_H 8192
> +#define MTL_MAX_DST_W 8192
> +#define MTL_MAX_DST_H 8192
>  #define SKL_MIN_YUV_420_SRC_W 16
>  #define SKL_MIN_YUV_420_SRC_H 16
>  
> @@ -103,6 +107,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>  	const struct drm_display_mode *adjusted_mode =
>  		&crtc_state->hw.adjusted_mode;
> +	int min_src_w, min_src_h, min_dst_w, min_dst_h;
> +	int max_src_w, max_src_h, max_dst_w, max_dst_h;
>  
>  	/*
>  	 * Src coordinates are already rotated by 270 degrees for
> @@ -157,15 +163,33 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
>  		return -EINVAL;
>  	}
>  
> +	min_src_w = SKL_MIN_SRC_W;
> +	min_src_h = SKL_MIN_SRC_H;
> +	min_dst_w = SKL_MIN_DST_W;
> +	min_dst_h = SKL_MIN_DST_H;
> +
> +	if (DISPLAY_VER(dev_priv) < 11) {
> +		max_src_w = SKL_MAX_SRC_W;
> +		max_src_h = SKL_MAX_SRC_H;
> +		max_dst_w = SKL_MAX_DST_W;
> +		max_dst_h = SKL_MAX_DST_H;
> +	} else if (DISPLAY_VER(dev_priv) < 14) {
> +		max_src_w = ICL_MAX_SRC_W;
> +		max_src_h = ICL_MAX_SRC_H;
> +		max_dst_w = ICL_MAX_DST_W;
> +		max_dst_h = ICL_MAX_DST_H;
> +	} else {
> +		max_src_w = MTL_MAX_SRC_W;
> +		max_src_h = MTL_MAX_SRC_H;
> +		max_dst_w = MTL_MAX_DST_W;
> +		max_dst_h = MTL_MAX_DST_H;
> +	}
> +
>  	/* range checks */
> -	if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
> -	    dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
> -	    (DISPLAY_VER(dev_priv) >= 11 &&
> -	     (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
> -	      dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
> -	    (DISPLAY_VER(dev_priv) < 11 &&
> -	     (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
> -	      dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H)))	{
> +	if (src_w < min_src_w || src_h < min_src_h ||
> +	    dst_w < min_dst_w || dst_h < min_dst_h ||
> +	    src_w > max_src_w || src_h > max_src_h ||
> +	    dst_w > max_dst_w || dst_h > max_dst_h) {

Yep, that looks definitely way cleaner than initial condition.

Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

>  		drm_dbg_kms(&dev_priv->drm,
>  			    "scaler_user index %u.%u: src %ux%u dst %ux%u "
>  			    "size is out of scaler range\n",
> -- 
> 2.39.0
> 

Re: [Intel-gfx] [PATCH v7 1/2] drm/i915/mtl: limit second scaler vertical scaling in ver >= 14

[Coelho, Luciano]

On Mon, 2023-01-09 at 09:06 +0200, Lisovskiy, Stanislav wrote:
> On Fri, Dec 23, 2022 at 03:05:08PM +0200, Luca Coelho wrote:
> > In newer hardware versions (i.e. display version >= 14), the second
> > scaler doesn't support vertical scaling.
> > 
> > The current implementation of the scaling limits is simplified and
> > only occurs when the planes are created, so we don't know which scaler
> > is being used.
> > 
> > In order to handle separate scaling limits for horizontal and vertical
> > scaling, and different limits per scaler, split the checks in two
> > phases.  We first do a simple check during plane creation and use the
> > best-case scenario (because we don't know the scaler that may be used
> > at a later point) and then do a more specific check when the scalers
> > are actually being set up.
> > 
> > Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> > ---
> > 
> > In v2:
> >    * fix DRM_PLANE_NO_SCALING renamed macros;
> > 
> > In v3:
> >    * No changes.
> > 
> > In v4:
> >    * Got rid of the changes in the general planes max scale code;
> >    * Added a couple of FIXMEs;
> >    * Made intel_atomic_setup_scaler() return an int with errors;
> > 
> > In v5:
> >    * Just resent with a cover letter.
> > 
> > In v6:
> >    * Now the correct version again (same as v4).
> > 
> > In v7:
> >    * Constify a couple of local variables;
> >    * Return -EINVAL, instead of -EOPNOTSUPP and -EBUSY;
> >    * Add another FIXME;
> >    * Remove unnecessary undoing of change in error cases.
> > 
> > 
> >  drivers/gpu/drm/i915/display/intel_atomic.c | 85 ++++++++++++++++++---
> >  1 file changed, 75 insertions(+), 10 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> > index 6621aa245caf..a9a3f3715279 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
> > @@ -41,6 +41,7 @@
> >  #include "intel_global_state.h"
> >  #include "intel_hdcp.h"
> >  #include "intel_psr.h"
> > +#include "intel_fb.h"
> >  #include "skl_universal_plane.h"
> >  
> >  /**
> > @@ -310,11 +311,11 @@ intel_crtc_destroy_state(struct drm_crtc *crtc,
> >  	kfree(crtc_state);
> >  }
> >  
> > -static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
> > -				      int num_scalers_need, struct intel_crtc *intel_crtc,
> > -				      const char *name, int idx,
> > -				      struct intel_plane_state *plane_state,
> > -				      int *scaler_id)
> > +static int intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_state,
> > +				     int num_scalers_need, struct intel_crtc *intel_crtc,
> > +				     const char *name, int idx,
> > +				     struct intel_plane_state *plane_state,
> > +				     int *scaler_id)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
> >  	int j;
> > @@ -334,7 +335,7 @@ static void intel_atomic_setup_scaler(struct intel_crtc_scaler_state *scaler_sta
> >  
> >  	if (drm_WARN(&dev_priv->drm, *scaler_id < 0,
> >  		     "Cannot find scaler for %s:%d\n", name, idx))
> > -		return;
> > +		return -EINVAL;
> 
> As I understand that change is a bit irrelevant to the patch topic,
> ideally it should be reflected in the commit message, that we are doing
> this and most importantly why.

Right, maybe this should have been mentioned in the commit message.  I
initially didn't return an error for the new failure path, but Ville
asked me to do so, so I changed the function to return an error here as
well.


> However I'm not going to be picky here, as it is a small thing, just
> as a side note.

Thanks!


> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>

Thanks for the review, Stan!

--
Cheers,
Luca.

Re: [Intel-gfx] [PATCH v7 2/2] drm/i915/mtl: update scaler source and destination limits for MTL

[Sripada, Radhakrishna]

Merged the two patches. Thanks for the review and the patch.

Regards,
Radhakrishna(RK) Sripada

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of
> Lisovskiy, Stanislav
> Sent: Sunday, January 8, 2023 11:32 PM
> To: Coelho, Luciano <luciano.coelho@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH v7 2/2] drm/i915/mtl: update scaler source and
> destination limits for MTL
> 
> On Fri, Dec 23, 2022 at 03:05:09PM +0200, Luca Coelho wrote:
> > From: Animesh Manna <animesh.manna@intel.com>
> >
> > The max source and destination limits for scalers in MTL have changed.
> > Use the new values accordingly.
> >
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > Signed-off-by: Animesh Manna <animesh.manna@intel.com>
> > Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
> > ---
> >
> > In v2:
> >    * No changes;
> >
> > In v3:
> >    * Removed stray reviewed-by tag;
> >    * Added my s-o-b.
> >
> > In v4:
> >    * No changes.
> >
> > In v5:
> >    * Just resent with a cover letter.
> >
> > In v6:
> >    * Now the correct version again (same as v4).
> >
> > In v7:
> >    * Update to new MTL limits according to the bspec.
> >
> >
> >  drivers/gpu/drm/i915/display/skl_scaler.c | 40 ++++++++++++++++++-----
> >  1 file changed, 32 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/skl_scaler.c
> b/drivers/gpu/drm/i915/display/skl_scaler.c
> > index d7390067b7d4..01e881293612 100644
> > --- a/drivers/gpu/drm/i915/display/skl_scaler.c
> > +++ b/drivers/gpu/drm/i915/display/skl_scaler.c
> > @@ -87,6 +87,10 @@ static u16 skl_scaler_calc_phase(int sub, int scale, bool
> chroma_cosited)
> >  #define ICL_MAX_SRC_H 4096
> >  #define ICL_MAX_DST_W 5120
> >  #define ICL_MAX_DST_H 4096
> > +#define MTL_MAX_SRC_W 4096
> > +#define MTL_MAX_SRC_H 8192
> > +#define MTL_MAX_DST_W 8192
> > +#define MTL_MAX_DST_H 8192
> >  #define SKL_MIN_YUV_420_SRC_W 16
> >  #define SKL_MIN_YUV_420_SRC_H 16
> >
> > @@ -103,6 +107,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state,
> bool force_detach,
> >  	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> >  	const struct drm_display_mode *adjusted_mode =
> >  		&crtc_state->hw.adjusted_mode;
> > +	int min_src_w, min_src_h, min_dst_w, min_dst_h;
> > +	int max_src_w, max_src_h, max_dst_w, max_dst_h;
> >
> >  	/*
> >  	 * Src coordinates are already rotated by 270 degrees for
> > @@ -157,15 +163,33 @@ skl_update_scaler(struct intel_crtc_state
> *crtc_state, bool force_detach,
> >  		return -EINVAL;
> >  	}
> >
> > +	min_src_w = SKL_MIN_SRC_W;
> > +	min_src_h = SKL_MIN_SRC_H;
> > +	min_dst_w = SKL_MIN_DST_W;
> > +	min_dst_h = SKL_MIN_DST_H;
> > +
> > +	if (DISPLAY_VER(dev_priv) < 11) {
> > +		max_src_w = SKL_MAX_SRC_W;
> > +		max_src_h = SKL_MAX_SRC_H;
> > +		max_dst_w = SKL_MAX_DST_W;
> > +		max_dst_h = SKL_MAX_DST_H;
> > +	} else if (DISPLAY_VER(dev_priv) < 14) {
> > +		max_src_w = ICL_MAX_SRC_W;
> > +		max_src_h = ICL_MAX_SRC_H;
> > +		max_dst_w = ICL_MAX_DST_W;
> > +		max_dst_h = ICL_MAX_DST_H;
> > +	} else {
> > +		max_src_w = MTL_MAX_SRC_W;
> > +		max_src_h = MTL_MAX_SRC_H;
> > +		max_dst_w = MTL_MAX_DST_W;
> > +		max_dst_h = MTL_MAX_DST_H;
> > +	}
> > +
> >  	/* range checks */
> > -	if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
> > -	    dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
> > -	    (DISPLAY_VER(dev_priv) >= 11 &&
> > -	     (src_w > ICL_MAX_SRC_W || src_h > ICL_MAX_SRC_H ||
> > -	      dst_w > ICL_MAX_DST_W || dst_h > ICL_MAX_DST_H)) ||
> > -	    (DISPLAY_VER(dev_priv) < 11 &&
> > -	     (src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
> > -	      dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H)))	{
> > +	if (src_w < min_src_w || src_h < min_src_h ||
> > +	    dst_w < min_dst_w || dst_h < min_dst_h ||
> > +	    src_w > max_src_w || src_h > max_src_h ||
> > +	    dst_w > max_dst_w || dst_h > max_dst_h) {
> 
> Yep, that looks definitely way cleaner than initial condition.
> 
> Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> 
> >  		drm_dbg_kms(&dev_priv->drm,
> >  			    "scaler_user index %u.%u: src %ux%u dst %ux%u "
> >  			    "size is out of scaler range\n",
> > --
> > 2.39.0
> >