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From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>,
	intel-gfx@lists.freedesktop.org
Cc: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
Subject: Re: [Intel-gfx] [PATCH v2 4/9] drm/i915/display: Handle frontbuffer rendering when PSR2 selective fetch is enabled
Date: Thu, 30 Sep 2021 10:17:32 +0300	[thread overview]
Message-ID: <7ce77c14-fd7a-95bb-c2aa-f1690fcb4d05@intel.com> (raw)
In-Reply-To: <20210930001409.254817-4-jose.souza@intel.com>



On 9/30/21 3:14 AM, José Roberto de Souza wrote:
> When PSR2 selective fetch is enabled writes to CURSURFLIVE alone do
> not causes the panel to be updated when doing frontbuffer rendering.
> 
>  From what I was able to figure from experiments the writes to
> CURSURFLIVE takes PSR2 from deep sleep but panel is not updated
> because PSR2_MAN_TRK_CTL has no start and end region set.
> 
> As we don't have the dirt area from current flush and invalidate API
> and even if we did userspace could do several draws to frontbuffer and
> we would need a way to append all the damaged areas of all the draws
> that need to be part of next frame.
> 
> So here only programing PSR2_MAN_TRK_CTL to do a single full frame
> fetch.
> 
> It is a safe approach as if scanout is in the visible area
> the single full frame will only be visible for hardware in the next
> frame because of the double buffering, and if scanout is in vblank
> area it will be draw in the current frame.
> 
> No need to disable PSR and wait a few miliseconds to enable it again.
> 
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_psr.c | 12 ++++++++++++
>   1 file changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index 8534cbb0d5144..7185801d5deff 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1397,10 +1397,22 @@ void intel_psr_resume(struct intel_dp *intel_dp)
>   	mutex_unlock(&psr->lock);
>   }
>   
> +static inline u32 man_trk_ctl_single_full_frame_bit_get(struct drm_i915_private *dev_priv)
> +{
> +	return IS_ALDERLAKE_P(dev_priv) ?
> +	       ADLP_PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME :
> +	       PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> +}
> +
>   static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
>   {
>   	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
>   
> +	if (intel_dp->psr.psr2_sel_fetch_enabled)
> +		intel_de_rmw(dev_priv,
> +			     PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder), 0,
> +			     man_trk_ctl_single_full_frame_bit_get(dev_priv));
> +
>   	/*
>   	 * Display WA #0884: skl+
The following details is described in the description related to Display 
WA #0884, so I think it matches the commit message described above.
  : Driver to issue a flip whenever a host modify occurs. This ensures 
PSR exits its sleep state during a host modify event.

However, it is not clearly stated whether this WA# will also affect 
GEN12+. Since there is a possibility that it may not work normally in HW 
that will be released later, if you don't mind could you please leave a 
comment that this operation has been confirmed in ADLP?

Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
>   	 * This documented WA for bxt can be safely applied
> 

  reply	other threads:[~2021-09-30  7:17 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-30  0:14 [Intel-gfx] [PATCH v2 1/9] drm/i915/display/psr: Handle plane and pipe restrictions at every page flip José Roberto de Souza
2021-09-30  0:14 ` [Intel-gfx] [PATCH v2 2/9] drm/i915/display/psr: Do full fetch when handling multi-planar formats José Roberto de Souza
2021-09-30 12:58   ` Ville Syrjälä
2021-09-30  0:14 ` [Intel-gfx] [PATCH v2 3/9] drm/i915/display: Drop unnecessary frontbuffer flushes José Roberto de Souza
2021-09-30  7:41   ` Ville Syrjälä
2021-09-30  0:14 ` [Intel-gfx] [PATCH v2 4/9] drm/i915/display: Handle frontbuffer rendering when PSR2 selective fetch is enabled José Roberto de Souza
2021-09-30  7:17   ` Gwan-gyeong Mun [this message]
2021-09-30 18:02     ` Souza, Jose
2021-09-30  0:14 ` [Intel-gfx] [PATCH v2 5/9] drm/i915/display: Fix glitches when moving cursor with PSR2 selective fetch enabled José Roberto de Souza
2021-09-30  7:56   ` Ville Syrjälä
2021-09-30 17:34     ` Gwan-gyeong Mun
2021-09-30  0:14 ` [Intel-gfx] [PATCH v2 6/9] drm/i915/display/adlp: Optimize PSR2 power-savings in corner cases José Roberto de Souza
2021-09-30  7:35   ` Gwan-gyeong Mun
2021-09-30 18:03     ` Souza, Jose
2021-09-30  0:14 ` [Intel-gfx] [PATCH v2 7/9] drm/i915/display/adlp: Allow PSR2 to be enabled José Roberto de Souza
2021-09-30  0:14 ` [Intel-gfx] [PATCH v2 8/9] drm/i915/display: Enable PSR2 selective fetch by default José Roberto de Souza
2021-09-30  0:14 ` [Intel-gfx] [PATCH v2 9/9] drm/i915/display: Always wait vblank counter to increment when commit needs a modeset José Roberto de Souza
2021-09-30  7:58   ` Ville Syrjälä
2021-09-30  0:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/9] drm/i915/display/psr: Handle plane and pipe restrictions at every page flip Patchwork
2021-09-30  0:47 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-30  2:05 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-30 16:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/9] drm/i915/display/psr: Handle plane and pipe restrictions at every page flip (rev2) Patchwork
2021-09-30 17:25 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-30 21:24 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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