From: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v2 6/9] drm/i915/display/adlp: Optimize PSR2 power-savings in corner cases
Date: Thu, 30 Sep 2021 10:35:59 +0300 [thread overview]
Message-ID: <f9b00ea2-0c2f-6727-f870-0119f0da6499@intel.com> (raw)
In-Reply-To: <20210930001409.254817-6-jose.souza@intel.com>
On 9/30/21 3:14 AM, José Roberto de Souza wrote:
> The Wa_14014971508 is required to fix scanout when a feature that i915
> do not support is enabled and this feature is not planned to be enabled
> for adlp.
>
> Keeping this workaround enabled can badly hurt power-savings when
> a full frame fetch is required(see psr2_sel_fetch_plane_state_supported()
> and psr2_sel_fetch_pipe_state_supported()).
>
> Here a example that could badly hurt power-savings, userspace does
> a page flip to a rotated plane, so CONTINUOS_FULL_FRAME set.
> But then for a whole 30 seconds nothing in the screen requires updates
> but because CONTINUOS_FULL_FRAME is set, it will not go into DC5/DC6.
>
> Reverting Wa_14014971508 fixes that, as only a single frame will be
> sent and then display can go to DC5/DC6 for those 30 seconds of
> idleness.
>
And add a little more explanation here.
DC6v is a power saving state where the display engine is powered off
when display enters PSR2 in the video playback.
And the Wa_14014971508 related to DC6v.
Reviewed-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> BSpec: 54369
> Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_psr.c | 11 +++--------
> 1 file changed, 3 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
> index e8af39591dfea..b37f123fe0c97 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -1499,15 +1499,10 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
>
> if (full_update) {
> /*
> - * Wa_14014971508:adlp
> - * SINGLE_FULL_FRAME bit is not hold in register so can not be
> - * restored by DMC, so using CONTINUOS_FULL_FRAME to mimic that
> + * Not applying Wa_14014971508:adlp as we do not support the
> + * feature that requires this workaround.
> */
> - if (IS_ALDERLAKE_P(dev_priv))
> - val |= ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME;
> - else
> - val |= PSR2_MAN_TRK_CTL_SF_SINGLE_FULL_FRAME;
> -
> + val |= man_trk_ctl_single_full_frame_bit_get(dev_priv);
> goto exit;
> }
>
>
next prev parent reply other threads:[~2021-09-30 7:36 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-30 0:14 [Intel-gfx] [PATCH v2 1/9] drm/i915/display/psr: Handle plane and pipe restrictions at every page flip José Roberto de Souza
2021-09-30 0:14 ` [Intel-gfx] [PATCH v2 2/9] drm/i915/display/psr: Do full fetch when handling multi-planar formats José Roberto de Souza
2021-09-30 12:58 ` Ville Syrjälä
2021-09-30 0:14 ` [Intel-gfx] [PATCH v2 3/9] drm/i915/display: Drop unnecessary frontbuffer flushes José Roberto de Souza
2021-09-30 7:41 ` Ville Syrjälä
2021-09-30 0:14 ` [Intel-gfx] [PATCH v2 4/9] drm/i915/display: Handle frontbuffer rendering when PSR2 selective fetch is enabled José Roberto de Souza
2021-09-30 7:17 ` Gwan-gyeong Mun
2021-09-30 18:02 ` Souza, Jose
2021-09-30 0:14 ` [Intel-gfx] [PATCH v2 5/9] drm/i915/display: Fix glitches when moving cursor with PSR2 selective fetch enabled José Roberto de Souza
2021-09-30 7:56 ` Ville Syrjälä
2021-09-30 17:34 ` Gwan-gyeong Mun
2021-09-30 0:14 ` [Intel-gfx] [PATCH v2 6/9] drm/i915/display/adlp: Optimize PSR2 power-savings in corner cases José Roberto de Souza
2021-09-30 7:35 ` Gwan-gyeong Mun [this message]
2021-09-30 18:03 ` Souza, Jose
2021-09-30 0:14 ` [Intel-gfx] [PATCH v2 7/9] drm/i915/display/adlp: Allow PSR2 to be enabled José Roberto de Souza
2021-09-30 0:14 ` [Intel-gfx] [PATCH v2 8/9] drm/i915/display: Enable PSR2 selective fetch by default José Roberto de Souza
2021-09-30 0:14 ` [Intel-gfx] [PATCH v2 9/9] drm/i915/display: Always wait vblank counter to increment when commit needs a modeset José Roberto de Souza
2021-09-30 7:58 ` Ville Syrjälä
2021-09-30 0:19 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/9] drm/i915/display/psr: Handle plane and pipe restrictions at every page flip Patchwork
2021-09-30 0:47 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-30 2:05 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-09-30 16:57 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for series starting with [v2,1/9] drm/i915/display/psr: Handle plane and pipe restrictions at every page flip (rev2) Patchwork
2021-09-30 17:25 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2021-09-30 21:24 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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