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From: "Govindapillai, Vinod" <vinod.govindapillai@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 3/6] drm/i915: Treat SAGV block time 0 as SAGV disabled
Date: Wed, 9 Mar 2022 11:29:37 +0000	[thread overview]
Message-ID: <7eff18fd44e1d44f6d014cacfd4db992444a0051.camel@intel.com> (raw)
In-Reply-To: <20220308173230.4182-4-ville.syrjala@linux.intel.com>

On Tue, 2022-03-08 at 19:32 +0200, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> For modern platforms the spec explicitly states that a
> SAGV block time of zero means that SAGV is not supported.
> Let's extend that to all platforms. Supposedly there should
> be no systems where this isn't true, and it'll allow us to:
> - use the same code regardless of older vs. newer platform
> - wm latencies already treat 0 as disabled, so this fits well
>   with other related code
> - make it a bit more clear when SAGV is used vs. not
> - avoid overflows from adding U32_MAX with a u16 wm0 latency value
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_pm.c | 14 ++++++++------
>  1 file changed, 8 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 21c37115c36e..906501d6b298 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3682,7 +3682,7 @@ intel_sagv_block_time(struct drm_i915_private *dev_priv)
>  				     &val, NULL);
>  		if (ret) {
>  			drm_dbg_kms(&dev_priv->drm, "Couldn't read SAGV block time!\n");
> -			return -1;
> +			return 0;
>  		}
>  
>  		return val;
> @@ -3691,8 +3691,7 @@ intel_sagv_block_time(struct drm_i915_private *dev_priv)
>  	} else if (DISPLAY_VER(dev_priv) == 9 && !IS_LP(dev_priv)) {
>  		return 30;
>  	} else {
> -		/* Default to an unusable block time */
> -		return -1;
> +		return 0;
>  	}
>  }
>  
> @@ -3704,7 +3703,7 @@ static void intel_sagv_init(struct drm_i915_private *i915)
>  		    str_yes_no(intel_has_sagv(i915)), i915->sagv_block_time_us);
>  
>  	if (!intel_has_sagv(i915))
> -		i915->sagv_block_time_us = -1;
> +		i915->sagv_block_time_us = 0;

Hi Ville

Currently we set the "sagv_status" as "I915_SAGV_NOT_CONTROLLED" based on the number of qgv points.
So here i915->sagv_block_time_us will be set to 0 even if intel_sagv_block_time(i915) would have
returned some valid values. Is that the desired behavior for sgav watermarks calcultations? 

BR
vinod

>  }
>  
>  /*
> @@ -5651,7 +5650,7 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
>  	result->min_ddb_alloc = max(min_ddb_alloc, blocks) + 1;
>  	result->enable = true;
>  
> -	if (DISPLAY_VER(dev_priv) < 12)
> +	if (DISPLAY_VER(dev_priv) < 12 && dev_priv->sagv_block_time_us)
>  		result->can_sagv = latency >= dev_priv->sagv_block_time_us;
>  }
>  
> @@ -5684,7 +5683,10 @@ static void tgl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	struct skl_wm_level *sagv_wm = &plane_wm->sagv.wm0;
>  	struct skl_wm_level *levels = plane_wm->wm;
> -	unsigned int latency = dev_priv->wm.skl_latency[0] + dev_priv->sagv_block_time_us;
> +	unsigned int latency = 0;
> +
> +	if (dev_priv->sagv_block_time_us)
> +		latency = dev_priv->sagv_block_time_us + dev_priv->wm.skl_latency[0];
>  
>  	skl_compute_plane_wm(crtc_state, plane, 0, latency,
>  			     wm_params, &levels[0],

  reply	other threads:[~2022-03-09 11:29 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-08 17:32 [Intel-gfx] [PATCH 0/6] drm/i915: SAGV block time fixes Ville Syrjala
2022-03-08 17:32 ` [Intel-gfx] [PATCH 1/6] drm/i915: Remove leftover cnl SAGV block time Ville Syrjala
2022-03-09 10:24   ` Govindapillai, Vinod
2022-03-08 17:32 ` [Intel-gfx] [PATCH 2/6] drm/i915: Rework SAGV block time probing Ville Syrjala
2022-03-09 10:41   ` Govindapillai, Vinod
2022-03-09 12:59     ` Ville Syrjälä
2022-03-08 17:32 ` [Intel-gfx] [PATCH 3/6] drm/i915: Treat SAGV block time 0 as SAGV disabled Ville Syrjala
2022-03-09 11:29   ` Govindapillai, Vinod [this message]
2022-03-09 13:00     ` Ville Syrjälä
2022-03-08 17:32 ` [Intel-gfx] [PATCH 4/6] drm/i915: Probe whether SAGV works on pre-icl Ville Syrjala
2022-03-08 17:32 ` [Intel-gfx] [PATCH 5/6] drm/i915: Reject excessive SAGV block time Ville Syrjala
2022-03-08 17:32 ` [Intel-gfx] [PATCH 6/6] drm/i915: Rename pre-icl SAGV enable/disable functions Ville Syrjala
2022-03-09  2:45 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: SAGV block time fixes Patchwork
2022-03-09 10:52 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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