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* [Intel-gfx] [PATCH 1/2] drm/i915: Fix ICL MG PHY vswing handling
@ 2020-12-07 20:35 Ville Syrjala
  2020-12-07 20:35 ` [Intel-gfx] [PATCH 2/2] drm/i915: Unify the sanity checks for the buf trans tables Ville Syrjala
                   ` (5 more replies)
  0 siblings, 6 replies; 8+ messages in thread
From: Ville Syrjala @ 2020-12-07 20:35 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The MH PHY vswing table does have all the entries these days. Get
rid of the old hacks in the code which claim otherwise.

This hack was totally bogus anyway. The correct way to handle the
lack of those two entries would have been to declare our max
vswing and pre-emph to both be level 2.

Cc: José Roberto de Souza <jose.souza@intel.com>
Cc: Clinton Taylor <clinton.a.taylor@intel.com>
Fixes: 9f7ffa297978 ("drm/i915/tc/icl: Update TC vswing tables")
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 5193473c838c..c3a15ce66478 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2760,12 +2760,11 @@ static void icl_mg_phy_ddi_vswing_sequence(struct intel_encoder *encoder,
 	u32 val;
 
 	ddi_translations = icl_get_mg_buf_trans(encoder, crtc_state, &n_entries);
-	/* The table does not have values for level 3 and level 9. */
-	if (level >= n_entries || level == 3 || level == 9) {
+	if (level >= n_entries) {
 		drm_dbg_kms(&dev_priv->drm,
 			    "DDI translation not found for level %d. Using %d instead.",
-			    level, n_entries - 2);
-		level = n_entries - 2;
+			    level, n_entries - 1);
+		level = n_entries - 1;
 	}
 
 	/* Set MG_TX_LINK_PARAMS cri_use_fs32 to 0. */
-- 
2.26.2

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^ permalink raw reply related	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2021-01-20 19:22 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2020-12-07 20:35 [Intel-gfx] [PATCH 1/2] drm/i915: Fix ICL MG PHY vswing handling Ville Syrjala
2020-12-07 20:35 ` [Intel-gfx] [PATCH 2/2] drm/i915: Unify the sanity checks for the buf trans tables Ville Syrjala
2021-01-20 19:22   ` Souza, Jose
2020-12-07 21:26 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: Fix ICL MG PHY vswing handling Patchwork
2020-12-14 16:27 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [1/2] drm/i915: Fix ICL MG PHY vswing handling (rev2) Patchwork
2020-12-14 16:53 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-12-14 19:46 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2021-01-20 19:19 ` [Intel-gfx] [PATCH 1/2] drm/i915: Fix ICL MG PHY vswing handling Souza, Jose

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