Re: [PATCH v2] drm/i915/icl: Whitelist GEN9_SLICE_COMMON_ECO_CHICKEN1

[Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>]

On 26/04/2019 17:58, Anuj Phogat wrote:
> 
> Joonas,
> 
> Mesa now applies this WA on ICL and we're not seeing any regressions in CI.
> I tested Mesa with and without this patch applied to kernel. I don't see 
> any
> performance impact to Manhattan from GfxBench5. I'm little surprised to
> see it's not really helping benchmark performance in Mesa. I'll dig bit 
> more
> to figure out a possible explanation. I haven't tried any other benchmarks
> with this patch.

I think the concern was, if user is running old Mesa (no WA) on new 
kernel (no WA) there wouldn't be any GPU hangs, just theoretical (yet 
unmeasured) perf drop?

Regards,

Tvrtko

> 
> Thanks
> Anuj
> On 04/26/2019 01:31 AM, Joonas Lahtinen wrote:
>> + Anuj
>>
>> Quoting Lionel Landwerlin (2019-04-26 11:13:58)
>>> On 18/04/2019 18:06, Tvrtko Ursulin wrote:
>>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>
>>>> WaEnableStateCacheRedirectToCS context workaround configures the L3 
>>>> cache
>>>> to benefit 3d workloads but media has different requirements.
>>>>
>>>> Remove the workaround and whitelist the register to allow any userspace
>>>> configure the behaviour to their liking.
>>>>
>>>> v2:
>>>>    * Remove the workaround apart from adding the whitelist.
>>>>
>>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>>>> Cc: kevin.ma@intel.com
>>>> Cc: xiaogang.li@intel.com
>>>
>>> Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>>>
>>>
>>> Mesa commits :
>>>
>>> commit db5b372bb9f5a0dfea86618f8f9832f25d9eaf71 (anv)
>>>
>>> commit eaadb62c9ea98f841d7ffc26c14341abdf84d2d6 (i965)
>>>
>>> commit d1be67db39463b48369cb71979ed18662b2c157e (iris)
>> Could somebody confirm that applying this patch does not cause hangs in
>> older mesa, and the performance drop (if any) is insignificant?
>>
>> Best Regards,
>> Joonas
> 
> 
> 
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