Re: [Intel-gfx] [PATCH] drm/1915/guc: enable engine reset on CAT

[John Harrison <john.c.harrison@intel.com>]

On 10/13/2022 09:14, Andrzej Hajda wrote:
> In case of catastrophic errors GuC is able to initate engine
> reset immediately, instead of waiting for timeout.
>
> Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
> ---
> Hi all,
>
> I am new in the subject, so please be polite if this is mistake.
> Tests shows that it allows to save about 7 seconds on the machine
> (Raptor Lake) in case of CAT.
> I am not aware of scenario in which would be reasonable to keep
> the engine in hung state.
> On the other side I am not sure if there should not be constraints
> on firmware version.
Technically there is. The feature was added in GuC v67. At present the 
earliest supported firmware version is 69 so it won't actually cause a 
break (or at least, not a new break). However, there is a task in 
progress to re-add support for v62 because 62 is out in the wild. So 
this change should really be wrapped with:
         if (GET_UC_VER(guc) >= MAKE_UC_VER(67, 0, 0))

There is also a potential impact for SRIOV customers. If one KMD wants 
reset-on-fault but another KMD (e.g. Windows) does not, that would be a 
problem. Will need to discuss this with the Windows team.

John.

>
> Regards
> Andrzej
> ---
>   drivers/gpu/drm/i915/gt/uc/intel_guc.c      | 2 +-
>   drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h | 1 +
>   2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> index 27b09ba1d295fc..2adcdf13db1911 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
> @@ -211,7 +211,7 @@ static u32 guc_ctl_debug_flags(struct intel_guc *guc)
>   
>   static u32 guc_ctl_feature_flags(struct intel_guc *guc)
>   {
> -	u32 flags = 0;
> +	u32 flags = GUC_CTL_ENABLE_ENGINE_RESET_ON_CAT;
>   
>   	if (!intel_guc_submission_is_used(guc))
>   		flags |= GUC_CTL_DISABLE_SCHEDULER;
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> index e7a7fb450f442a..96f3116e263cdf 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h
> @@ -109,6 +109,7 @@
>   
>   #define GUC_CTL_FEATURE			2
>   #define   GUC_CTL_ENABLE_SLPC		BIT(2)
> +#define   GUC_CTL_ENABLE_ENGINE_RESET_ON_CAT BIT(8)
>   #define   GUC_CTL_DISABLE_SCHEDULER	BIT(14)
>   
>   #define GUC_CTL_DEBUG			3