[PATCH v3] drm/i915: Move to CPU domain in pwrite/pread

[PATCH v3] drm/i915: Move to CPU domain in pwrite/pread

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Currently it's possible to get visible cache dirt on scanout on LLC
machines when using pwrite on the future scanout bo if its cache_level
is already NONE.

pwrite's "does this need clflush?" checks would decide that no clflush
is necessary since the bo isn't currently pinned to the display and LLC
makes everything else coherent. The subsequent set_cache_level(NONE)
would also do nothing since cache_level is already correct. And hence
no clflush will be performed and we flip to a bo which can still have
dirty data in the caches.

To correctly track the cache dirtyness move the object to CPU write
domain in pwrite. This cures the cache dirt since we explicitly flush
the CPU write domain in the pin_to_display path.

Give pread the same treatment simply in the name of symmetry.

v2: Use trace_i915_gem_object_change_domain() and provide some kind
    of commit message
v3: Don't mark things as clean if we're not sure everything got
    flushed (Chris)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem.c | 39 ++++++++++++++++++++++++++++++++++++++-
 1 file changed, 38 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 3e0cabe..117b064 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -456,6 +456,7 @@ __copy_from_user_swizzled(char *gpu_vaddr, int gpu_offset,
 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
 				    int *needs_clflush)
 {
+	u32 old_read_domains;
 	int ret;
 
 	*needs_clflush = 0;
@@ -475,6 +476,7 @@ int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
 			return ret;
 
 		i915_gem_object_retire(obj);
+		i915_gem_object_flush_gtt_write_domain(obj);
 	}
 
 	ret = i915_gem_object_get_pages(obj);
@@ -483,6 +485,13 @@ int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
 
 	i915_gem_object_pin_pages(obj);
 
+	old_read_domains = obj->base.read_domains;
+	obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
+
+	trace_i915_gem_object_change_domain(obj,
+					    old_read_domains,
+					    obj->base.write_domain);
+
 	return ret;
 }
 
@@ -875,6 +884,7 @@ i915_gem_shmem_pwrite(struct drm_device *dev,
 	int needs_clflush_after = 0;
 	int needs_clflush_before = 0;
 	struct sg_page_iter sg_iter;
+	u32 old_write_domain, old_read_domains;
 
 	user_data = to_user_ptr(args->data_ptr);
 	remain = args->size;
@@ -892,6 +902,7 @@ i915_gem_shmem_pwrite(struct drm_device *dev,
 			return ret;
 
 		i915_gem_object_retire(obj);
+		i915_gem_object_flush_gtt_write_domain(obj);
 	}
 	/* Same trick applies to invalidate partially written cachelines read
 	 * before writing. */
@@ -908,6 +919,15 @@ i915_gem_shmem_pwrite(struct drm_device *dev,
 	offset = args->offset;
 	obj->dirty = 1;
 
+	old_read_domains = obj->base.read_domains;
+	old_write_domain = obj->base.write_domain;
+	obj->base.read_domains = I915_GEM_DOMAIN_CPU;
+	obj->base.write_domain = I915_GEM_DOMAIN_CPU;
+
+	trace_i915_gem_object_change_domain(obj,
+					    old_read_domains,
+					    old_write_domain);
+
 	for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents,
 			 offset >> PAGE_SHIFT) {
 		struct page *page = sg_page_iter_page(&sg_iter);
@@ -978,9 +998,26 @@ out:
 		}
 	}
 
-	if (needs_clflush_after)
+	if (needs_clflush_after) {
 		i915_gem_chipset_flush(dev);
 
+		/*
+		 * If the caches were clean in the start they should
+		 * still be clean due to the clflushes we did. Otherwise
+		 * we may not have flushed all the dirty cachelines and
+		 * thus must leave write_domain alone.
+		 */
+		if (old_write_domain != I915_GEM_DOMAIN_CPU &&
+		    obj->base.write_domain == I915_GEM_DOMAIN_CPU) {
+			old_write_domain = obj->base.write_domain;
+			obj->base.write_domain = 0;
+
+			trace_i915_gem_object_change_domain(obj,
+							    obj->base.read_domains,
+							    old_write_domain);
+		}
+	}
+
 	return ret;
 }
 
-- 
2.0.4

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Re: [PATCH v3] drm/i915: Move to CPU domain in pwrite/pread

[shuang.he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com)
-------------------------------------Summary-------------------------------------
Platform: baseline_drm_intel_nightly_pass_rate->patch_applied_pass_rate
BYT: pass/total=291/291->284/291
PNV: pass/total=356/356->350/356
ILK: pass/total=372/372->365/372
IVB: pass/total=544/546->545/546
SNB: pass/total=378/380->379/380
HSW: pass/total=579/579->577/579
BDW: pass/total=433/435->434/435
-------------------------------------Detailed-------------------------------------
test_platform: test_suite, test_case, result_with_drm_intel_nightly(count, machine_id...)...->result_with_patch_applied(count, machine_id)...
BYT: Intel_gpu_tools, igt_gem_pread_after_blit_interruptible, FAIL(3, M36)PASS(1, M38) -> FAIL(1, M36)PASS(3, M36)
BYT: Intel_gpu_tools, igt_gem_pread_after_blit_interruptible-display, FAIL(3, M36)PASS(1, M38) -> FAIL(1, M36)PASS(3, M36)
BYT: Intel_gpu_tools, igt_gem_pread_after_blit_interruptible-uncached, FAIL(2, M36)CRASH(1, M36)PASS(1, M38) -> FAIL(1, M36)PASS(3, M36)
BYT: Intel_gpu_tools, igt_gem_pread_after_blit_normal, FAIL(3, M36)PASS(1, M38) -> FAIL(1, M36)PASS(3, M36)
BYT: Intel_gpu_tools, igt_gem_pread_after_blit_normal-display, FAIL(3, M36)PASS(1, M38) -> FAIL(1, M36)PASS(3, M36)
BYT: Intel_gpu_tools, igt_gem_pread_after_blit_normal-uncached, FAIL(3, M36)PASS(1, M38) -> FAIL(1, M36)PASS(3, M36)
BYT: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, TIMEOUT(3, M36)PASS(1, M38) -> TIMEOUT(4, M36)
PNV: Intel_gpu_tools, igt_gem_pread_after_blit_interruptible, FAIL(3, M24)PASS(1, M23) -> FAIL(1, M24)PASS(3, M24)
PNV: Intel_gpu_tools, igt_gem_pread_after_blit_interruptible-display, FAIL(3, M24)PASS(1, M23) -> FAIL(1, M24)PASS(3, M24)
PNV: Intel_gpu_tools, igt_gem_pread_after_blit_interruptible-uncached, FAIL(3, M24)PASS(1, M23) -> FAIL(1, M24)PASS(3, M24)
PNV: Intel_gpu_tools, igt_gem_pread_after_blit_normal, FAIL(3, M24)PASS(1, M23) -> FAIL(1, M24)DMESG_WARN(1, M24)PASS(2, M24)
PNV: Intel_gpu_tools, igt_gem_pread_after_blit_normal-display, FAIL(3, M24)PASS(1, M23) -> FAIL(1, M24)PASS(3, M24)
PNV: Intel_gpu_tools, igt_gem_pread_after_blit_normal-uncached, FAIL(3, M24)PASS(1, M23) -> FAIL(1, M24)PASS(3, M24)
ILK: Intel_gpu_tools, igt_gem_pread_after_blit_interruptible, FAIL(3, M37)PASS(1, M6) -> FAIL(1, M37)PASS(3, M37)
ILK: Intel_gpu_tools, igt_gem_pread_after_blit_interruptible-display, FAIL(3, M37)PASS(1, M6) -> FAIL(1, M37)PASS(3, M37)
ILK: Intel_gpu_tools, igt_gem_pread_after_blit_interruptible-uncached, FAIL(3, M37)PASS(1, M6) -> FAIL(1, M37)PASS(3, M37)
ILK: Intel_gpu_tools, igt_gem_pread_after_blit_normal, FAIL(3, M37)PASS(1, M6) -> FAIL(1, M37)PASS(3, M37)
ILK: Intel_gpu_tools, igt_gem_pread_after_blit_normal-display, FAIL(3, M37)PASS(1, M6) -> FAIL(1, M37)PASS(3, M37)
ILK: Intel_gpu_tools, igt_gem_pread_after_blit_normal-uncached, FAIL(3, M37)PASS(1, M6) -> FAIL(1, M37)PASS(3, M37)
ILK: Intel_gpu_tools, igt_kms_setmode_invalid-clone-single-crtc, FAIL(3, M26)DMESG_FAIL(1, M26)TIMEOUT(17, M37M6M26)PASS(1, M26) -> TIMEOUT(4, M37)
IVB: Intel_gpu_tools, igt_gem_bad_reloc_negative-reloc, NSPT(2, M4M21)PASS(2, M21) -> NSPT(1, M21)PASS(3, M21)
SNB: Intel_gpu_tools, igt_gem_concurrent_blit_gpuX-bcs-overwrite-source-forked, FAIL(1, M22)PASS(3, M35) -> PASS(4, M35)
HSW: Intel_gpu_tools, igt_kms_flip_tiling_flip-changes-tiling, PASS(4, M39) -> DMESG_WARN(1, M39)PASS(3, M39)
HSW: Intel_gpu_tools, igt_pm_rpm_fences-dpms, PASS(4, M39) -> DMESG_WARN(1, M39)PASS(3, M39)
BDW: Intel_gpu_tools, igt_gem_reset_stats_ban-bsd, DMESG_WARN(1, M30)PASS(3, M30) -> PASS(4, M30)
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[PATCH i-g-t] tests/kms_pwrite_crc: Add pwrite vs display coherency test

[ville.syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Add a test to verify that pwriting to a future scanout buffer works
correctly. The specific problem occurs when the buffer is already
UC/WT before the pwrite, not the current scanout buffer, and not
currently in the CPU write domain. With the buggy kernel no clflush
will be performed after the pwrite, and hence we end up with cache
dirt on the display.

The problem only affects LLC platforms (non-LLC would clflush anywway
after pwrite), but we can let th test run on all platforms.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 tests/Makefile.sources |   3 +-
 tests/kms_pwrite_crc.c | 217 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 219 insertions(+), 1 deletion(-)
 create mode 100644 tests/kms_pwrite_crc.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index afbe597..2677bf7 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -145,9 +145,10 @@ TESTS_progs = \
 	gen3_render_tiledy_blits \
 	gen7_forcewake_mt \
 	kms_3d \
+	kms_fence_pin_leak \
 	kms_force_connector \
+	kms_pwrite_crc \
 	kms_sink_crc_basic \
-	kms_fence_pin_leak \
 	prime_udl \
 	$(NULL)
 
diff --git a/tests/kms_pwrite_crc.c b/tests/kms_pwrite_crc.c
new file mode 100644
index 0000000..9c5dabf
--- /dev/null
+++ b/tests/kms_pwrite_crc.c
@@ -0,0 +1,217 @@
+/*
+ * Copyright © 2014 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ */
+
+#include <errno.h>
+#include <limits.h>
+#include <stdbool.h>
+#include <stdio.h>
+#include <string.h>
+
+#include "drmtest.h"
+#include "igt_debugfs.h"
+#include "igt_kms.h"
+#include "intel_chipset.h"
+#include "ioctl_wrappers.h"
+#include "igt_aux.h"
+
+IGT_TEST_DESCRIPTION(
+   "Use the display CRC support to validate pwrite to an already uncached future scanout buffer.");
+
+typedef struct {
+	int drm_fd;
+	igt_display_t display;
+	struct igt_fb fb[2];
+	igt_output_t *output;
+	igt_plane_t *primary;
+	enum pipe pipe;
+	igt_crc_t ref_crc;
+	igt_pipe_crc_t *pipe_crc;
+	uint32_t devid;
+} data_t;
+
+static void test(data_t *data)
+{
+	igt_display_t *display = &data->display;
+	igt_output_t *output = data->output;
+	struct igt_fb *fb = &data->fb[1];
+	drmModeModeInfo *mode;
+	cairo_t *cr;
+	uint32_t caching;
+	void *buf;
+	igt_crc_t crc;
+
+	mode = igt_output_get_mode(output);
+
+	/* create a non-white fb where we can pwrite later */
+	igt_create_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
+		      DRM_FORMAT_XRGB8888, I915_TILING_NONE, fb);
+
+	cr = igt_get_cairo_ctx(data->drm_fd, fb);
+	igt_paint_test_pattern(cr, fb->width, fb->height);
+	cairo_destroy(cr);
+
+	/* flip to it to make it UC/WC and fully flushed */
+	igt_plane_set_fb(data->primary, fb);
+	igt_display_commit(display);
+
+	/* sanity check to make sure crc changed */
+	igt_pipe_crc_collect_crc(data->pipe_crc, &crc);
+	igt_assert(!igt_crc_equal(&crc, &data->ref_crc));
+
+	/* flip back the original white buffer */
+	igt_plane_set_fb(data->primary, &data->fb[0]);
+	igt_display_commit(display);
+
+	/* make sure caching mode has become UC/WT */
+	caching = gem_get_caching(data->drm_fd, fb->gem_handle);
+	igt_assert(caching == I915_CACHING_NONE || caching == I915_CACHING_DISPLAY);
+
+	/* use pwrite to make the other fb all white too */
+	buf = malloc(fb->size);
+	igt_assert(buf != NULL);
+	memset(buf, 0xff, fb->size);
+	gem_write(data->drm_fd, fb->gem_handle, 0, buf, fb->size);
+	free(buf);
+
+	/* and flip to it */
+	igt_plane_set_fb(data->primary, fb);
+	igt_display_commit(display);
+
+	/* check that the crc is as expected, which requires that caches got flushed */
+	igt_pipe_crc_collect_crc(data->pipe_crc, &crc);
+	igt_assert(igt_crc_equal(&crc, &data->ref_crc));
+}
+
+static bool prepare_crtc(data_t *data)
+{
+	igt_display_t *display = &data->display;
+	igt_output_t *output = data->output;
+	drmModeModeInfo *mode;
+
+	/* select the pipe we want to use */
+	igt_output_set_pipe(output, data->pipe);
+	igt_display_commit(display);
+
+	if (!output->valid) {
+		igt_output_set_pipe(output, PIPE_ANY);
+		igt_display_commit(display);
+		return false;
+	}
+
+	mode = igt_output_get_mode(output);
+
+	/* create a white reference fb and flip to it */
+	igt_create_color_fb(data->drm_fd, mode->hdisplay, mode->vdisplay,
+			    DRM_FORMAT_XRGB8888, I915_TILING_NONE,
+			    1.0, 1.0, 1.0, &data->fb[0]);
+
+	data->primary = igt_output_get_plane(output, IGT_PLANE_PRIMARY);
+
+	igt_plane_set_fb(data->primary, &data->fb[0]);
+	igt_display_commit(display);
+
+	if (data->pipe_crc)
+		igt_pipe_crc_free(data->pipe_crc);
+
+	data->pipe_crc = igt_pipe_crc_new(data->pipe,
+					  INTEL_PIPE_CRC_SOURCE_AUTO);
+	if (!data->pipe_crc) {
+		igt_info("auto crc not supported on this connector with pipe %i\n",
+			 data->pipe);
+		return false;
+	}
+
+	/* get reference crc for the white fb */
+	igt_pipe_crc_collect_crc(data->pipe_crc, &data->ref_crc);
+
+	return true;
+}
+
+static void cleanup_crtc(data_t *data)
+{
+	igt_display_t *display = &data->display;
+	igt_output_t *output = data->output;
+
+	igt_pipe_crc_free(data->pipe_crc);
+	data->pipe_crc = NULL;
+
+	igt_plane_set_fb(data->primary, NULL);
+
+	igt_output_set_pipe(output, PIPE_ANY);
+	igt_display_commit(display);
+
+	igt_remove_fb(data->drm_fd, &data->fb[0]);
+	igt_remove_fb(data->drm_fd, &data->fb[1]);
+
+}
+
+static void run_test(data_t *data)
+{
+	igt_display_t *display = &data->display;
+	igt_output_t *output;
+	enum pipe pipe;
+
+	for_each_connected_output(display, output) {
+		data->output = output;
+		for_each_pipe(display, pipe) {
+			data->pipe = pipe;
+
+			if (!prepare_crtc(data))
+				continue;
+
+			test(data);
+			cleanup_crtc(data);
+
+			/* once is enough */
+			return;
+		}
+	}
+
+	igt_skip("no valid crtc/connector combinations found\n");
+}
+
+static data_t data;
+
+igt_simple_main
+{
+	igt_skip_on_simulation();
+
+	igt_fixture {
+		data.drm_fd = drm_open_any_master();
+
+		data.devid = intel_get_drm_devid(data.drm_fd);
+
+		kmstest_set_vt_graphics_mode();
+
+		igt_require_pipe_crc();
+
+		igt_display_init(&data.display, data.drm_fd);
+	}
+
+	run_test(&data);
+
+	igt_fixture {
+		igt_display_fini(&data.display);
+	}
+}
-- 
2.0.4

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Re: [PATCH v3] drm/i915: Move to CPU domain in pwrite/pread

[Chris Wilson]

On Wed, Nov 12, 2014 at 11:47:14PM +0200, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Currently it's possible to get visible cache dirt on scanout on LLC
> machines when using pwrite on the future scanout bo if its cache_level
> is already NONE.
> 
> pwrite's "does this need clflush?" checks would decide that no clflush
> is necessary since the bo isn't currently pinned to the display and LLC
> makes everything else coherent. The subsequent set_cache_level(NONE)
> would also do nothing since cache_level is already correct. And hence
> no clflush will be performed and we flip to a bo which can still have
> dirty data in the caches.
> 
> To correctly track the cache dirtyness move the object to CPU write
> domain in pwrite. This cures the cache dirt since we explicitly flush
> the CPU write domain in the pin_to_display path.
> 
> Give pread the same treatment simply in the name of symmetry.
> 
> v2: Use trace_i915_gem_object_change_domain() and provide some kind
>     of commit message
> v3: Don't mark things as clean if we're not sure everything got
>     flushed (Chris)

I think we just want to be more conservative during clflushes after
pwrite:

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 557746b2b72b..e9f98531b9d2 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -75,7 +75,7 @@ static bool cpu_cache_is_coherent(struct drm_device *dev,
 
 static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
 {
-       if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
+       if (level != I915_CACHE_NONE)
                return true;
 
        return obj->pin_display;

-- 
Chris Wilson, Intel Open Source Technology Centre
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Re: [PATCH v3] drm/i915: Move to CPU domain in pwrite/pread

[Ville Syrjälä]

On Fri, Nov 14, 2014 at 05:00:59PM +0000, Chris Wilson wrote:
> On Wed, Nov 12, 2014 at 11:47:14PM +0200, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Currently it's possible to get visible cache dirt on scanout on LLC
> > machines when using pwrite on the future scanout bo if its cache_level
> > is already NONE.
> > 
> > pwrite's "does this need clflush?" checks would decide that no clflush
> > is necessary since the bo isn't currently pinned to the display and LLC
> > makes everything else coherent. The subsequent set_cache_level(NONE)
> > would also do nothing since cache_level is already correct. And hence
> > no clflush will be performed and we flip to a bo which can still have
> > dirty data in the caches.
> > 
> > To correctly track the cache dirtyness move the object to CPU write
> > domain in pwrite. This cures the cache dirt since we explicitly flush
> > the CPU write domain in the pin_to_display path.
> > 
> > Give pread the same treatment simply in the name of symmetry.
> > 
> > v2: Use trace_i915_gem_object_change_domain() and provide some kind
> >     of commit message
> > v3: Don't mark things as clean if we're not sure everything got
> >     flushed (Chris)
> 
> I think we just want to be more conservative during clflushes after
> pwrite:
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 557746b2b72b..e9f98531b9d2 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -75,7 +75,7 @@ static bool cpu_cache_is_coherent(struct drm_device *dev,
>  
>  static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
>  {
> -       if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
> +       if (level != I915_CACHE_NONE)

You mean == ?

And I guess you'd then have to consider WT as well.

It would mean we'd end up clflushing even when not strictly needed. But
maybe that's acceptable.

>                 return true;
>  
>         return obj->pin_display;
> 
> -- 
> Chris Wilson, Intel Open Source Technology Centre

-- 
Ville Syrjälä
Intel OTC
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Re: [PATCH v3] drm/i915: Move to CPU domain in pwrite/pread

[Chris Wilson]

On Fri, Nov 14, 2014 at 08:35:57PM +0200, Ville Syrjälä wrote:
> On Fri, Nov 14, 2014 at 05:00:59PM +0000, Chris Wilson wrote:
> > On Wed, Nov 12, 2014 at 11:47:14PM +0200, ville.syrjala@linux.intel.com wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Currently it's possible to get visible cache dirt on scanout on LLC
> > > machines when using pwrite on the future scanout bo if its cache_level
> > > is already NONE.
> > > 
> > > pwrite's "does this need clflush?" checks would decide that no clflush
> > > is necessary since the bo isn't currently pinned to the display and LLC
> > > makes everything else coherent. The subsequent set_cache_level(NONE)
> > > would also do nothing since cache_level is already correct. And hence
> > > no clflush will be performed and we flip to a bo which can still have
> > > dirty data in the caches.
> > > 
> > > To correctly track the cache dirtyness move the object to CPU write
> > > domain in pwrite. This cures the cache dirt since we explicitly flush
> > > the CPU write domain in the pin_to_display path.
> > > 
> > > Give pread the same treatment simply in the name of symmetry.
> > > 
> > > v2: Use trace_i915_gem_object_change_domain() and provide some kind
> > >     of commit message
> > > v3: Don't mark things as clean if we're not sure everything got
> > >     flushed (Chris)
> > 
> > I think we just want to be more conservative during clflushes after
> > pwrite:
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> > index 557746b2b72b..e9f98531b9d2 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -75,7 +75,7 @@ static bool cpu_cache_is_coherent(struct drm_device *dev,
> >  
> >  static bool cpu_write_needs_clflush(struct drm_i915_gem_object *obj)
> >  {
> > -       if (!cpu_cache_is_coherent(obj->base.dev, obj->cache_level))
> > +       if (level != I915_CACHE_NONE)
> 
> You mean == ?

Indeed.
 
> And I guess you'd then have to consider WT as well.
> 
> It would mean we'd end up clflushing even when not strictly needed. But
> maybe that's acceptable.

Yes. I think it is better to err on clflushing too often and worry later
if someone batters us over the head with a profile. The only mistake I
know about, in this regard, is my pwrite of the sprite planes and the
mmap(wc) fixes that, or I can flag those planes as fenced which may be
preferrable by hw (I didn't think so at the time)? The much more frequent
use case (and the only other one that immediately springs to mind) will
not trigger the clflushes.
-Chris

-- 
Chris Wilson, Intel Open Source Technology Centre
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