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From: Keith Packard <keithp@keithp.com>
To: Adam Jackson <ajax@redhat.com>, 4ernov <4ernov@gmail.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: Dear Intel: please document SDVO LVDS option block
Date: Mon, 28 Nov 2011 09:28:35 -0800	[thread overview]
Message-ID: <86ipm45f7g.fsf@sumi.keithp.com> (raw)
In-Reply-To: <1319640791.18349.10.camel@atropine>


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On Wed, 26 Oct 2011 10:53:11 -0400, Adam Jackson <ajax@redhat.com> wrote:
> On Wed, 2011-10-19 at 10:28 -0400, Adam Jackson wrote:
> 
> > I assume the SDVO LVDS options block in the VBT would tell us what bits
> > are correct to program here, but intel_bios.h documents only the layout
> > of that structure, not its content.  Or, we can hope that the SDVO card
> > set it up correctly for us (hah).
> > 
> > Intel people, care to shed some light here?
> 
> Just re-raising this.  I suspect we can't support SDVO LVDS correctly
> without knowing more here.  In particular:
> 
> - what "panel type" means in struct bdb_sdvo_lvds_options

Which of the four panels in the SDVO info is actually connected.

> - what the "misc bits" mean in same

LVDS_Misc_Bits_1
	Bits [7:6] = Reserved
	Bit 5 = Dither
		   = 0, off
		   = 1, on
	Bit 4 = Panel Fitting
	         = 0, Disabled
	         = 1, Enabled
	Bit 3 = Panel EDID support - Reserved 
	        = 0, Disabled
	        = 1, Enabled
	Bit 2 - 0 = Panel protection
	      Bit 2 -  Monitor Pixel Clk  (0 = off, 1 = on)
	      Bit 1 - Monitor VSync (0 = off, 1 = on)
	      Bit 0 - Monitor HSync (0 = off, 1 = on)	

LVDS_Misc_Bits_2
	Bit 7 = LVDS SSC Enabled
	         = 0, Disabled
	         = 1, Enabled
	Bit6 = Disable SSC in Dual Twin Display
	         = 0, Not disabled
	         = 1, Disabled
	Bits[5:4] = LVDS Channel
	         = 02-03, Reserved
	         = 01, Dual Channel
	         = 00, Single Channel       
	Bits[3:2] = Panel Connector
	         = 01, OpenLDI
	         = 00, SPGW       
	Bits[1:0] = Panel color depth
		   = 02-03, Reserved
	         = 01, 24-bit Color depth
	         = 00, 18-bit Color depth     

LVDS_Misc_Bits_3
	Bits [7:4] = Reserved
	Bit 3 = Panel #4
		  = 0, Single Channel
		  = 1, Dual Channel
	Bit 2 = Panel #3
		  = 0, Single Channel
		  = 1, Dual Channel
	Bit 1 = Panel #2
		  = 0, Single Channel
		  = 1, Dual Channel
	Bit 0 = Panel #1
		  = 0, Single Channel
		  = 1, Dual Channel


> - whether the BIOS AIM code can be relied on to have set
> depth/type/channel correctly or if that's the driver's job

That, I'm afraid, I haven't a clue about -- the BIOS does try to light
up every display, but it can run out of resources just like Linux, and I
don't know what happens when there's not enough pipes to go around.

-- 
keith.packard@intel.com

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  parent reply	other threads:[~2011-11-28 17:28 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-10-19  9:08 Where is SDVO mode setting code in kernel module sources? 4ernov
2011-10-19 13:39 ` Adam Jackson
2011-10-19 13:48   ` 4ernov
2011-10-19 14:28     ` Adam Jackson
2011-10-19 14:43       ` 4ernov
2011-10-19 15:02         ` Adam Jackson
2011-10-19 15:21           ` 4ernov
2011-10-26 14:53       ` Dear Intel: please document SDVO LVDS option block Adam Jackson
2011-10-27  6:49         ` 4ernov
2011-11-28 17:28         ` Keith Packard [this message]
2011-11-28 18:35           ` Adam Jackson
2011-11-28 18:56             ` 4ernov
2011-11-29  9:30               ` 4ernov

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